+#define REG_EDP_28nm_PHY_PLL_REFCLK_CFG 0x00000000
+
+#define REG_EDP_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
+
+#define REG_EDP_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
+
+#define REG_EDP_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
+
+#define REG_EDP_28nm_PHY_PLL_VREG_CFG 0x00000010
+
+#define REG_EDP_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
+
+#define REG_EDP_28nm_PHY_PLL_DMUX_CFG 0x00000018
+
+#define REG_EDP_28nm_PHY_PLL_AMUX_CFG 0x0000001c
+
+#define REG_EDP_28nm_PHY_PLL_GLB_CFG 0x00000020
+#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
+#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
+#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
+#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
+
+#define REG_EDP_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
+
+#define REG_EDP_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
+
+#define REG_EDP_28nm_PHY_PLL_LPFR_CFG 0x0000002c
+
+#define REG_EDP_28nm_PHY_PLL_LPFC1_CFG 0x00000030
+
+#define REG_EDP_28nm_PHY_PLL_LPFC2_CFG 0x00000034
+
+#define REG_EDP_28nm_PHY_PLL_SDM_CFG0 0x00000038
+
+#define REG_EDP_28nm_PHY_PLL_SDM_CFG1 0x0000003c
+
+#define REG_EDP_28nm_PHY_PLL_SDM_CFG2 0x00000040
+
+#define REG_EDP_28nm_PHY_PLL_SDM_CFG3 0x00000044
+
+#define REG_EDP_28nm_PHY_PLL_SDM_CFG4 0x00000048
+
+#define REG_EDP_28nm_PHY_PLL_SSC_CFG0 0x0000004c
+
+#define REG_EDP_28nm_PHY_PLL_SSC_CFG1 0x00000050
+
+#define REG_EDP_28nm_PHY_PLL_SSC_CFG2 0x00000054
+
+#define REG_EDP_28nm_PHY_PLL_SSC_CFG3 0x00000058
+
+#define REG_EDP_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
+
+#define REG_EDP_28nm_PHY_PLL_LKDET_CFG1 0x00000060
+
+#define REG_EDP_28nm_PHY_PLL_LKDET_CFG2 0x00000064
+
+#define REG_EDP_28nm_PHY_PLL_TEST_CFG 0x00000068
+#define EDP_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG0 0x0000006c
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG1 0x00000070
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG2 0x00000074
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG3 0x00000078
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG4 0x0000007c
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG5 0x00000080
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG6 0x00000084
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG7 0x00000088
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG8 0x0000008c
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG9 0x00000090
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG10 0x00000094
+
+#define REG_EDP_28nm_PHY_PLL_CAL_CFG11 0x00000098
+
+#define REG_EDP_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
+
+#define REG_EDP_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
+