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Upgrade to 4.4.50-rt62
[kvmfornfv.git]
/
kernel
/
drivers
/
clk
/
clk-qoriq.c
diff --git
a/kernel/drivers/clk/clk-qoriq.c
b/kernel/drivers/clk/clk-qoriq.c
index
7bc1c45
..
a5070f9
100644
(file)
--- a/
kernel/drivers/clk/clk-qoriq.c
+++ b/
kernel/drivers/clk/clk-qoriq.c
@@
-700,6
+700,7
@@
static struct clk * __init create_mux_common(struct clockgen *cg,
struct mux_hwclock *hwc,
const struct clk_ops *ops,
unsigned long min_rate,
struct mux_hwclock *hwc,
const struct clk_ops *ops,
unsigned long min_rate,
+ unsigned long max_rate,
unsigned long pct80_rate,
const char *fmt, int idx)
{
unsigned long pct80_rate,
const char *fmt, int idx)
{
@@
-728,6
+729,8
@@
static struct clk * __init create_mux_common(struct clockgen *cg,
continue;
if (rate < min_rate)
continue;
continue;
if (rate < min_rate)
continue;
+ if (rate > max_rate)
+ continue;
parent_names[j] = div->name;
hwc->parent_to_clksel[j] = i;
parent_names[j] = div->name;
hwc->parent_to_clksel[j] = i;
@@
-759,14
+762,18
@@
static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
struct mux_hwclock *hwc;
const struct clockgen_pll_div *div;
unsigned long plat_rate, min_rate;
struct mux_hwclock *hwc;
const struct clockgen_pll_div *div;
unsigned long plat_rate, min_rate;
- u64 pct80_rate;
+ u64
max_rate,
pct80_rate;
u32 clksel;
hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
if (!hwc)
return NULL;
u32 clksel;
hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
if (!hwc)
return NULL;
- hwc->reg = cg->regs + 0x20 * idx;
+ if (cg->info.flags & CG_VER3)
+ hwc->reg = cg->regs + 0x70000 + 0x20 * idx;
+ else
+ hwc->reg = cg->regs + 0x20 * idx;
+
hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
/*
hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
/*
@@
-783,8
+790,8
@@
static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
return NULL;
}
return NULL;
}
-
pct80
_rate = clk_get_rate(div->clk);
- pct80_rate
*=
8;
+
max
_rate = clk_get_rate(div->clk);
+ pct80_rate
= max_rate *
8;
do_div(pct80_rate, 10);
plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
do_div(pct80_rate, 10);
plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
@@
-794,7
+801,7
@@
static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
else
min_rate = plat_rate / 2;
else
min_rate = plat_rate / 2;
- return create_mux_common(cg, hwc, &cmux_ops, min_rate,
+ return create_mux_common(cg, hwc, &cmux_ops, min_rate,
max_rate,
pct80_rate, "cg-cmux%d", idx);
}
pct80_rate, "cg-cmux%d", idx);
}
@@
-809,7
+816,7
@@
static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
hwc->reg = cg->regs + 0x20 * idx + 0x10;
hwc->info = cg->info.hwaccel[idx];
hwc->reg = cg->regs + 0x20 * idx + 0x10;
hwc->info = cg->info.hwaccel[idx];
- return create_mux_common(cg, hwc, &hwaccel_ops, 0, 0,
+ return create_mux_common(cg, hwc, &hwaccel_ops, 0,
ULONG_MAX,
0,
"cg-hwaccel%d", idx);
}
"cg-hwaccel%d", idx);
}