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These changes are the raw update to linux-4.4.6-rt14. Kernel sources
[kvmfornfv.git]
/
kernel
/
arch
/
arm
/
boot
/
dts
/
stih418-clock.dtsi
diff --git
a/kernel/arch/arm/boot/dts/stih418-clock.dtsi
b/kernel/arch/arm/boot/dts/stih418-clock.dtsi
index
0ab23da
..
ae6d997
100644
(file)
--- a/
kernel/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/
kernel/arch/arm/boot/dts/stih418-clock.dtsi
@@
-44,7
+44,7
@@
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
- compatible = "st,stih4
07-plls-c32
-a9", "st,clkgen-plls-c32";
+ compatible = "st,stih4
18-plls-c28
-a9", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clocks = <&clk_sysin>;
@@
-137,7
+137,7
@@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,
stih407-plls-c32-c0
_0", "st,clkgen-plls-c32";
+ compatible = "st,
plls-c32-cx
_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clocks = <&clk_sysin>;
@@
-146,7
+146,7
@@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,
stih407-plls-c32-c0
_1", "st,clkgen-plls-c32";
+ compatible = "st,
plls-c32-cx
_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clocks = <&clk_sysin>;