4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
28 #include "ui/console.h"
29 #include "hw/i386/pc.h"
30 #include "hw/pci/pci.h"
32 #include "ui/pixel_ops.h"
33 #include "qemu/timer.h"
34 #include "hw/xen/xen.h"
38 //#define DEBUG_VGA_MEM
39 //#define DEBUG_VGA_REG
41 //#define DEBUG_BOCHS_VBE
43 /* 16 state changes per vertical frame @60 Hz */
44 #define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
47 * Video Graphics Array (VGA)
49 * Chipset docs for original IBM VGA:
50 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
53 * http://www.osdever.net/FreeVGA/home.htm
55 * Standard VGA features and Bochs VBE extensions are implemented.
58 /* force some bits to zero */
59 const uint8_t sr_mask[8] = {
70 const uint8_t gr_mask[16] = {
89 #define cbswap_32(__x) \
91 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
92 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
93 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
94 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
96 #ifdef HOST_WORDS_BIGENDIAN
97 #define PAT(x) cbswap_32(x)
102 #ifdef HOST_WORDS_BIGENDIAN
108 #ifdef HOST_WORDS_BIGENDIAN
109 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
111 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
114 static const uint32_t mask16[16] = {
135 #ifdef HOST_WORDS_BIGENDIAN
138 #define PAT(x) cbswap_32(x)
141 static uint32_t expand4[256];
142 static uint16_t expand2[256];
143 static uint8_t expand4to8[16];
145 static void vbe_update_vgaregs(VGACommonState *s);
147 static inline bool vbe_enabled(VGACommonState *s)
149 return s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED;
152 static void vga_update_memory_access(VGACommonState *s)
154 hwaddr base, offset, size;
156 if (s->legacy_address_space == NULL) {
160 if (s->has_chain4_alias) {
161 memory_region_del_subregion(s->legacy_address_space, &s->chain4_alias);
162 object_unparent(OBJECT(&s->chain4_alias));
163 s->has_chain4_alias = false;
164 s->plane_updated = 0xf;
166 if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) ==
167 VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
169 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
177 offset = s->bank_offset;
189 assert(offset + size <= s->vram_size);
190 memory_region_init_alias(&s->chain4_alias, memory_region_owner(&s->vram),
191 "vga.chain4", &s->vram, offset, size);
192 memory_region_add_subregion_overlap(s->legacy_address_space, base,
193 &s->chain4_alias, 2);
194 s->has_chain4_alias = true;
198 static void vga_dumb_update_retrace_info(VGACommonState *s)
203 static void vga_precise_update_retrace_info(VGACommonState *s)
206 int hretr_start_char;
207 int hretr_skew_chars;
211 int vretr_start_line;
220 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
221 int64_t chars_per_sec;
222 struct vga_precise_retrace *r = &s->retrace_info.precise;
224 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
225 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
226 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
227 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
229 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
230 (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
231 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
232 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
233 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
234 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
235 vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
237 clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1;
238 clock_sel = (s->msr >> 2) & 3;
239 dots = (s->msr & 1) ? 8 : 9;
241 chars_per_sec = clk_hz[clock_sel] / dots;
243 htotal_chars <<= clocking_mode;
245 r->total_chars = vtotal_lines * htotal_chars;
247 r->ticks_per_char = NANOSECONDS_PER_SECOND / (r->total_chars * r->freq);
249 r->ticks_per_char = NANOSECONDS_PER_SECOND / chars_per_sec;
252 r->vstart = vretr_start_line;
253 r->vend = r->vstart + vretr_end_line + 1;
255 r->hstart = hretr_start_char + hretr_skew_chars;
256 r->hend = r->hstart + hretr_end_char + 1;
257 r->htotal = htotal_chars;
260 div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
261 sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
271 "div2 = %d sldiv2 = %d\n"
272 "clocking_mode = %d\n"
273 "clock_sel = %d %d\n"
275 "ticks/char = %" PRId64 "\n"
277 (double) NANOSECONDS_PER_SECOND / (r->ticks_per_char * r->total_chars),
295 static uint8_t vga_precise_retrace(VGACommonState *s)
297 struct vga_precise_retrace *r = &s->retrace_info.precise;
298 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
300 if (r->total_chars) {
301 int cur_line, cur_line_char, cur_char;
304 cur_tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
306 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
307 cur_line = cur_char / r->htotal;
309 if (cur_line >= r->vstart && cur_line <= r->vend) {
310 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
312 cur_line_char = cur_char % r->htotal;
313 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
314 val |= ST01_DISP_ENABLE;
320 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
324 static uint8_t vga_dumb_retrace(VGACommonState *s)
326 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
329 int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
331 if (s->msr & VGA_MIS_COLOR) {
333 return (addr >= 0x3b0 && addr <= 0x3bf);
336 return (addr >= 0x3d0 && addr <= 0x3df);
340 uint32_t vga_ioport_read(void *opaque, uint32_t addr)
342 VGACommonState *s = opaque;
345 if (vga_ioport_invalid(s, addr)) {
350 if (s->ar_flip_flop == 0) {
357 index = s->ar_index & 0x1f;
358 if (index < VGA_ATT_C) {
371 val = s->sr[s->sr_index];
373 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
380 val = s->dac_write_index;
383 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
384 if (++s->dac_sub_index == 3) {
385 s->dac_sub_index = 0;
399 val = s->gr[s->gr_index];
401 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
410 val = s->cr[s->cr_index];
412 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
417 /* just toggle to fool polling */
418 val = s->st01 = s->retrace(s);
426 #if defined(DEBUG_VGA)
427 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
432 void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
434 VGACommonState *s = opaque;
437 /* check port range access depending on color/monochrome mode */
438 if (vga_ioport_invalid(s, addr)) {
442 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
447 if (s->ar_flip_flop == 0) {
451 index = s->ar_index & 0x1f;
453 case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
454 s->ar[index] = val & 0x3f;
457 s->ar[index] = val & ~0x10;
459 case VGA_ATC_OVERSCAN:
462 case VGA_ATC_PLANE_ENABLE:
463 s->ar[index] = val & ~0xc0;
466 s->ar[index] = val & ~0xf0;
468 case VGA_ATC_COLOR_PAGE:
469 s->ar[index] = val & ~0xf0;
475 s->ar_flip_flop ^= 1;
478 s->msr = val & ~0x10;
479 s->update_retrace_info(s);
482 s->sr_index = val & 7;
486 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
488 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
489 vbe_update_vgaregs(s);
490 if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
491 s->update_retrace_info(s);
493 vga_update_memory_access(s);
496 s->dac_read_index = val;
497 s->dac_sub_index = 0;
501 s->dac_write_index = val;
502 s->dac_sub_index = 0;
506 s->dac_cache[s->dac_sub_index] = val;
507 if (++s->dac_sub_index == 3) {
508 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
509 s->dac_sub_index = 0;
510 s->dac_write_index++;
514 s->gr_index = val & 0x0f;
518 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
520 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
521 vbe_update_vgaregs(s);
522 vga_update_memory_access(s);
531 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
533 /* handle CR0-7 protection */
534 if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
535 s->cr_index <= VGA_CRTC_OVERFLOW) {
536 /* can always write bit 4 of CR7 */
537 if (s->cr_index == VGA_CRTC_OVERFLOW) {
538 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
540 vbe_update_vgaregs(s);
544 s->cr[s->cr_index] = val;
545 vbe_update_vgaregs(s);
547 switch(s->cr_index) {
548 case VGA_CRTC_H_TOTAL:
549 case VGA_CRTC_H_SYNC_START:
550 case VGA_CRTC_H_SYNC_END:
551 case VGA_CRTC_V_TOTAL:
552 case VGA_CRTC_OVERFLOW:
553 case VGA_CRTC_V_SYNC_END:
555 s->update_retrace_info(s);
567 * Sanity check vbe register writes.
569 * As we don't have a way to signal errors to the guest in the bochs
570 * dispi interface we'll go adjust the registers to the closest valid
573 static void vbe_fixup_regs(VGACommonState *s)
575 uint16_t *r = s->vbe_regs;
576 uint32_t bits, linelength, maxy, offset;
578 if (!vbe_enabled(s)) {
579 /* vbe is turned off -- nothing to do */
584 switch (r[VBE_DISPI_INDEX_BPP]) {
590 bits = r[VBE_DISPI_INDEX_BPP];
596 bits = r[VBE_DISPI_INDEX_BPP] = 8;
601 r[VBE_DISPI_INDEX_XRES] &= ~7u;
602 if (r[VBE_DISPI_INDEX_XRES] == 0) {
603 r[VBE_DISPI_INDEX_XRES] = 8;
605 if (r[VBE_DISPI_INDEX_XRES] > VBE_DISPI_MAX_XRES) {
606 r[VBE_DISPI_INDEX_XRES] = VBE_DISPI_MAX_XRES;
608 r[VBE_DISPI_INDEX_VIRT_WIDTH] &= ~7u;
609 if (r[VBE_DISPI_INDEX_VIRT_WIDTH] > VBE_DISPI_MAX_XRES) {
610 r[VBE_DISPI_INDEX_VIRT_WIDTH] = VBE_DISPI_MAX_XRES;
612 if (r[VBE_DISPI_INDEX_VIRT_WIDTH] < r[VBE_DISPI_INDEX_XRES]) {
613 r[VBE_DISPI_INDEX_VIRT_WIDTH] = r[VBE_DISPI_INDEX_XRES];
617 linelength = r[VBE_DISPI_INDEX_VIRT_WIDTH] * bits / 8;
618 maxy = s->vbe_size / linelength;
619 if (r[VBE_DISPI_INDEX_YRES] == 0) {
620 r[VBE_DISPI_INDEX_YRES] = 1;
622 if (r[VBE_DISPI_INDEX_YRES] > VBE_DISPI_MAX_YRES) {
623 r[VBE_DISPI_INDEX_YRES] = VBE_DISPI_MAX_YRES;
625 if (r[VBE_DISPI_INDEX_YRES] > maxy) {
626 r[VBE_DISPI_INDEX_YRES] = maxy;
630 if (r[VBE_DISPI_INDEX_X_OFFSET] > VBE_DISPI_MAX_XRES) {
631 r[VBE_DISPI_INDEX_X_OFFSET] = VBE_DISPI_MAX_XRES;
633 if (r[VBE_DISPI_INDEX_Y_OFFSET] > VBE_DISPI_MAX_YRES) {
634 r[VBE_DISPI_INDEX_Y_OFFSET] = VBE_DISPI_MAX_YRES;
636 offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
637 offset += r[VBE_DISPI_INDEX_Y_OFFSET] * linelength;
638 if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
639 r[VBE_DISPI_INDEX_Y_OFFSET] = 0;
640 offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
641 if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
642 r[VBE_DISPI_INDEX_X_OFFSET] = 0;
647 /* update vga state */
648 r[VBE_DISPI_INDEX_VIRT_HEIGHT] = maxy;
649 s->vbe_line_offset = linelength;
650 s->vbe_start_addr = offset / 4;
653 /* we initialize the VGA graphic mode */
654 static void vbe_update_vgaregs(VGACommonState *s)
656 int h, shift_control;
658 if (!vbe_enabled(s)) {
659 /* vbe is turned off -- nothing to do */
663 /* graphic mode + memory map 1 */
664 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
665 VGA_GR06_GRAPHICS_MODE;
666 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
667 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
669 s->cr[VGA_CRTC_H_DISP] =
670 (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
671 /* height (only meaningful if < 1024) */
672 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
673 s->cr[VGA_CRTC_V_DISP_END] = h;
674 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
675 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
676 /* line compare to 1023 */
677 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
678 s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
679 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
681 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
683 s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
686 /* set chain 4 mode */
687 s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
688 /* activate all planes */
689 s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
691 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
692 (shift_control << 5);
693 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
696 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
698 VGACommonState *s = opaque;
704 uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
706 VGACommonState *s = opaque;
709 if (s->vbe_index < VBE_DISPI_INDEX_NB) {
710 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
711 switch(s->vbe_index) {
712 /* XXX: do not hardcode ? */
713 case VBE_DISPI_INDEX_XRES:
714 val = VBE_DISPI_MAX_XRES;
716 case VBE_DISPI_INDEX_YRES:
717 val = VBE_DISPI_MAX_YRES;
719 case VBE_DISPI_INDEX_BPP:
720 val = VBE_DISPI_MAX_BPP;
723 val = s->vbe_regs[s->vbe_index];
727 val = s->vbe_regs[s->vbe_index];
729 } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
730 val = s->vbe_size / (64 * 1024);
734 #ifdef DEBUG_BOCHS_VBE
735 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
740 void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
742 VGACommonState *s = opaque;
746 void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
748 VGACommonState *s = opaque;
750 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
751 #ifdef DEBUG_BOCHS_VBE
752 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
754 switch(s->vbe_index) {
755 case VBE_DISPI_INDEX_ID:
756 if (val == VBE_DISPI_ID0 ||
757 val == VBE_DISPI_ID1 ||
758 val == VBE_DISPI_ID2 ||
759 val == VBE_DISPI_ID3 ||
760 val == VBE_DISPI_ID4) {
761 s->vbe_regs[s->vbe_index] = val;
764 case VBE_DISPI_INDEX_XRES:
765 case VBE_DISPI_INDEX_YRES:
766 case VBE_DISPI_INDEX_BPP:
767 case VBE_DISPI_INDEX_VIRT_WIDTH:
768 case VBE_DISPI_INDEX_X_OFFSET:
769 case VBE_DISPI_INDEX_Y_OFFSET:
770 s->vbe_regs[s->vbe_index] = val;
772 vbe_update_vgaregs(s);
774 case VBE_DISPI_INDEX_BANK:
775 val &= s->vbe_bank_mask;
776 s->vbe_regs[s->vbe_index] = val;
777 s->bank_offset = (val << 16);
778 vga_update_memory_access(s);
780 case VBE_DISPI_INDEX_ENABLE:
781 if ((val & VBE_DISPI_ENABLED) &&
782 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
784 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = 0;
785 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
786 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
787 s->vbe_regs[VBE_DISPI_INDEX_ENABLE] |= VBE_DISPI_ENABLED;
789 vbe_update_vgaregs(s);
791 /* clear the screen */
792 if (!(val & VBE_DISPI_NOCLEARMEM)) {
793 memset(s->vram_ptr, 0,
794 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
799 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
800 s->vbe_regs[s->vbe_index] = val;
801 vga_update_memory_access(s);
809 /* called for accesses between 0xa0000 and 0xc0000 */
810 uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
812 int memory_map_mode, plane;
815 /* convert to VGA memory offset */
816 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
818 switch(memory_map_mode) {
824 addr += s->bank_offset;
839 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
840 /* chain 4 mode : simplest access */
841 assert(addr < s->vram_size);
842 ret = s->vram_ptr[addr];
843 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
844 /* odd/even mode (aka text mode mapping) */
845 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
846 addr = ((addr & ~1) << 1) | plane;
847 if (addr >= s->vram_size) {
850 ret = s->vram_ptr[addr];
852 /* standard VGA latched access */
853 if (addr * sizeof(uint32_t) >= s->vram_size) {
856 s->latch = ((uint32_t *)s->vram_ptr)[addr];
858 if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
860 plane = s->gr[VGA_GFX_PLANE_READ];
861 ret = GET_PLANE(s->latch, plane);
864 ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
865 mask16[s->gr[VGA_GFX_COMPARE_MASK]];
874 /* called for accesses between 0xa0000 and 0xc0000 */
875 void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
877 int memory_map_mode, plane, write_mode, b, func_select, mask;
878 uint32_t write_mask, bit_mask, set_mask;
881 printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
883 /* convert to VGA memory offset */
884 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
886 switch(memory_map_mode) {
892 addr += s->bank_offset;
907 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
908 /* chain 4 mode : simplest access */
911 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
912 assert(addr < s->vram_size);
913 s->vram_ptr[addr] = val;
915 printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
917 s->plane_updated |= mask; /* only used to detect font change */
918 memory_region_set_dirty(&s->vram, addr, 1);
920 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
921 /* odd/even mode (aka text mode mapping) */
922 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
924 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
925 addr = ((addr & ~1) << 1) | plane;
926 if (addr >= s->vram_size) {
929 s->vram_ptr[addr] = val;
931 printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
933 s->plane_updated |= mask; /* only used to detect font change */
934 memory_region_set_dirty(&s->vram, addr, 1);
937 /* standard VGA latched access */
938 write_mode = s->gr[VGA_GFX_MODE] & 3;
943 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
944 val = ((val >> b) | (val << (8 - b))) & 0xff;
948 /* apply set/reset mask */
949 set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
950 val = (val & ~set_mask) |
951 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
952 bit_mask = s->gr[VGA_GFX_BIT_MASK];
958 val = mask16[val & 0x0f];
959 bit_mask = s->gr[VGA_GFX_BIT_MASK];
963 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
964 val = (val >> b) | (val << (8 - b));
966 bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
967 val = mask16[s->gr[VGA_GFX_SR_VALUE]];
971 /* apply logical operation */
972 func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
973 switch(func_select) {
993 bit_mask |= bit_mask << 8;
994 bit_mask |= bit_mask << 16;
995 val = (val & bit_mask) | (s->latch & ~bit_mask);
998 /* mask data according to sr[2] */
999 mask = s->sr[VGA_SEQ_PLANE_WRITE];
1000 s->plane_updated |= mask; /* only used to detect font change */
1001 write_mask = mask16[mask];
1002 if (addr * sizeof(uint32_t) >= s->vram_size) {
1005 ((uint32_t *)s->vram_ptr)[addr] =
1006 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
1008 #ifdef DEBUG_VGA_MEM
1009 printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
1010 addr * 4, write_mask, val);
1012 memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
1016 typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
1017 const uint8_t *s, int width);
1019 #include "vga-helpers.h"
1021 /* return true if the palette was modified */
1022 static int update_palette16(VGACommonState *s)
1025 uint32_t v, col, *palette;
1028 palette = s->last_palette;
1029 for(i = 0; i < 16; i++) {
1031 if (s->ar[VGA_ATC_MODE] & 0x80) {
1032 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
1034 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
1037 col = rgb_to_pixel32(c6_to_8(s->palette[v]),
1038 c6_to_8(s->palette[v + 1]),
1039 c6_to_8(s->palette[v + 2]));
1040 if (col != palette[i]) {
1048 /* return true if the palette was modified */
1049 static int update_palette256(VGACommonState *s)
1052 uint32_t v, col, *palette;
1055 palette = s->last_palette;
1057 for(i = 0; i < 256; i++) {
1059 col = rgb_to_pixel32(s->palette[v],
1063 col = rgb_to_pixel32(c6_to_8(s->palette[v]),
1064 c6_to_8(s->palette[v + 1]),
1065 c6_to_8(s->palette[v + 2]));
1067 if (col != palette[i]) {
1076 static void vga_get_offsets(VGACommonState *s,
1077 uint32_t *pline_offset,
1078 uint32_t *pstart_addr,
1079 uint32_t *pline_compare)
1081 uint32_t start_addr, line_offset, line_compare;
1083 if (vbe_enabled(s)) {
1084 line_offset = s->vbe_line_offset;
1085 start_addr = s->vbe_start_addr;
1086 line_compare = 65535;
1088 /* compute line_offset in bytes */
1089 line_offset = s->cr[VGA_CRTC_OFFSET];
1092 /* starting address */
1093 start_addr = s->cr[VGA_CRTC_START_LO] |
1094 (s->cr[VGA_CRTC_START_HI] << 8);
1097 line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
1098 ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
1099 ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
1101 *pline_offset = line_offset;
1102 *pstart_addr = start_addr;
1103 *pline_compare = line_compare;
1106 /* update start_addr and line_offset. Return TRUE if modified */
1107 static int update_basic_params(VGACommonState *s)
1110 uint32_t start_addr, line_offset, line_compare;
1114 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1116 if (line_offset != s->line_offset ||
1117 start_addr != s->start_addr ||
1118 line_compare != s->line_compare) {
1119 s->line_offset = line_offset;
1120 s->start_addr = start_addr;
1121 s->line_compare = line_compare;
1128 static const uint8_t cursor_glyph[32 * 4] = {
1129 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1130 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1131 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1132 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1133 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1134 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1135 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1136 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1137 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1138 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1139 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1140 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1141 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1142 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1143 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1144 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1147 static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
1148 int *pcwidth, int *pcheight)
1150 int width, cwidth, height, cheight;
1152 /* total width & height */
1153 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1155 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
1158 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
1159 cwidth = 16; /* NOTE: no 18 pixel wide */
1161 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1162 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1163 /* ugly hack for CGA 160x100x16 - explain me the logic */
1166 height = s->cr[VGA_CRTC_V_DISP_END] |
1167 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1168 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1169 height = (height + 1) / cheight;
1175 *pcheight = cheight;
1186 static void vga_draw_text(VGACommonState *s, int full_update)
1188 DisplaySurface *surface = qemu_console_surface(s->con);
1189 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1190 int cx_min, cx_max, linesize, x_incr, line, line1;
1191 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1192 uint8_t *d1, *d, *src, *dest, *cursor_ptr;
1193 const uint8_t *font_ptr, *font_base[2];
1194 int dup9, line_offset;
1196 uint32_t *ch_attr_ptr;
1197 int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1199 /* compute font data address (in plane 2) */
1200 v = s->sr[VGA_SEQ_CHARACTER_MAP];
1201 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1202 if (offset != s->font_offsets[0]) {
1203 s->font_offsets[0] = offset;
1206 font_base[0] = s->vram_ptr + offset;
1208 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1209 font_base[1] = s->vram_ptr + offset;
1210 if (offset != s->font_offsets[1]) {
1211 s->font_offsets[1] = offset;
1214 if (s->plane_updated & (1 << 2) || s->has_chain4_alias) {
1215 /* if the plane 2 was modified since the last display, it
1216 indicates the font may have been modified */
1217 s->plane_updated = 0;
1220 full_update |= update_basic_params(s);
1222 line_offset = s->line_offset;
1224 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1225 if ((height * width) <= 1) {
1226 /* better than nothing: exit if transient size is too small */
1229 if ((height * width) > CH_ATTR_SIZE) {
1230 /* better than nothing: exit if transient size is too big */
1234 if (width != s->last_width || height != s->last_height ||
1235 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1236 s->last_scr_width = width * cw;
1237 s->last_scr_height = height * cheight;
1238 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
1239 surface = qemu_console_surface(s->con);
1240 dpy_text_resize(s->con, width, height);
1242 s->last_width = width;
1243 s->last_height = height;
1244 s->last_ch = cheight;
1248 full_update |= update_palette16(s);
1249 palette = s->last_palette;
1250 x_incr = cw * surface_bytes_per_pixel(surface);
1253 s->full_update_text = 1;
1255 if (s->full_update_gfx) {
1256 s->full_update_gfx = 0;
1260 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1261 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1262 if (cursor_offset != s->cursor_offset ||
1263 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1264 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
1265 /* if the cursor position changed, we update the old and new
1267 if (s->cursor_offset < CH_ATTR_SIZE)
1268 s->last_ch_attr[s->cursor_offset] = -1;
1269 if (cursor_offset < CH_ATTR_SIZE)
1270 s->last_ch_attr[cursor_offset] = -1;
1271 s->cursor_offset = cursor_offset;
1272 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1273 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1275 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1276 if (now >= s->cursor_blink_time) {
1277 s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2;
1278 s->cursor_visible_phase = !s->cursor_visible_phase;
1281 dest = surface_data(surface);
1282 linesize = surface_stride(surface);
1283 ch_attr_ptr = s->last_ch_attr;
1285 offset = s->start_addr * 4;
1286 for(cy = 0; cy < height; cy++) {
1288 src = s->vram_ptr + offset;
1291 for(cx = 0; cx < width; cx++) {
1292 ch_attr = *(uint16_t *)src;
1293 if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) {
1298 *ch_attr_ptr = ch_attr;
1299 #ifdef HOST_WORDS_BIGENDIAN
1301 cattr = ch_attr & 0xff;
1303 ch = ch_attr & 0xff;
1304 cattr = ch_attr >> 8;
1306 font_ptr = font_base[(cattr >> 3) & 1];
1307 font_ptr += 32 * 4 * ch;
1308 bgcol = palette[cattr >> 4];
1309 fgcol = palette[cattr & 0x0f];
1311 vga_draw_glyph16(d1, linesize,
1312 font_ptr, cheight, fgcol, bgcol);
1313 } else if (cw != 9) {
1314 vga_draw_glyph8(d1, linesize,
1315 font_ptr, cheight, fgcol, bgcol);
1318 if (ch >= 0xb0 && ch <= 0xdf &&
1319 (s->ar[VGA_ATC_MODE] & 0x04)) {
1322 vga_draw_glyph9(d1, linesize,
1323 font_ptr, cheight, fgcol, bgcol, dup9);
1325 if (src == cursor_ptr &&
1326 !(s->cr[VGA_CRTC_CURSOR_START] & 0x20) &&
1327 s->cursor_visible_phase) {
1328 int line_start, line_last, h;
1329 /* draw the cursor */
1330 line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
1331 line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
1332 /* XXX: check that */
1333 if (line_last > cheight - 1)
1334 line_last = cheight - 1;
1335 if (line_last >= line_start && line_start < cheight) {
1336 h = line_last - line_start + 1;
1337 d = d1 + linesize * line_start;
1339 vga_draw_glyph16(d, linesize,
1340 cursor_glyph, h, fgcol, bgcol);
1341 } else if (cw != 9) {
1342 vga_draw_glyph8(d, linesize,
1343 cursor_glyph, h, fgcol, bgcol);
1345 vga_draw_glyph9(d, linesize,
1346 cursor_glyph, h, fgcol, bgcol, 1);
1356 dpy_gfx_update(s->con, cx_min * cw, cy * cheight,
1357 (cx_max - cx_min + 1) * cw, cheight);
1359 dest += linesize * cheight;
1360 line1 = line + cheight;
1361 offset += line_offset;
1362 if (line < s->line_compare && line1 >= s->line_compare) {
1387 static vga_draw_line_func * const vga_draw_line_table[VGA_DRAW_LINE_NB] = {
1404 static int vga_get_bpp(VGACommonState *s)
1408 if (vbe_enabled(s)) {
1409 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1416 static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1420 if (vbe_enabled(s)) {
1421 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1422 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1424 width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
1425 height = s->cr[VGA_CRTC_V_DISP_END] |
1426 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1427 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1428 height = (height + 1);
1434 void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
1437 if (y1 >= VGA_MAX_HEIGHT)
1439 if (y2 >= VGA_MAX_HEIGHT)
1440 y2 = VGA_MAX_HEIGHT;
1441 for(y = y1; y < y2; y++) {
1442 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1446 void vga_sync_dirty_bitmap(VGACommonState *s)
1448 memory_region_sync_dirty_bitmap(&s->vram);
1451 void vga_dirty_log_start(VGACommonState *s)
1453 memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
1456 void vga_dirty_log_stop(VGACommonState *s)
1458 memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
1464 static void vga_draw_graphic(VGACommonState *s, int full_update)
1466 DisplaySurface *surface = qemu_console_surface(s->con);
1467 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1468 int width, height, shift_control, line_offset, bwidth, bits;
1469 ram_addr_t page0, page1, page_min, page_max;
1470 int disp_width, multi_scan, multi_run;
1472 uint32_t v, addr1, addr;
1473 vga_draw_line_func *vga_draw_line = NULL;
1475 pixman_format_code_t format;
1476 #ifdef HOST_WORDS_BIGENDIAN
1477 bool byteswap = !s->big_endian_fb;
1479 bool byteswap = s->big_endian_fb;
1482 full_update |= update_basic_params(s);
1485 vga_sync_dirty_bitmap(s);
1487 s->get_resolution(s, &width, &height);
1490 shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
1491 double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
1492 if (shift_control != 1) {
1493 multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
1496 /* in CGA modes, multi_scan is ignored */
1497 /* XXX: is it correct ? */
1498 multi_scan = double_scan;
1500 multi_run = multi_scan;
1501 if (shift_control != s->shift_control ||
1502 double_scan != s->double_scan) {
1504 s->shift_control = shift_control;
1505 s->double_scan = double_scan;
1508 if (shift_control == 0) {
1509 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1512 } else if (shift_control == 1) {
1513 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1518 depth = s->get_bpp(s);
1521 * Check whether we can share the surface with the backend
1522 * or whether we need a shadow surface. We share native
1523 * endian surfaces for 15bpp and above and byteswapped
1524 * surfaces for 24bpp and above.
1526 format = qemu_default_pixman_format(depth, !byteswap);
1528 share_surface = dpy_gfx_check_format(s->con, format)
1529 && !s->force_shadow;
1531 share_surface = false;
1533 if (s->line_offset != s->last_line_offset ||
1534 disp_width != s->last_width ||
1535 height != s->last_height ||
1536 s->last_depth != depth ||
1537 s->last_byteswap != byteswap ||
1538 share_surface != is_buffer_shared(surface)) {
1539 if (share_surface) {
1540 surface = qemu_create_displaysurface_from(disp_width,
1541 height, format, s->line_offset,
1542 s->vram_ptr + (s->start_addr * 4));
1543 dpy_gfx_replace_surface(s->con, surface);
1545 printf("VGA: Using shared surface for depth=%d swap=%d\n",
1549 qemu_console_resize(s->con, disp_width, height);
1550 surface = qemu_console_surface(s->con);
1552 printf("VGA: Using shadow surface for depth=%d swap=%d\n",
1556 s->last_scr_width = disp_width;
1557 s->last_scr_height = height;
1558 s->last_width = disp_width;
1559 s->last_height = height;
1560 s->last_line_offset = s->line_offset;
1561 s->last_depth = depth;
1562 s->last_byteswap = byteswap;
1564 } else if (is_buffer_shared(surface) &&
1565 (full_update || surface_data(surface) != s->vram_ptr
1566 + (s->start_addr * 4))) {
1567 pixman_format_code_t format =
1568 qemu_default_pixman_format(depth, !byteswap);
1569 surface = qemu_create_displaysurface_from(disp_width,
1570 height, format, s->line_offset,
1571 s->vram_ptr + (s->start_addr * 4));
1572 dpy_gfx_replace_surface(s->con, surface);
1575 if (shift_control == 0) {
1576 full_update |= update_palette16(s);
1577 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1578 v = VGA_DRAW_LINE4D2;
1583 } else if (shift_control == 1) {
1584 full_update |= update_palette16(s);
1585 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1586 v = VGA_DRAW_LINE2D2;
1592 switch(s->get_bpp(s)) {
1595 full_update |= update_palette256(s);
1596 v = VGA_DRAW_LINE8D2;
1600 full_update |= update_palette256(s);
1605 v = s->big_endian_fb ? VGA_DRAW_LINE15_BE : VGA_DRAW_LINE15_LE;
1609 v = s->big_endian_fb ? VGA_DRAW_LINE16_BE : VGA_DRAW_LINE16_LE;
1613 v = s->big_endian_fb ? VGA_DRAW_LINE24_BE : VGA_DRAW_LINE24_LE;
1617 v = s->big_endian_fb ? VGA_DRAW_LINE32_BE : VGA_DRAW_LINE32_LE;
1622 vga_draw_line = vga_draw_line_table[v];
1624 if (!is_buffer_shared(surface) && s->cursor_invalidate) {
1625 s->cursor_invalidate(s);
1628 line_offset = s->line_offset;
1630 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1631 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
1632 s->line_compare, s->sr[VGA_SEQ_CLOCK_MODE]);
1634 addr1 = (s->start_addr * 4);
1635 bwidth = (width * bits + 7) / 8;
1639 d = surface_data(surface);
1640 linesize = surface_stride(surface);
1642 for(y = 0; y < height; y++) {
1644 if (!(s->cr[VGA_CRTC_MODE] & 1)) {
1646 /* CGA compatibility handling */
1647 shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
1648 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1650 if (!(s->cr[VGA_CRTC_MODE] & 2)) {
1651 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1653 update = full_update;
1655 page1 = addr + bwidth - 1;
1656 update |= memory_region_get_dirty(&s->vram, page0, page1 - page0,
1658 /* explicit invalidation for the hardware cursor */
1659 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1663 if (page0 < page_min)
1665 if (page1 > page_max)
1667 if (!(is_buffer_shared(surface))) {
1668 vga_draw_line(s, d, s->vram_ptr + addr, width);
1669 if (s->cursor_draw_line)
1670 s->cursor_draw_line(s, d, y);
1674 /* flush to display */
1675 dpy_gfx_update(s->con, 0, y_start,
1676 disp_width, y - y_start);
1681 mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
1682 if ((y1 & mask) == mask)
1683 addr1 += line_offset;
1685 multi_run = multi_scan;
1689 /* line compare acts on the displayed lines */
1690 if (y == s->line_compare)
1695 /* flush to display */
1696 dpy_gfx_update(s->con, 0, y_start,
1697 disp_width, y - y_start);
1699 /* reset modified pages */
1700 if (page_max >= page_min) {
1701 memory_region_reset_dirty(&s->vram,
1703 page_max - page_min,
1706 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1709 static void vga_draw_blank(VGACommonState *s, int full_update)
1711 DisplaySurface *surface = qemu_console_surface(s->con);
1717 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1720 w = s->last_scr_width * surface_bytes_per_pixel(surface);
1721 d = surface_data(surface);
1722 for(i = 0; i < s->last_scr_height; i++) {
1724 d += surface_stride(surface);
1726 dpy_gfx_update(s->con, 0, 0,
1727 s->last_scr_width, s->last_scr_height);
1730 #define GMODE_TEXT 0
1731 #define GMODE_GRAPH 1
1732 #define GMODE_BLANK 2
1734 static void vga_update_display(void *opaque)
1736 VGACommonState *s = opaque;
1737 DisplaySurface *surface = qemu_console_surface(s->con);
1738 int full_update, graphic_mode;
1740 qemu_flush_coalesced_mmio_buffer();
1742 if (surface_bits_per_pixel(surface) == 0) {
1746 if (!(s->ar_index & 0x20)) {
1747 graphic_mode = GMODE_BLANK;
1749 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1751 if (graphic_mode != s->graphic_mode) {
1752 s->graphic_mode = graphic_mode;
1753 s->cursor_blink_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1756 switch(graphic_mode) {
1758 vga_draw_text(s, full_update);
1761 vga_draw_graphic(s, full_update);
1765 vga_draw_blank(s, full_update);
1771 /* force a full display refresh */
1772 static void vga_invalidate_display(void *opaque)
1774 VGACommonState *s = opaque;
1777 s->last_height = -1;
1780 void vga_common_reset(VGACommonState *s)
1783 memset(s->sr, '\0', sizeof(s->sr));
1785 memset(s->gr, '\0', sizeof(s->gr));
1787 memset(s->ar, '\0', sizeof(s->ar));
1788 s->ar_flip_flop = 0;
1790 memset(s->cr, '\0', sizeof(s->cr));
1796 s->dac_sub_index = 0;
1797 s->dac_read_index = 0;
1798 s->dac_write_index = 0;
1799 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1801 memset(s->palette, '\0', sizeof(s->palette));
1804 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1805 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
1806 s->vbe_start_addr = 0;
1807 s->vbe_line_offset = 0;
1808 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1809 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1810 s->graphic_mode = -1; /* force full update */
1811 s->shift_control = 0;
1814 s->line_compare = 0;
1816 s->plane_updated = 0;
1821 s->last_scr_width = 0;
1822 s->last_scr_height = 0;
1823 s->cursor_start = 0;
1825 s->cursor_offset = 0;
1826 s->big_endian_fb = s->default_endian_fb;
1827 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1828 memset(s->last_palette, '\0', sizeof(s->last_palette));
1829 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1830 switch (vga_retrace_method) {
1831 case VGA_RETRACE_DUMB:
1833 case VGA_RETRACE_PRECISE:
1834 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1837 vga_update_memory_access(s);
1840 static void vga_reset(void *opaque)
1842 VGACommonState *s = opaque;
1843 vga_common_reset(s);
1846 #define TEXTMODE_X(x) ((x) % width)
1847 #define TEXTMODE_Y(x) ((x) / width)
1848 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1849 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1850 /* relay text rendering to the display driver
1851 * instead of doing a full vga_update_display() */
1852 static void vga_update_text(void *opaque, console_ch_t *chardata)
1854 VGACommonState *s = opaque;
1855 int graphic_mode, i, cursor_offset, cursor_visible;
1856 int cw, cheight, width, height, size, c_min, c_max;
1858 console_ch_t *dst, val;
1859 char msg_buffer[80];
1860 int full_update = 0;
1862 qemu_flush_coalesced_mmio_buffer();
1864 if (!(s->ar_index & 0x20)) {
1865 graphic_mode = GMODE_BLANK;
1867 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1869 if (graphic_mode != s->graphic_mode) {
1870 s->graphic_mode = graphic_mode;
1873 if (s->last_width == -1) {
1878 switch (graphic_mode) {
1880 /* TODO: update palette */
1881 full_update |= update_basic_params(s);
1883 /* total width & height */
1884 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1886 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
1889 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
1890 cw = 16; /* NOTE: no 18 pixel wide */
1892 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1893 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1894 /* ugly hack for CGA 160x100x16 - explain me the logic */
1897 height = s->cr[VGA_CRTC_V_DISP_END] |
1898 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1899 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1900 height = (height + 1) / cheight;
1903 size = (height * width);
1904 if (size > CH_ATTR_SIZE) {
1908 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
1913 if (width != s->last_width || height != s->last_height ||
1914 cw != s->last_cw || cheight != s->last_ch) {
1915 s->last_scr_width = width * cw;
1916 s->last_scr_height = height * cheight;
1917 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
1918 dpy_text_resize(s->con, width, height);
1920 s->last_width = width;
1921 s->last_height = height;
1922 s->last_ch = cheight;
1928 s->full_update_gfx = 1;
1930 if (s->full_update_text) {
1931 s->full_update_text = 0;
1935 /* Update "hardware" cursor */
1936 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1937 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1938 if (cursor_offset != s->cursor_offset ||
1939 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1940 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
1941 cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
1942 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
1943 dpy_text_cursor(s->con,
1944 TEXTMODE_X(cursor_offset),
1945 TEXTMODE_Y(cursor_offset));
1947 dpy_text_cursor(s->con, -1, -1);
1948 s->cursor_offset = cursor_offset;
1949 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1950 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1953 src = (uint32_t *) s->vram_ptr + s->start_addr;
1957 for (i = 0; i < size; src ++, dst ++, i ++)
1958 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
1960 dpy_text_update(s->con, 0, 0, width, height);
1964 for (i = 0; i < size; src ++, dst ++, i ++) {
1965 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
1973 for (; i < size; src ++, dst ++, i ++) {
1974 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
1981 if (c_min <= c_max) {
1982 i = TEXTMODE_Y(c_min);
1983 dpy_text_update(s->con, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
1992 s->get_resolution(s, &width, &height);
1993 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2001 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
2005 /* Display a message */
2007 s->last_height = height = 3;
2008 dpy_text_cursor(s->con, -1, -1);
2009 dpy_text_resize(s->con, s->last_width, height);
2011 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2012 console_write_ch(dst ++, ' ');
2014 size = strlen(msg_buffer);
2015 width = (s->last_width - size) / 2;
2016 dst = chardata + s->last_width + width;
2017 for (i = 0; i < size; i ++)
2018 console_write_ch(dst ++, ATTR2CHTYPE(msg_buffer[i], QEMU_COLOR_BLUE,
2019 QEMU_COLOR_BLACK, 1));
2021 dpy_text_update(s->con, 0, 0, s->last_width, height);
2024 static uint64_t vga_mem_read(void *opaque, hwaddr addr,
2027 VGACommonState *s = opaque;
2029 return vga_mem_readb(s, addr);
2032 static void vga_mem_write(void *opaque, hwaddr addr,
2033 uint64_t data, unsigned size)
2035 VGACommonState *s = opaque;
2037 vga_mem_writeb(s, addr, data);
2040 const MemoryRegionOps vga_mem_ops = {
2041 .read = vga_mem_read,
2042 .write = vga_mem_write,
2043 .endianness = DEVICE_LITTLE_ENDIAN,
2045 .min_access_size = 1,
2046 .max_access_size = 1,
2050 static int vga_common_post_load(void *opaque, int version_id)
2052 VGACommonState *s = opaque;
2055 s->graphic_mode = -1;
2059 static bool vga_endian_state_needed(void *opaque)
2061 VGACommonState *s = opaque;
2064 * Only send the endian state if it's different from the
2065 * default one, thus ensuring backward compatibility for
2066 * migration of the common case
2068 return s->default_endian_fb != s->big_endian_fb;
2071 static const VMStateDescription vmstate_vga_endian = {
2072 .name = "vga.endian",
2074 .minimum_version_id = 1,
2075 .needed = vga_endian_state_needed,
2076 .fields = (VMStateField[]) {
2077 VMSTATE_BOOL(big_endian_fb, VGACommonState),
2078 VMSTATE_END_OF_LIST()
2082 const VMStateDescription vmstate_vga_common = {
2085 .minimum_version_id = 2,
2086 .post_load = vga_common_post_load,
2087 .fields = (VMStateField[]) {
2088 VMSTATE_UINT32(latch, VGACommonState),
2089 VMSTATE_UINT8(sr_index, VGACommonState),
2090 VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2091 VMSTATE_UINT8(gr_index, VGACommonState),
2092 VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2093 VMSTATE_UINT8(ar_index, VGACommonState),
2094 VMSTATE_BUFFER(ar, VGACommonState),
2095 VMSTATE_INT32(ar_flip_flop, VGACommonState),
2096 VMSTATE_UINT8(cr_index, VGACommonState),
2097 VMSTATE_BUFFER(cr, VGACommonState),
2098 VMSTATE_UINT8(msr, VGACommonState),
2099 VMSTATE_UINT8(fcr, VGACommonState),
2100 VMSTATE_UINT8(st00, VGACommonState),
2101 VMSTATE_UINT8(st01, VGACommonState),
2103 VMSTATE_UINT8(dac_state, VGACommonState),
2104 VMSTATE_UINT8(dac_sub_index, VGACommonState),
2105 VMSTATE_UINT8(dac_read_index, VGACommonState),
2106 VMSTATE_UINT8(dac_write_index, VGACommonState),
2107 VMSTATE_BUFFER(dac_cache, VGACommonState),
2108 VMSTATE_BUFFER(palette, VGACommonState),
2110 VMSTATE_INT32(bank_offset, VGACommonState),
2111 VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
2112 VMSTATE_UINT16(vbe_index, VGACommonState),
2113 VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2114 VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2115 VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2116 VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
2117 VMSTATE_END_OF_LIST()
2119 .subsections = (const VMStateDescription*[]) {
2120 &vmstate_vga_endian,
2125 static const GraphicHwOps vga_ops = {
2126 .invalidate = vga_invalidate_display,
2127 .gfx_update = vga_update_display,
2128 .text_update = vga_update_text,
2131 static inline uint32_t uint_clamp(uint32_t val, uint32_t vmin, uint32_t vmax)
2142 void vga_common_init(VGACommonState *s, Object *obj, bool global_vmstate)
2146 for(i = 0;i < 256; i++) {
2148 for(j = 0; j < 8; j++) {
2149 v |= ((i >> j) & 1) << (j * 4);
2154 for(j = 0; j < 4; j++) {
2155 v |= ((i >> (2 * j)) & 3) << (j * 4);
2159 for(i = 0; i < 16; i++) {
2161 for(j = 0; j < 4; j++) {
2164 v |= b << (2 * j + 1);
2169 s->vram_size_mb = uint_clamp(s->vram_size_mb, 1, 512);
2170 s->vram_size_mb = pow2ceil(s->vram_size_mb);
2171 s->vram_size = s->vram_size_mb << 20;
2174 s->vbe_size = s->vram_size;
2177 s->is_vbe_vmstate = 1;
2178 memory_region_init_ram(&s->vram, obj, "vga.vram", s->vram_size,
2180 vmstate_register_ram(&s->vram, global_vmstate ? NULL : DEVICE(obj));
2181 xen_register_framebuffer(&s->vram);
2182 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
2183 s->get_bpp = vga_get_bpp;
2184 s->get_offsets = vga_get_offsets;
2185 s->get_resolution = vga_get_resolution;
2186 s->hw_ops = &vga_ops;
2187 switch (vga_retrace_method) {
2188 case VGA_RETRACE_DUMB:
2189 s->retrace = vga_dumb_retrace;
2190 s->update_retrace_info = vga_dumb_update_retrace_info;
2193 case VGA_RETRACE_PRECISE:
2194 s->retrace = vga_precise_retrace;
2195 s->update_retrace_info = vga_precise_update_retrace_info;
2200 * Set default fb endian based on target, could probably be turned
2201 * into a device attribute set by the machine/platform to remove
2202 * all target endian dependencies from this file.
2204 #ifdef TARGET_WORDS_BIGENDIAN
2205 s->default_endian_fb = true;
2207 s->default_endian_fb = false;
2209 vga_dirty_log_start(s);
2212 static const MemoryRegionPortio vga_portio_list[] = {
2213 { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
2214 { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
2215 { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
2216 { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
2217 { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
2218 PORTIO_END_OF_LIST(),
2221 static const MemoryRegionPortio vbe_portio_list[] = {
2222 { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
2224 { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2226 { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2227 PORTIO_END_OF_LIST(),
2230 /* Used by both ISA and PCI */
2231 MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
2232 const MemoryRegionPortio **vga_ports,
2233 const MemoryRegionPortio **vbe_ports)
2235 MemoryRegion *vga_mem;
2237 *vga_ports = vga_portio_list;
2238 *vbe_ports = vbe_portio_list;
2240 vga_mem = g_malloc(sizeof(*vga_mem));
2241 memory_region_init_io(vga_mem, obj, &vga_mem_ops, s,
2242 "vga-lowmem", 0x20000);
2243 memory_region_set_flush_coalesced(vga_mem);
2248 void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
2249 MemoryRegion *address_space_io, bool init_vga_ports)
2251 MemoryRegion *vga_io_memory;
2252 const MemoryRegionPortio *vga_ports, *vbe_ports;
2254 qemu_register_reset(vga_reset, s);
2258 s->legacy_address_space = address_space;
2260 vga_io_memory = vga_init_io(s, obj, &vga_ports, &vbe_ports);
2261 memory_region_add_subregion_overlap(address_space,
2265 memory_region_set_coalescing(vga_io_memory);
2266 if (init_vga_ports) {
2267 portio_list_init(&s->vga_port_list, obj, vga_ports, s, "vga");
2268 portio_list_set_flush_coalesced(&s->vga_port_list);
2269 portio_list_add(&s->vga_port_list, address_space_io, 0x3b0);
2272 portio_list_init(&s->vbe_port_list, obj, vbe_ports, s, "vbe");
2273 portio_list_add(&s->vbe_port_list, address_space_io, 0x1ce);
2277 void vga_init_vbe(VGACommonState *s, Object *obj, MemoryRegion *system_memory)
2279 /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2280 * so use an alias to avoid double-mapping the same region.
2282 memory_region_init_alias(&s->vram_vbe, obj, "vram.vbe",
2283 &s->vram, 0, memory_region_size(&s->vram));
2284 /* XXX: use optimized standard vga accesses */
2285 memory_region_add_subregion(system_memory,
2286 VBE_DISPI_LFB_PHYSICAL_ADDRESS,