1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
30 static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code)
32 struct spi_info *spi = &(chip->spi);
34 spi->err_code = err_code;
37 static int spi_init(struct rtsx_chip *chip)
41 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF,
42 CS_POLARITY_LOW | DTO_MSB_FIRST | SPI_MASTER | SPI_MODE0 | SPI_AUTO);
47 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK,
54 return STATUS_SUCCESS;
57 static int spi_set_init_para(struct rtsx_chip *chip)
59 struct spi_info *spi = &(chip->spi);
62 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF,
63 (u8)(spi->clk_div >> 8));
68 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF,
75 retval = switch_clock(chip, spi->spi_clock);
76 if (retval != STATUS_SUCCESS) {
81 retval = select_card(chip, SPI_CARD);
82 if (retval != STATUS_SUCCESS) {
87 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN,
93 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN,
102 retval = spi_init(chip);
103 if (retval != STATUS_SUCCESS) {
108 return STATUS_SUCCESS;
111 static int sf_polling_status(struct rtsx_chip *chip, int msec)
117 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR);
118 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
119 SPI_TRANSFER0_START | SPI_POLLING_MODE0);
120 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
123 retval = rtsx_send_cmd(chip, 0, msec);
125 rtsx_clear_spi_error(chip);
126 spi_set_err_code(chip, SPI_BUSY_ERR);
131 return STATUS_SUCCESS;
134 static int sf_enable_write(struct rtsx_chip *chip, u8 ins)
136 struct spi_info *spi = &(chip->spi);
140 return STATUS_SUCCESS;
144 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
145 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
146 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
147 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
148 SPI_TRANSFER0_START | SPI_C_MODE0);
149 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
152 retval = rtsx_send_cmd(chip, 0, 100);
154 rtsx_clear_spi_error(chip);
155 spi_set_err_code(chip, SPI_HW_ERR);
160 return STATUS_SUCCESS;
163 static int sf_disable_write(struct rtsx_chip *chip, u8 ins)
165 struct spi_info *spi = &(chip->spi);
169 return STATUS_SUCCESS;
173 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
174 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
175 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
176 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
177 SPI_TRANSFER0_START | SPI_C_MODE0);
178 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
181 retval = rtsx_send_cmd(chip, 0, 100);
183 rtsx_clear_spi_error(chip);
184 spi_set_err_code(chip, SPI_HW_ERR);
189 return STATUS_SUCCESS;
192 static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr,
195 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
196 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
197 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
198 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len);
199 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8));
201 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
202 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
204 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
206 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
207 SPI_TRANSFER0_START | SPI_CADO_MODE0);
209 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
210 SPI_TRANSFER0_START | SPI_CDO_MODE0);
212 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
216 static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr)
222 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
223 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
224 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
226 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
227 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
229 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
231 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
232 SPI_TRANSFER0_START | SPI_CA_MODE0);
234 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
235 SPI_TRANSFER0_START | SPI_C_MODE0);
237 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
240 retval = rtsx_send_cmd(chip, 0, 100);
242 rtsx_clear_spi_error(chip);
243 spi_set_err_code(chip, SPI_HW_ERR);
248 return STATUS_SUCCESS;
251 static int spi_init_eeprom(struct rtsx_chip *chip)
261 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00);
266 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27);
272 retval = switch_clock(chip, clk);
273 if (retval != STATUS_SUCCESS) {
278 retval = select_card(chip, SPI_CARD);
279 if (retval != STATUS_SUCCESS) {
284 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN,
290 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN,
299 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF,
300 CS_POLARITY_HIGH | SPI_EEPROM_AUTO);
305 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK,
312 return STATUS_SUCCESS;
315 static int spi_eeprom_program_enable(struct rtsx_chip *chip)
321 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86);
322 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13);
323 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
324 SPI_TRANSFER0_START | SPI_CA_MODE0);
325 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
328 retval = rtsx_send_cmd(chip, 0, 100);
334 return STATUS_SUCCESS;
337 int spi_erase_eeprom_chip(struct rtsx_chip *chip)
341 retval = spi_init_eeprom(chip);
342 if (retval != STATUS_SUCCESS) {
347 retval = spi_eeprom_program_enable(chip);
348 if (retval != STATUS_SUCCESS) {
355 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
356 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
357 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12);
358 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84);
359 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
360 SPI_TRANSFER0_START | SPI_CA_MODE0);
361 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
364 retval = rtsx_send_cmd(chip, 0, 100);
370 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
376 return STATUS_SUCCESS;
379 int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr)
383 retval = spi_init_eeprom(chip);
384 if (retval != STATUS_SUCCESS) {
389 retval = spi_eeprom_program_enable(chip);
390 if (retval != STATUS_SUCCESS) {
397 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
398 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
399 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x07);
400 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
401 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
402 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
403 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
404 SPI_TRANSFER0_START | SPI_CA_MODE0);
405 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
408 retval = rtsx_send_cmd(chip, 0, 100);
414 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
420 return STATUS_SUCCESS;
424 int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val)
429 retval = spi_init_eeprom(chip);
430 if (retval != STATUS_SUCCESS) {
437 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
438 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
439 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x06);
440 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
441 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
442 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
443 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
444 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
445 SPI_TRANSFER0_START | SPI_CADI_MODE0);
446 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
449 retval = rtsx_send_cmd(chip, 0, 100);
456 retval = rtsx_read_register(chip, SPI_DATA, &data);
465 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
471 return STATUS_SUCCESS;
474 int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val)
478 retval = spi_init_eeprom(chip);
479 if (retval != STATUS_SUCCESS) {
484 retval = spi_eeprom_program_enable(chip);
485 if (retval != STATUS_SUCCESS) {
492 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
493 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
494 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x05);
495 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val);
496 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)addr);
497 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8));
498 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E);
499 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
500 SPI_TRANSFER0_START | SPI_CA_MODE0);
501 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
504 retval = rtsx_send_cmd(chip, 0, 100);
510 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
516 return STATUS_SUCCESS;
520 int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
522 struct spi_info *spi = &(chip->spi);
524 dev_dbg(rtsx_dev(chip), "spi_get_status: err_code = 0x%x\n",
526 rtsx_stor_set_xfer_buf(&(spi->err_code),
527 min_t(int, scsi_bufflen(srb), 1), srb);
528 scsi_set_resid(srb, scsi_bufflen(srb) - 1);
530 return STATUS_SUCCESS;
533 int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip)
535 struct spi_info *spi = &(chip->spi);
537 spi_set_err_code(chip, SPI_NO_ERR);
540 spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9];
542 spi->spi_clock = srb->cmnd[3];
544 spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5];
545 spi->write_en = srb->cmnd[6];
547 dev_dbg(rtsx_dev(chip), "spi_set_parameter: spi_clock = %d, clk_div = %d, write_en = %d\n",
548 spi->spi_clock, spi->clk_div, spi->write_en);
550 return STATUS_SUCCESS;
553 int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
559 spi_set_err_code(chip, SPI_NO_ERR);
561 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
563 spi_set_err_code(chip, SPI_INVALID_COMMAND);
568 retval = spi_set_init_para(chip);
569 if (retval != STATUS_SUCCESS) {
570 spi_set_err_code(chip, SPI_HW_ERR);
577 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
580 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]);
581 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]);
582 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]);
583 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]);
584 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
585 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
586 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]);
587 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]);
591 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
592 0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0);
594 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
595 0xFF, SPI_TRANSFER0_START | SPI_C_MODE0);
599 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
600 SPI_TRANSFER0_START | SPI_CADI_MODE0);
602 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
603 SPI_TRANSFER0_START | SPI_CDI_MODE0);
607 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
610 retval = rtsx_send_cmd(chip, 0, 100);
612 rtsx_clear_spi_error(chip);
613 spi_set_err_code(chip, SPI_HW_ERR);
619 buf = kmalloc(len, GFP_KERNEL);
625 retval = rtsx_read_ppbuf(chip, buf, len);
626 if (retval != STATUS_SUCCESS) {
627 spi_set_err_code(chip, SPI_READ_ERR);
633 rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb);
634 scsi_set_resid(srb, 0);
639 return STATUS_SUCCESS;
642 int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
645 unsigned int index = 0, offset = 0;
651 spi_set_err_code(chip, SPI_NO_ERR);
654 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
655 << 8) | srb->cmnd[6];
656 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
657 slow_read = srb->cmnd[9];
659 retval = spi_set_init_para(chip);
660 if (retval != STATUS_SUCCESS) {
661 spi_set_err_code(chip, SPI_HW_ERR);
666 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
673 u16 pagelen = SF_PAGE_LEN - (u8)addr;
680 trans_dma_enable(DMA_FROM_DEVICE, chip, 256, DMA_256);
682 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
685 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF,
687 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
689 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
691 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
692 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
694 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
696 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
698 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF,
700 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
701 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32);
704 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF,
706 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF,
709 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
710 SPI_TRANSFER0_START | SPI_CADI_MODE0);
711 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0,
712 SPI_TRANSFER0_END, SPI_TRANSFER0_END);
714 rtsx_send_cmd_no_wait(chip);
716 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
717 DMA_FROM_DEVICE, 10000);
720 rtsx_clear_spi_error(chip);
721 spi_set_err_code(chip, SPI_HW_ERR);
726 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset,
733 scsi_set_resid(srb, 0);
736 return STATUS_SUCCESS;
739 int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
742 u8 ins, program_mode;
746 unsigned int index = 0, offset = 0;
748 spi_set_err_code(chip, SPI_NO_ERR);
751 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
752 << 8) | srb->cmnd[6];
753 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
754 program_mode = srb->cmnd[9];
756 retval = spi_set_init_para(chip);
757 if (retval != STATUS_SUCCESS) {
758 spi_set_err_code(chip, SPI_HW_ERR);
763 if (program_mode == BYTE_PROGRAM) {
764 buf = kmalloc(4, GFP_KERNEL);
771 retval = sf_enable_write(chip, SPI_WREN);
772 if (retval != STATUS_SUCCESS) {
778 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
783 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
784 0x01, PINGPONG_BUFFER);
785 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
787 sf_program(chip, ins, 1, addr, 1);
789 retval = rtsx_send_cmd(chip, 0, 100);
792 rtsx_clear_spi_error(chip);
793 spi_set_err_code(chip, SPI_HW_ERR);
798 retval = sf_polling_status(chip, 100);
799 if (retval != STATUS_SUCCESS) {
811 } else if (program_mode == AAI_PROGRAM) {
814 retval = sf_enable_write(chip, SPI_WREN);
815 if (retval != STATUS_SUCCESS) {
820 buf = kmalloc(4, GFP_KERNEL);
827 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
832 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
833 0x01, PINGPONG_BUFFER);
834 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
837 sf_program(chip, ins, 1, addr, 1);
840 sf_program(chip, ins, 0, 0, 1);
843 retval = rtsx_send_cmd(chip, 0, 100);
846 rtsx_clear_spi_error(chip);
847 spi_set_err_code(chip, SPI_HW_ERR);
852 retval = sf_polling_status(chip, 100);
853 if (retval != STATUS_SUCCESS) {
864 retval = sf_disable_write(chip, SPI_WRDI);
865 if (retval != STATUS_SUCCESS) {
870 retval = sf_polling_status(chip, 100);
871 if (retval != STATUS_SUCCESS) {
875 } else if (program_mode == PAGE_PROGRAM) {
876 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
883 u16 pagelen = SF_PAGE_LEN - (u8)addr;
888 retval = sf_enable_write(chip, SPI_WREN);
889 if (retval != STATUS_SUCCESS) {
897 trans_dma_enable(DMA_TO_DEVICE, chip, 256, DMA_256);
898 sf_program(chip, ins, 1, addr, pagelen);
900 rtsx_send_cmd_no_wait(chip);
902 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index,
903 &offset, FROM_XFER_BUF);
905 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
909 rtsx_clear_spi_error(chip);
910 spi_set_err_code(chip, SPI_HW_ERR);
915 retval = sf_polling_status(chip, 100);
916 if (retval != STATUS_SUCCESS) {
928 spi_set_err_code(chip, SPI_INVALID_COMMAND);
933 return STATUS_SUCCESS;
936 int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
942 spi_set_err_code(chip, SPI_NO_ERR);
945 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
946 << 8) | srb->cmnd[6];
947 erase_mode = srb->cmnd[9];
949 retval = spi_set_init_para(chip);
950 if (retval != STATUS_SUCCESS) {
951 spi_set_err_code(chip, SPI_HW_ERR);
956 if (erase_mode == PAGE_ERASE) {
957 retval = sf_enable_write(chip, SPI_WREN);
958 if (retval != STATUS_SUCCESS) {
963 retval = sf_erase(chip, ins, 1, addr);
964 if (retval != STATUS_SUCCESS) {
968 } else if (erase_mode == CHIP_ERASE) {
969 retval = sf_enable_write(chip, SPI_WREN);
970 if (retval != STATUS_SUCCESS) {
975 retval = sf_erase(chip, ins, 0, 0);
976 if (retval != STATUS_SUCCESS) {
981 spi_set_err_code(chip, SPI_INVALID_COMMAND);
986 return STATUS_SUCCESS;
989 int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
992 u8 ins, status, ewsr;
995 status = srb->cmnd[4];
998 retval = spi_set_init_para(chip);
999 if (retval != STATUS_SUCCESS) {
1000 spi_set_err_code(chip, SPI_HW_ERR);
1005 retval = sf_enable_write(chip, ewsr);
1006 if (retval != STATUS_SUCCESS) {
1011 rtsx_init_cmd(chip);
1013 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
1016 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
1017 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
1018 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
1019 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0);
1020 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
1021 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status);
1022 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
1023 SPI_TRANSFER0_START | SPI_CDO_MODE0);
1024 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
1027 retval = rtsx_send_cmd(chip, 0, 100);
1028 if (retval != STATUS_SUCCESS) {
1029 rtsx_clear_spi_error(chip);
1030 spi_set_err_code(chip, SPI_HW_ERR);
1035 return STATUS_SUCCESS;