1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/workqueue.h>
27 #include <linux/vmalloc.h>
34 static void rtsx_calibration(struct rtsx_chip *chip)
36 rtsx_write_phy_register(chip, 0x1B, 0x135E);
38 rtsx_write_phy_register(chip, 0x00, 0x0280);
39 rtsx_write_phy_register(chip, 0x01, 0x7112);
40 rtsx_write_phy_register(chip, 0x01, 0x7110);
41 rtsx_write_phy_register(chip, 0x01, 0x7112);
42 rtsx_write_phy_register(chip, 0x01, 0x7113);
43 rtsx_write_phy_register(chip, 0x00, 0x0288);
46 void rtsx_disable_card_int(struct rtsx_chip *chip)
48 u32 reg = rtsx_readl(chip, RTSX_BIER);
50 reg &= ~(XD_INT_EN | SD_INT_EN | MS_INT_EN);
51 rtsx_writel(chip, RTSX_BIER, reg);
54 void rtsx_enable_card_int(struct rtsx_chip *chip)
56 u32 reg = rtsx_readl(chip, RTSX_BIER);
59 for (i = 0; i <= chip->max_lun; i++) {
60 if (chip->lun2card[i] & XD_CARD)
62 if (chip->lun2card[i] & SD_CARD)
64 if (chip->lun2card[i] & MS_CARD)
67 if (chip->hw_bypass_sd)
68 reg &= ~((u32)SD_INT_EN);
70 rtsx_writel(chip, RTSX_BIER, reg);
73 void rtsx_enable_bus_int(struct rtsx_chip *chip)
76 #ifndef DISABLE_CARD_INT
80 reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
82 #ifndef DISABLE_CARD_INT
83 for (i = 0; i <= chip->max_lun; i++) {
84 dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n",
85 i, chip->lun2card[i]);
87 if (chip->lun2card[i] & XD_CARD)
89 if (chip->lun2card[i] & SD_CARD)
91 if (chip->lun2card[i] & MS_CARD)
94 if (chip->hw_bypass_sd)
95 reg &= ~((u32)SD_INT_EN);
98 if (chip->ic_version >= IC_VER_C)
103 if (!chip->adma_mode)
104 reg |= DATA_DONE_INT_EN;
106 /* Enable Bus Interrupt */
107 rtsx_writel(chip, RTSX_BIER, reg);
109 dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg);
112 void rtsx_disable_bus_int(struct rtsx_chip *chip)
114 rtsx_writel(chip, RTSX_BIER, 0);
117 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
121 if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
122 if (chip->asic_code) {
123 retval = rtsx_write_register(chip, CARD_PULL_CTL5,
125 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
131 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
133 FPGA_SD_PULL_CTL_EN);
139 retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF,
146 /* Enable SDIO internal clock */
147 retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01);
153 retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF,
154 SDIO_BUS_CTRL | SDIO_CD_CTRL);
163 chip->need_reset |= SD_CARD;
166 return STATUS_SUCCESS;
169 #ifdef HW_AUTO_SWITCH_SD_BUS
170 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
173 bool sw_bypass_sd = false;
176 if (chip->driver_first_load) {
177 if (CHECK_PID(chip, 0x5288)) {
178 retval = rtsx_read_register(chip, 0xFE5A, &tmp);
185 } else if (CHECK_PID(chip, 0x5208)) {
186 retval = rtsx_read_register(chip, 0xFE70, &tmp);
195 if (chip->sdio_in_charge)
198 dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n",
199 chip->sdio_in_charge);
200 dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n",
201 chip->driver_first_load);
202 dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n",
206 u8 cd_toggle_mask = 0;
208 retval = rtsx_read_register(chip, TLPTISTAT, &tmp);
213 cd_toggle_mask = 0x08;
215 if (tmp & cd_toggle_mask) {
216 /* Disable sdio_bus_auto_switch */
217 if (CHECK_PID(chip, 0x5288)) {
218 retval = rtsx_write_register(chip, 0xFE5A,
224 } else if (CHECK_PID(chip, 0x5208)) {
225 retval = rtsx_write_register(chip, 0xFE70,
233 retval = rtsx_write_register(chip, TLPTISTAT, 0xFF,
240 chip->need_reset |= SD_CARD;
242 dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n");
244 if (chip->asic_code) {
245 retval = sd_pull_ctl_enable(chip);
246 if (retval != STATUS_SUCCESS) {
251 retval = rtsx_write_register(chip,
253 FPGA_SD_PULL_CTL_BIT | 0x20,
260 retval = card_share_mode(chip, SD_CARD);
261 if (retval != STATUS_SUCCESS) {
266 /* Enable sdio_bus_auto_switch */
267 if (CHECK_PID(chip, 0x5288)) {
268 retval = rtsx_write_register(chip, 0xFE5A,
274 } else if (CHECK_PID(chip, 0x5208)) {
275 retval = rtsx_write_register(chip, 0xFE70,
283 chip->chip_insert_with_sdio = 1;
287 retval = rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
293 chip->need_reset |= SD_CARD;
296 return STATUS_SUCCESS;
300 static int rtsx_reset_aspm(struct rtsx_chip *chip)
304 if (chip->dynamic_aspm) {
305 if (!CHK_SDIO_EXIST(chip) || !CHECK_PID(chip, 0x5288))
306 return STATUS_SUCCESS;
308 ret = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF,
309 chip->aspm_l0s_l1_en);
310 if (ret != STATUS_SUCCESS) {
315 return STATUS_SUCCESS;
318 if (CHECK_PID(chip, 0x5208)) {
319 ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F);
325 ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
326 if (ret != STATUS_SUCCESS) {
331 chip->aspm_level[0] = chip->aspm_l0s_l1_en;
332 if (CHK_SDIO_EXIST(chip)) {
333 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
334 ret = rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
335 0xC0, 0xFF, chip->aspm_l0s_l1_en);
336 if (ret != STATUS_SUCCESS) {
342 chip->aspm_enabled = 1;
344 return STATUS_SUCCESS;
347 static int rtsx_enable_pcie_intr(struct rtsx_chip *chip)
351 if (!chip->asic_code || !CHECK_PID(chip, 0x5208)) {
352 rtsx_enable_bus_int(chip);
353 return STATUS_SUCCESS;
356 if (chip->phy_debug_mode) {
357 ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0);
362 rtsx_disable_bus_int(chip);
364 rtsx_enable_bus_int(chip);
367 if (chip->ic_version >= IC_VER_D) {
370 ret = rtsx_read_phy_register(chip, 0x00, ®);
371 if (ret != STATUS_SUCCESS) {
378 ret = rtsx_write_phy_register(chip, 0x00, reg);
379 if (ret != STATUS_SUCCESS) {
384 ret = rtsx_read_phy_register(chip, 0x1C, ®);
385 if (ret != STATUS_SUCCESS) {
391 ret = rtsx_write_phy_register(chip, 0x1C, reg);
392 if (ret != STATUS_SUCCESS) {
398 if (chip->driver_first_load && (chip->ic_version < IC_VER_C))
399 rtsx_calibration(chip);
401 return STATUS_SUCCESS;
404 int rtsx_reset_chip(struct rtsx_chip *chip)
408 rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
410 rtsx_disable_aspm(chip);
412 retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00);
418 /* Disable card clock */
419 retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0);
426 /* SSC power on, OCD power on */
427 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
428 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0);
434 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
442 retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK,
448 retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK,
454 retval = rtsx_write_register(chip, OCPCTL, 0xFF,
455 CARD_OC_INT_EN | CARD_DETECT_EN);
462 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
470 if (!CHECK_PID(chip, 0x5288)) {
471 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03);
479 retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03);
485 /* Reset delink mode */
486 retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0);
492 /* Card driving select */
493 retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF,
494 chip->card_drive_sel);
500 #ifdef LED_AUTO_BLINK
501 retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF,
502 LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
509 if (chip->asic_code) {
510 /* Enable SSC Clock */
511 retval = rtsx_write_register(chip, SSC_CTL1, 0xFF,
512 SSC_8X_EN | SSC_SEL_4M);
517 retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12);
525 * Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
527 * bit[1] u_cd_rst_core_en rst_value = 0
528 * bit[2] u_force_rst_core_en rst_value = 0
529 * bit[5] u_mac_phy_rst_n_dbg rst_value = 1
530 * bit[4] u_non_sticky_rst_n_dbg rst_value = 0
532 retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10);
539 if (chip->aspm_l0s_l1_en) {
540 retval = rtsx_reset_aspm(chip);
541 if (retval != STATUS_SUCCESS) {
546 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
547 retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
548 if (retval != STATUS_SUCCESS) {
553 retval = rtsx_write_config_byte(chip, LCTLR,
554 chip->aspm_l0s_l1_en);
555 if (retval != STATUS_SUCCESS) {
561 retval = rtsx_write_config_byte(chip, 0x81, 1);
562 if (retval != STATUS_SUCCESS) {
567 if (CHK_SDIO_EXIST(chip)) {
568 retval = rtsx_write_cfg_dw(chip,
569 CHECK_PID(chip, 0x5288) ? 2 : 1,
570 0xC0, 0xFF00, 0x0100);
572 if (retval != STATUS_SUCCESS) {
578 if (CHECK_PID(chip, 0x5288) && !CHK_SDIO_EXIST(chip)) {
579 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103);
580 if (retval != STATUS_SUCCESS) {
585 retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
586 if (retval != STATUS_SUCCESS) {
592 retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT,
599 retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
605 retval = rtsx_enable_pcie_intr(chip);
606 if (retval != STATUS_SUCCESS) {
611 chip->need_reset = 0;
613 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
615 if (chip->hw_bypass_sd)
617 dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__,
619 if (chip->int_reg & SD_EXIST) {
620 #ifdef HW_AUTO_SWITCH_SD_BUS
621 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C))
622 retval = rtsx_pre_handle_sdio_old(chip);
624 retval = rtsx_pre_handle_sdio_new(chip);
626 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (rtsx_reset_chip)\n",
627 (unsigned int)(chip->need_reset));
628 #else /* HW_AUTO_SWITCH_SD_BUS */
629 retval = rtsx_pre_handle_sdio_old(chip);
630 #endif /* HW_AUTO_SWITCH_SD_BUS */
631 if (retval != STATUS_SUCCESS) {
638 retval = rtsx_write_register(chip, SDIO_CTRL,
639 SDIO_BUS_CTRL | SDIO_CD_CTRL, 0);
647 if (chip->int_reg & XD_EXIST)
648 chip->need_reset |= XD_CARD;
649 if (chip->int_reg & MS_EXIST)
650 chip->need_reset |= MS_CARD;
651 if (chip->int_reg & CARD_EXIST) {
652 retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB,
660 dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__,
661 (unsigned int)(chip->need_reset));
663 retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00);
669 if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
670 /* Turn off main power when entering S3/S4 state */
671 retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03,
679 if (chip->remote_wakeup_en && !chip->auto_delink_en) {
680 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07);
685 if (chip->aux_pwr_exist) {
686 retval = rtsx_write_register(chip, PME_FORCE_CTL,
694 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04);
699 retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30);
706 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
707 retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14);
714 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
715 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
716 if (retval != STATUS_SUCCESS) {
722 if (chip->ft2_fast_mode) {
723 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
724 MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON);
729 udelay(chip->pmos_pwr_on_interval);
730 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
731 MS_POWER_ON | SD_POWER_ON);
741 rtsx_reset_detected_cards(chip, 0);
743 chip->driver_first_load = 0;
745 return STATUS_SUCCESS;
748 static inline int check_sd_speed_prior(u32 sd_speed_prior)
750 bool fake_para = false;
753 for (i = 0; i < 4; i++) {
754 u8 tmp = (u8)(sd_speed_prior >> (i*8));
756 if ((tmp < 0x01) || (tmp > 0x04)) {
765 static inline int check_sd_current_prior(u32 sd_current_prior)
767 bool fake_para = false;
770 for (i = 0; i < 4; i++) {
771 u8 tmp = (u8)(sd_current_prior >> (i*8));
782 static int rts5208_init(struct rtsx_chip *chip)
788 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
793 retval = rtsx_read_register(chip, CLK_SEL, &val);
798 chip->asic_code = val == 0 ? 1 : 0;
800 if (chip->asic_code) {
801 retval = rtsx_read_phy_register(chip, 0x1C, ®);
802 if (retval != STATUS_SUCCESS) {
807 dev_dbg(rtsx_dev(chip), "Value of phy register 0x1C is 0x%x\n",
809 chip->ic_version = (reg >> 4) & 0x07;
810 chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0;
813 retval = rtsx_read_register(chip, 0xFE80, &val);
818 chip->ic_version = val;
819 chip->phy_debug_mode = 0;
822 retval = rtsx_read_register(chip, PDINFO, &val);
827 dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
828 chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
830 retval = rtsx_read_register(chip, 0xFE50, &val);
835 chip->hw_bypass_sd = val & 0x01 ? 1 : 0;
837 rtsx_read_config_byte(chip, 0x0E, &val);
839 SET_SDIO_EXIST(chip);
841 CLR_SDIO_EXIST(chip);
843 if (chip->use_hw_setting) {
844 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
849 chip->auto_delink_en = val & 0x80 ? 1 : 0;
852 return STATUS_SUCCESS;
855 static int rts5288_init(struct rtsx_chip *chip)
858 u8 val = 0, max_func;
861 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
866 retval = rtsx_read_register(chip, CLK_SEL, &val);
871 chip->asic_code = val == 0 ? 1 : 0;
873 chip->ic_version = 0;
874 chip->phy_debug_mode = 0;
876 retval = rtsx_read_register(chip, PDINFO, &val);
881 dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
882 chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
884 retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val);
889 dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val);
890 chip->baro_pkg = val & 0x04 ? QFN : LQFP;
892 retval = rtsx_read_register(chip, 0xFE5A, &val);
897 chip->hw_bypass_sd = val & 0x10 ? 1 : 0;
899 retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
900 if (retval != STATUS_SUCCESS) {
905 max_func = (u8)((lval >> 29) & 0x07);
906 dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func);
907 if (max_func == 0x02)
908 SET_SDIO_EXIST(chip);
910 CLR_SDIO_EXIST(chip);
912 if (chip->use_hw_setting) {
913 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
918 chip->auto_delink_en = val & 0x80 ? 1 : 0;
920 if (CHECK_BARO_PKG(chip, LQFP))
921 chip->lun_mode = SD_MS_1LUN;
923 chip->lun_mode = DEFAULT_SINGLE;
926 return STATUS_SUCCESS;
929 int rtsx_init_chip(struct rtsx_chip *chip)
931 struct sd_info *sd_card = &chip->sd_card;
932 struct xd_info *xd_card = &chip->xd_card;
933 struct ms_info *ms_card = &chip->ms_card;
937 dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n",
938 chip->vendor_id, chip->product_id);
940 chip->ic_version = 0;
946 memset(xd_card, 0, sizeof(struct xd_info));
947 memset(sd_card, 0, sizeof(struct sd_info));
948 memset(ms_card, 0, sizeof(struct ms_info));
950 chip->xd_reset_counter = 0;
951 chip->sd_reset_counter = 0;
952 chip->ms_reset_counter = 0;
954 chip->xd_show_cnt = MAX_SHOW_CNT;
955 chip->sd_show_cnt = MAX_SHOW_CNT;
956 chip->ms_show_cnt = MAX_SHOW_CNT;
959 chip->auto_delink_cnt = 0;
960 chip->auto_delink_allowed = 1;
961 rtsx_set_stat(chip, RTSX_STAT_INIT);
963 chip->aspm_enabled = 0;
964 chip->chip_insert_with_sdio = 0;
967 chip->sdio_counter = 0;
969 chip->phy_debug_mode = 0;
970 chip->sdio_func_exist = 0;
971 memset(chip->sdio_raw_data, 0, 12);
973 for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
974 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
975 chip->rw_fail_cnt[i] = 0;
978 if (!check_sd_speed_prior(chip->sd_speed_prior))
979 chip->sd_speed_prior = 0x01040203;
981 dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n",
982 chip->sd_speed_prior);
984 if (!check_sd_current_prior(chip->sd_current_prior))
985 chip->sd_current_prior = 0x00010203;
987 dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n",
988 chip->sd_current_prior);
990 if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0))
991 chip->sd_ddr_tx_phase = 0;
993 if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0))
994 chip->mmc_ddr_tx_phase = 0;
996 retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0);
1002 retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07);
1007 dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n",
1008 chip->use_hw_setting);
1010 if (CHECK_PID(chip, 0x5208)) {
1011 retval = rts5208_init(chip);
1012 if (retval != STATUS_SUCCESS) {
1017 } else if (CHECK_PID(chip, 0x5288)) {
1018 retval = rts5288_init(chip);
1019 if (retval != STATUS_SUCCESS) {
1025 if (chip->ss_en == 2)
1028 dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code);
1029 dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version);
1030 dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n",
1031 chip->phy_debug_mode);
1032 dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n",
1033 chip->aux_pwr_exist);
1034 dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n",
1035 chip->sdio_func_exist);
1036 dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n",
1037 chip->hw_bypass_sd);
1038 dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n",
1039 chip->aspm_l0s_l1_en);
1040 dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode);
1041 dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n",
1042 chip->auto_delink_en);
1043 dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en);
1044 dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg);
1046 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1047 chip->card2lun[SD_CARD] = 0;
1048 chip->card2lun[MS_CARD] = 1;
1049 chip->card2lun[XD_CARD] = 0xFF;
1050 chip->lun2card[0] = SD_CARD;
1051 chip->lun2card[1] = MS_CARD;
1053 SET_SDIO_IGNORED(chip);
1054 } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
1055 chip->card2lun[SD_CARD] = 0;
1056 chip->card2lun[MS_CARD] = 0;
1057 chip->card2lun[XD_CARD] = 0xFF;
1058 chip->lun2card[0] = SD_CARD | MS_CARD;
1061 chip->card2lun[XD_CARD] = 0;
1062 chip->card2lun[SD_CARD] = 0;
1063 chip->card2lun[MS_CARD] = 0;
1064 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
1068 retval = rtsx_reset_chip(chip);
1069 if (retval != STATUS_SUCCESS) {
1074 return STATUS_SUCCESS;
1077 void rtsx_release_chip(struct rtsx_chip *chip)
1079 xd_free_l2p_tbl(chip);
1080 ms_free_l2p_tbl(chip);
1081 chip->card_exist = 0;
1082 chip->card_ready = 0;
1085 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1086 static inline void rtsx_blink_led(struct rtsx_chip *chip)
1088 if (chip->card_exist && chip->blink_led) {
1089 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
1090 chip->led_toggle_counter++;
1092 chip->led_toggle_counter = 0;
1093 toggle_gpio(chip, LED_GPIO);
1099 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
1101 bool reg_changed, maybe_support_aspm;
1103 u8 reg0 = 0, reg1 = 0;
1105 maybe_support_aspm = false;
1106 reg_changed = false;
1107 rtsx_read_config_byte(chip, LCTLR, ®0);
1108 if (chip->aspm_level[0] != reg0) {
1110 chip->aspm_level[0] = reg0;
1112 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1113 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
1115 if (chip->aspm_level[1] != reg1) {
1117 chip->aspm_level[1] = reg1;
1120 if ((reg0 & 0x03) && (reg1 & 0x03))
1121 maybe_support_aspm = true;
1125 maybe_support_aspm = true;
1129 if (maybe_support_aspm)
1130 chip->aspm_l0s_l1_en = 0x03;
1132 dev_dbg(rtsx_dev(chip), "aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
1133 chip->aspm_level[0], chip->aspm_level[1]);
1135 if (chip->aspm_l0s_l1_en) {
1136 chip->aspm_enabled = 1;
1138 chip->aspm_enabled = 0;
1139 chip->sdio_aspm = 0;
1141 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
1142 0x30 | chip->aspm_level[0] |
1143 (chip->aspm_level[1] << 2));
1147 static void rtsx_manage_ocp(struct rtsx_chip *chip)
1153 rtsx_read_register(chip, OCPSTAT, &chip->ocp_stat);
1155 if (chip->card_exist & SD_CARD)
1156 sd_power_off_card3v3(chip);
1157 else if (chip->card_exist & MS_CARD)
1158 ms_power_off_card3v3(chip);
1159 else if (chip->card_exist & XD_CARD)
1160 xd_power_off_card3v3(chip);
1166 static void rtsx_manage_sd_lock(struct rtsx_chip *chip)
1168 #ifdef SUPPORT_SD_LOCK
1169 struct sd_info *sd_card = &chip->sd_card;
1172 if (!sd_card->sd_erase_status)
1175 if (chip->card_exist & SD_CARD) {
1176 rtsx_read_register(chip, 0xFD30, &val);
1178 sd_card->sd_erase_status = SD_NOT_ERASE;
1179 sd_card->sd_lock_notify = 1;
1180 chip->need_reinit |= SD_CARD;
1183 sd_card->sd_erase_status = SD_NOT_ERASE;
1188 static bool rtsx_is_ss_allowed(struct rtsx_chip *chip)
1192 if (!chip->ss_en || CHECK_PID(chip, 0x5288))
1195 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1196 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
1204 static void rtsx_manage_ss(struct rtsx_chip *chip)
1206 if (!rtsx_is_ss_allowed(chip) || chip->sd_io)
1209 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1210 chip->ss_counter = 0;
1214 if (chip->ss_counter < (chip->ss_idle_period / POLLING_INTERVAL))
1217 rtsx_exclusive_enter_ss(chip);
1220 static void rtsx_manage_aspm(struct rtsx_chip *chip)
1224 if (!CHECK_PID(chip, 0x5208))
1227 rtsx_monitor_aspm_config(chip);
1229 #ifdef SUPPORT_SDIO_ASPM
1230 if (!CHK_SDIO_EXIST(chip) || CHK_SDIO_IGNORED(chip) ||
1231 !chip->aspm_l0s_l1_en || !chip->dynamic_aspm)
1235 dynamic_configure_sdio_aspm(chip);
1239 if (chip->sdio_aspm)
1242 dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
1243 data = 0x30 | (chip->aspm_level[1] << 2);
1244 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, data);
1245 chip->sdio_aspm = 1;
1249 static void rtsx_manage_idle(struct rtsx_chip *chip)
1251 if (chip->idle_counter < IDLE_MAX_COUNT) {
1252 chip->idle_counter++;
1256 if (rtsx_get_stat(chip) == RTSX_STAT_IDLE)
1259 dev_dbg(rtsx_dev(chip), "Idle state!\n");
1260 rtsx_set_stat(chip, RTSX_STAT_IDLE);
1262 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1263 chip->led_toggle_counter = 0;
1265 rtsx_force_power_on(chip, SSC_PDCTL);
1267 turn_off_led(chip, LED_GPIO);
1269 if (chip->auto_power_down && !chip->card_ready && !chip->sd_io)
1270 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1273 static void rtsx_manage_2lun_mode(struct rtsx_chip *chip)
1278 sd_oc = chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER);
1279 ms_oc = chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER);
1282 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1285 if (sd_oc && (chip->card_exist & SD_CARD)) {
1286 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1287 card_power_off(chip, SD_CARD);
1288 chip->card_fail |= SD_CARD;
1291 if (ms_oc && (chip->card_exist & MS_CARD)) {
1292 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1293 card_power_off(chip, MS_CARD);
1294 chip->card_fail |= MS_CARD;
1299 static void rtsx_manage_1lun_mode(struct rtsx_chip *chip)
1302 if (!(chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)))
1305 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1308 if (chip->card_exist & SD_CARD) {
1309 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1310 chip->card_fail |= SD_CARD;
1311 } else if (chip->card_exist & MS_CARD) {
1312 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1313 chip->card_fail |= MS_CARD;
1314 } else if (chip->card_exist & XD_CARD) {
1315 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
1316 chip->card_fail |= XD_CARD;
1318 card_power_off(chip, SD_CARD);
1322 static void rtsx_delink_stage1(struct rtsx_chip *chip, int enter_L1,
1327 rtsx_set_stat(chip, RTSX_STAT_DELINK);
1329 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1330 rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1332 if (chip->card_exist)
1333 dev_dbg(rtsx_dev(chip), "False card inserted, do force delink\n");
1335 dev_dbg(rtsx_dev(chip), "No card inserted, do delink\n");
1338 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1340 if (chip->card_exist)
1345 rtsx_write_register(chip, CHANGE_LINK_STATE, val, val);
1348 rtsx_enter_L1(chip);
1350 if (chip->card_exist)
1351 chip->auto_delink_cnt = stage3_cnt + 1;
1354 static void rtsx_delink_stage(struct rtsx_chip *chip)
1356 int delink_stage1_cnt, delink_stage2_cnt, delink_stage3_cnt;
1359 if (!chip->auto_delink_en || !chip->auto_delink_allowed ||
1360 chip->card_ready || chip->card_ejected || chip->sd_io) {
1361 chip->auto_delink_cnt = 0;
1365 enter_L1 = chip->auto_delink_in_L1 &&
1366 (chip->aspm_l0s_l1_en || chip->ss_en);
1368 delink_stage1_cnt = chip->delink_stage1_step;
1369 delink_stage2_cnt = delink_stage1_cnt + chip->delink_stage2_step;
1370 delink_stage3_cnt = delink_stage2_cnt + chip->delink_stage3_step;
1372 if (chip->auto_delink_cnt > delink_stage3_cnt)
1375 if (chip->auto_delink_cnt == delink_stage1_cnt)
1376 rtsx_delink_stage1(chip, enter_L1, delink_stage3_cnt);
1378 if (chip->auto_delink_cnt == delink_stage2_cnt) {
1379 dev_dbg(rtsx_dev(chip), "Try to do force delink\n");
1384 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1385 rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1387 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A);
1390 chip->auto_delink_cnt++;
1393 void rtsx_polling_func(struct rtsx_chip *chip)
1395 if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
1398 if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
1401 if (chip->polling_config) {
1404 rtsx_read_config_byte(chip, 0, &val);
1407 if (rtsx_chk_stat(chip, RTSX_STAT_SS))
1410 rtsx_manage_ocp(chip);
1412 rtsx_manage_sd_lock(chip);
1414 rtsx_init_cards(chip);
1416 rtsx_manage_ss(chip);
1418 rtsx_manage_aspm(chip);
1420 rtsx_manage_idle(chip);
1422 switch (rtsx_get_stat(chip)) {
1424 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1425 rtsx_blink_led(chip);
1427 do_remaining_work(chip);
1430 case RTSX_STAT_IDLE:
1431 if (chip->sd_io && !chip->sd_int)
1432 try_to_switch_sdio_ctrl(chip);
1434 rtsx_enable_aspm(chip);
1441 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1442 rtsx_manage_2lun_mode(chip);
1444 rtsx_manage_1lun_mode(chip);
1447 rtsx_delink_stage(chip);
1450 void rtsx_undo_delink(struct rtsx_chip *chip)
1452 chip->auto_delink_allowed = 0;
1453 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x00);
1457 * rtsx_stop_cmd - stop command transfer and DMA transfer
1458 * @chip: Realtek's card reader chip
1459 * @card: flash card type
1461 * Stop command transfer and DMA transfer.
1462 * This function is called in error handler.
1464 void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1468 for (i = 0; i <= 8; i++) {
1469 int addr = RTSX_HCBAR + i * 4;
1472 reg = rtsx_readl(chip, addr);
1473 dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg);
1475 rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1476 rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1478 for (i = 0; i < 16; i++) {
1479 u16 addr = 0xFE20 + (u16)i;
1482 rtsx_read_register(chip, addr, &val);
1483 dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val);
1486 rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1487 rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1490 #define MAX_RW_REG_CNT 1024
1492 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1497 val |= (u32)(addr & 0x3FFF) << 16;
1498 val |= (u32)mask << 8;
1501 rtsx_writel(chip, RTSX_HAIMR, val);
1503 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1504 val = rtsx_readl(chip, RTSX_HAIMR);
1505 if ((val & (1 << 31)) == 0) {
1506 if (data != (u8)val) {
1511 return STATUS_SUCCESS;
1516 return STATUS_TIMEDOUT;
1519 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1527 val |= (u32)(addr & 0x3FFF) << 16;
1529 rtsx_writel(chip, RTSX_HAIMR, val);
1531 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1532 val = rtsx_readl(chip, RTSX_HAIMR);
1533 if ((val & (1 << 31)) == 0)
1537 if (i >= MAX_RW_REG_CNT) {
1539 return STATUS_TIMEDOUT;
1543 *data = (u8)(val & 0xFF);
1545 return STATUS_SUCCESS;
1548 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask,
1555 for (i = 0; i < 4; i++) {
1557 retval = rtsx_write_register(chip, CFGDATA0 + i,
1559 (u8)(val & mask & 0xFF));
1571 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1576 retval = rtsx_write_register(chip, CFGADDR1, 0xFF,
1583 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1584 0x80 | mode | ((func_no & 0x03) << 4));
1590 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1591 retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1596 if ((tmp & 0x80) == 0)
1601 return STATUS_SUCCESS;
1604 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1611 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1616 retval = rtsx_write_register(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1621 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1622 0x80 | ((func_no & 0x03) << 4));
1628 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1629 retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1634 if ((tmp & 0x80) == 0)
1638 for (i = 0; i < 4; i++) {
1639 retval = rtsx_read_register(chip, CFGDATA0 + i, &tmp);
1644 data |= (u32)tmp << (i * 8);
1650 return STATUS_SUCCESS;
1653 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1657 u16 offset = addr % 4;
1658 u16 aligned_addr = addr - offset;
1664 return STATUS_NOMEM;
1667 if ((len + offset) % 4)
1668 dw_len = (len + offset) / 4 + 1;
1670 dw_len = (len + offset) / 4;
1672 dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1674 data = vzalloc(dw_len * 4);
1677 return STATUS_NOMEM;
1680 mask = vzalloc(dw_len * 4);
1684 return STATUS_NOMEM;
1688 for (i = 0; i < len; i++) {
1689 mask[j] |= 0xFF << (offset * 8);
1690 data[j] |= buf[i] << (offset * 8);
1691 if (++offset == 4) {
1697 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, mask,
1699 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, data,
1702 for (i = 0; i < dw_len; i++) {
1703 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4,
1705 if (retval != STATUS_SUCCESS) {
1716 return STATUS_SUCCESS;
1719 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1723 u16 offset = addr % 4;
1724 u16 aligned_addr = addr - offset;
1728 if ((len + offset) % 4)
1729 dw_len = (len + offset) / 4 + 1;
1731 dw_len = (len + offset) / 4;
1733 dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1735 data = vmalloc(dw_len * 4);
1738 return STATUS_NOMEM;
1741 for (i = 0; i < dw_len; i++) {
1742 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4,
1744 if (retval != STATUS_SUCCESS) {
1754 for (i = 0; i < len; i++) {
1755 buf[i] = (u8)(data[j] >> (offset * 8));
1756 if (++offset == 4) {
1765 return STATUS_SUCCESS;
1768 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1771 bool finished = false;
1775 retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val);
1780 retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1785 retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1790 retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x81);
1796 for (i = 0; i < 100000; i++) {
1797 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1802 if (!(tmp & 0x80)) {
1813 return STATUS_SUCCESS;
1816 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1819 bool finished = false;
1824 retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1829 retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x80);
1835 for (i = 0; i < 100000; i++) {
1836 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1841 if (!(tmp & 0x80)) {
1852 retval = rtsx_read_register(chip, PHYDATA0, &tmp);
1858 retval = rtsx_read_register(chip, PHYDATA1, &tmp);
1863 data |= (u16)tmp << 8;
1868 return STATUS_SUCCESS;
1871 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1877 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 0x80 | addr);
1883 for (i = 0; i < 100; i++) {
1884 retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1896 return STATUS_TIMEDOUT;
1899 retval = rtsx_read_register(chip, EFUSE_DATA, &data);
1907 return STATUS_SUCCESS;
1910 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1914 u8 data = 0, tmp = 0xFF;
1916 for (i = 0; i < 8; i++) {
1917 if (val & (u8)(1 << i))
1920 tmp &= (~(u8)(1 << i));
1921 dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr);
1923 retval = rtsx_write_register(chip, EFUSE_DATA, 0xFF, tmp);
1928 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF,
1935 for (j = 0; j < 100; j++) {
1936 retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1948 return STATUS_TIMEDOUT;
1954 return STATUS_SUCCESS;
1957 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1962 retval = rtsx_read_phy_register(chip, reg, &value);
1963 if (retval != STATUS_SUCCESS) {
1968 if (value & (1 << bit)) {
1969 value &= ~(1 << bit);
1970 retval = rtsx_write_phy_register(chip, reg, value);
1971 if (retval != STATUS_SUCCESS) {
1977 return STATUS_SUCCESS;
1980 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1985 retval = rtsx_read_phy_register(chip, reg, &value);
1986 if (retval != STATUS_SUCCESS) {
1991 if ((value & (1 << bit)) == 0) {
1992 value |= (1 << bit);
1993 retval = rtsx_write_phy_register(chip, reg, value);
1994 if (retval != STATUS_SUCCESS) {
2000 return STATUS_SUCCESS;
2003 int rtsx_check_link_ready(struct rtsx_chip *chip)
2008 retval = rtsx_read_register(chip, IRQSTAT0, &val);
2014 dev_dbg(rtsx_dev(chip), "IRQSTAT0: 0x%x\n", val);
2015 if (val & LINK_RDY_INT) {
2016 dev_dbg(rtsx_dev(chip), "Delinked!\n");
2017 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
2021 return STATUS_SUCCESS;
2024 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
2028 dev_dbg(rtsx_dev(chip), "%04x set pm_dstate to %d\n",
2029 chip->product_id, dstate);
2031 if (CHK_SDIO_EXIST(chip)) {
2034 if (CHECK_PID(chip, 0x5288))
2039 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
2040 dev_dbg(rtsx_dev(chip), "pm_dstate of function %d: 0x%x\n",
2041 (int)func_no, ultmp);
2042 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
2045 rtsx_write_config_byte(chip, 0x44, dstate);
2046 rtsx_write_config_byte(chip, 0x45, 0);
2049 void rtsx_enter_L1(struct rtsx_chip *chip)
2051 rtsx_handle_pm_dstate(chip, 2);
2054 void rtsx_exit_L1(struct rtsx_chip *chip)
2056 rtsx_write_config_byte(chip, 0x44, 0);
2057 rtsx_write_config_byte(chip, 0x45, 0);
2060 void rtsx_enter_ss(struct rtsx_chip *chip)
2062 dev_dbg(rtsx_dev(chip), "Enter Selective Suspend State!\n");
2064 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
2066 if (chip->power_down_in_ss) {
2067 rtsx_power_off_card(chip);
2068 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2071 if (CHK_SDIO_EXIST(chip))
2072 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
2073 0xC0, 0xFF00, 0x0100);
2075 if (chip->auto_delink_en) {
2076 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
2078 if (!chip->phy_debug_mode) {
2081 tmp = rtsx_readl(chip, RTSX_BIER);
2083 rtsx_writel(chip, RTSX_BIER, tmp);
2086 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
2089 rtsx_enter_L1(chip);
2091 RTSX_CLR_DELINK(chip);
2092 rtsx_set_stat(chip, RTSX_STAT_SS);
2095 void rtsx_exit_ss(struct rtsx_chip *chip)
2097 dev_dbg(rtsx_dev(chip), "Exit Selective Suspend State!\n");
2101 if (chip->power_down_in_ss) {
2102 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
2106 if (RTSX_TST_DELINK(chip)) {
2107 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
2108 rtsx_reinit_cards(chip, 1);
2109 RTSX_CLR_DELINK(chip);
2110 } else if (chip->power_down_in_ss) {
2111 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
2112 rtsx_reinit_cards(chip, 0);
2116 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
2118 u32 status, int_enable;
2119 bool exit_ss = false;
2127 chip->ss_counter = 0;
2128 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
2131 rtsx_set_stat(chip, RTSX_STAT_RUN);
2135 int_enable = rtsx_readl(chip, RTSX_BIER);
2136 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
2138 if (((chip->int_reg & int_enable) == 0) ||
2139 (chip->int_reg == 0xFFFFFFFF))
2142 status = chip->int_reg &= (int_enable | 0x7FFFFF);
2144 if (status & CARD_INT) {
2145 chip->auto_delink_cnt = 0;
2147 if (status & SD_INT) {
2148 if (status & SD_EXIST) {
2149 set_bit(SD_NR, &chip->need_reset);
2151 set_bit(SD_NR, &chip->need_release);
2152 chip->sd_reset_counter = 0;
2153 chip->sd_show_cnt = 0;
2154 clear_bit(SD_NR, &chip->need_reset);
2158 * If multi-luns, it's possible that
2159 * when plugging/unplugging one card
2160 * there is another card which still
2161 * exists in the slot. In this case,
2162 * all existed cards should be reset.
2164 if (exit_ss && (status & SD_EXIST))
2165 set_bit(SD_NR, &chip->need_reinit);
2167 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
2168 if (status & XD_INT) {
2169 if (status & XD_EXIST) {
2170 set_bit(XD_NR, &chip->need_reset);
2172 set_bit(XD_NR, &chip->need_release);
2173 chip->xd_reset_counter = 0;
2174 chip->xd_show_cnt = 0;
2175 clear_bit(XD_NR, &chip->need_reset);
2178 if (exit_ss && (status & XD_EXIST))
2179 set_bit(XD_NR, &chip->need_reinit);
2182 if (status & MS_INT) {
2183 if (status & MS_EXIST) {
2184 set_bit(MS_NR, &chip->need_reset);
2186 set_bit(MS_NR, &chip->need_release);
2187 chip->ms_reset_counter = 0;
2188 chip->ms_show_cnt = 0;
2189 clear_bit(MS_NR, &chip->need_reset);
2192 if (exit_ss && (status & MS_EXIST))
2193 set_bit(MS_NR, &chip->need_reinit);
2198 chip->ocp_int = ocp_int & status;
2201 if (chip->sd_io && (chip->int_reg & DATA_DONE_INT))
2202 chip->int_reg &= ~(u32)DATA_DONE_INT;
2204 return STATUS_SUCCESS;
2207 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
2211 dev_dbg(rtsx_dev(chip), "%s, pm_stat = %d\n", __func__, pm_stat);
2213 rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
2215 retval = rtsx_force_power_on(chip, SSC_PDCTL);
2216 if (retval != STATUS_SUCCESS)
2219 rtsx_release_cards(chip);
2220 rtsx_disable_bus_int(chip);
2221 turn_off_led(chip, LED_GPIO);
2223 #ifdef HW_AUTO_SWITCH_SD_BUS
2225 chip->sdio_in_charge = 1;
2226 if (CHECK_PID(chip, 0x5208)) {
2227 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2228 /* Enable sdio_bus_auto_switch */
2229 rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
2230 } else if (CHECK_PID(chip, 0x5288)) {
2231 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2232 /* Enable sdio_bus_auto_switch */
2233 rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
2238 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
2239 /* u_force_clkreq_0 */
2240 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
2243 if (pm_stat == PM_S1) {
2244 dev_dbg(rtsx_dev(chip), "Host enter S1\n");
2245 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2247 } else if (pm_stat == PM_S3) {
2248 if (chip->s3_pwr_off_delay > 0)
2249 wait_timeout(chip->s3_pwr_off_delay);
2251 dev_dbg(rtsx_dev(chip), "Host enter S3\n");
2252 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2256 if (chip->do_delink_before_power_down && chip->auto_delink_en)
2257 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
2259 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2263 chip->card_exist = 0;
2266 void rtsx_enable_aspm(struct rtsx_chip *chip)
2268 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && !chip->aspm_enabled) {
2269 dev_dbg(rtsx_dev(chip), "Try to enable ASPM\n");
2270 chip->aspm_enabled = 1;
2272 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2273 rtsx_write_phy_register(chip, 0x07, 0);
2274 if (CHECK_PID(chip, 0x5208)) {
2275 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
2276 0x30 | chip->aspm_level[0]);
2278 rtsx_write_config_byte(chip, LCTLR,
2279 chip->aspm_l0s_l1_en);
2282 if (CHK_SDIO_EXIST(chip)) {
2283 u16 val = chip->aspm_l0s_l1_en | 0x0100;
2285 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
2291 void rtsx_disable_aspm(struct rtsx_chip *chip)
2293 if (CHECK_PID(chip, 0x5208))
2294 rtsx_monitor_aspm_config(chip);
2296 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && chip->aspm_enabled) {
2297 dev_dbg(rtsx_dev(chip), "Try to disable ASPM\n");
2298 chip->aspm_enabled = 0;
2300 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2301 rtsx_write_phy_register(chip, 0x07, 0x0129);
2302 if (CHECK_PID(chip, 0x5208))
2303 rtsx_write_register(chip, ASPM_FORCE_CTL,
2306 rtsx_write_config_byte(chip, LCTLR, 0x00);
2312 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2321 return STATUS_ERROR;
2325 reg_addr = PPBUF_BASE2;
2326 for (i = 0; i < buf_len/256; i++) {
2327 rtsx_init_cmd(chip);
2329 for (j = 0; j < 256; j++)
2330 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2332 retval = rtsx_send_cmd(chip, 0, 250);
2338 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
2343 rtsx_init_cmd(chip);
2345 for (j = 0; j < buf_len%256; j++)
2346 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2348 retval = rtsx_send_cmd(chip, 0, 250);
2355 memcpy(ptr, rtsx_get_cmd_data(chip), buf_len%256);
2357 return STATUS_SUCCESS;
2360 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2369 return STATUS_ERROR;
2373 reg_addr = PPBUF_BASE2;
2374 for (i = 0; i < buf_len/256; i++) {
2375 rtsx_init_cmd(chip);
2377 for (j = 0; j < 256; j++) {
2378 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2383 retval = rtsx_send_cmd(chip, 0, 250);
2391 rtsx_init_cmd(chip);
2393 for (j = 0; j < buf_len%256; j++) {
2394 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2399 retval = rtsx_send_cmd(chip, 0, 250);
2406 return STATUS_SUCCESS;
2409 int rtsx_check_chip_exist(struct rtsx_chip *chip)
2411 if (rtsx_readl(chip, 0) == 0xFFFFFFFF) {
2416 return STATUS_SUCCESS;
2419 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
2424 if (ctl & SSC_PDCTL)
2425 mask |= SSC_POWER_DOWN;
2428 if (ctl & OC_PDCTL) {
2429 mask |= SD_OC_POWER_DOWN;
2430 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2431 mask |= MS_OC_POWER_DOWN;
2436 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
2437 if (retval != STATUS_SUCCESS) {
2442 if (CHECK_PID(chip, 0x5288))
2446 return STATUS_SUCCESS;
2449 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
2452 u8 mask = 0, val = 0;
2454 if (ctl & SSC_PDCTL)
2455 mask |= SSC_POWER_DOWN;
2458 if (ctl & OC_PDCTL) {
2459 mask |= SD_OC_POWER_DOWN;
2460 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2461 mask |= MS_OC_POWER_DOWN;
2467 retval = rtsx_write_register(chip, FPDCTL, mask, val);
2468 if (retval != STATUS_SUCCESS) {
2474 return STATUS_SUCCESS;