4 * Copyright IBM, Corp. 2012-2013
7 * Anthony Liguori <aliguori@us.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
14 #include "libqos/pci.h"
16 #include "hw/pci/pci_regs.h"
19 void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
20 void (*func)(QPCIDevice *dev, int devfn, void *data),
25 for (slot = 0; slot < 32; slot++) {
28 for (fn = 0; fn < 8; fn++) {
31 dev = qpci_device_find(bus, QPCI_DEVFN(slot, fn));
36 if (vendor_id != -1 &&
37 qpci_config_readw(dev, PCI_VENDOR_ID) != vendor_id) {
42 if (device_id != -1 &&
43 qpci_config_readw(dev, PCI_DEVICE_ID) != device_id) {
48 func(dev, QPCI_DEVFN(slot, fn), data);
53 QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
57 dev = g_malloc0(sizeof(*dev));
61 if (qpci_config_readw(dev, PCI_VENDOR_ID) == 0xFFFF) {
69 void qpci_device_enable(QPCIDevice *dev)
73 /* FIXME -- does this need to be a bus callout? */
74 cmd = qpci_config_readw(dev, PCI_COMMAND);
75 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
76 qpci_config_writew(dev, PCI_COMMAND, cmd);
78 /* Verify the bits are now set. */
79 cmd = qpci_config_readw(dev, PCI_COMMAND);
80 g_assert_cmphex(cmd & PCI_COMMAND_IO, ==, PCI_COMMAND_IO);
81 g_assert_cmphex(cmd & PCI_COMMAND_MEMORY, ==, PCI_COMMAND_MEMORY);
82 g_assert_cmphex(cmd & PCI_COMMAND_MASTER, ==, PCI_COMMAND_MASTER);
85 uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id)
88 uint8_t addr = qpci_config_readb(dev, PCI_CAPABILITY_LIST);
91 cap = qpci_config_readb(dev, addr);
93 addr = qpci_config_readb(dev, addr + PCI_CAP_LIST_NEXT);
95 } while (cap != id && addr != 0);
100 void qpci_msix_enable(QPCIDevice *dev)
109 addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
110 g_assert_cmphex(addr, !=, 0);
112 val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
113 qpci_config_writew(dev, addr + PCI_MSIX_FLAGS, val | PCI_MSIX_FLAGS_ENABLE);
115 table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE);
116 bir_table = table & PCI_MSIX_FLAGS_BIRMASK;
117 offset = qpci_iomap(dev, bir_table, NULL);
118 dev->msix_table = offset + (table & ~PCI_MSIX_FLAGS_BIRMASK);
120 table = qpci_config_readl(dev, addr + PCI_MSIX_PBA);
121 bir_pba = table & PCI_MSIX_FLAGS_BIRMASK;
122 if (bir_pba != bir_table) {
123 offset = qpci_iomap(dev, bir_pba, NULL);
125 dev->msix_pba = offset + (table & ~PCI_MSIX_FLAGS_BIRMASK);
127 g_assert(dev->msix_table != NULL);
128 g_assert(dev->msix_pba != NULL);
129 dev->msix_enabled = true;
132 void qpci_msix_disable(QPCIDevice *dev)
137 g_assert(dev->msix_enabled);
138 addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
139 g_assert_cmphex(addr, !=, 0);
140 val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
141 qpci_config_writew(dev, addr + PCI_MSIX_FLAGS,
142 val & ~PCI_MSIX_FLAGS_ENABLE);
144 qpci_iounmap(dev, dev->msix_table);
145 qpci_iounmap(dev, dev->msix_pba);
146 dev->msix_enabled = 0;
147 dev->msix_table = NULL;
148 dev->msix_pba = NULL;
151 bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry)
154 uint8_t bit_n = entry % 32;
155 void *addr = dev->msix_pba + (entry / 32) * PCI_MSIX_ENTRY_SIZE / 4;
157 g_assert(dev->msix_enabled);
158 pba_entry = qpci_io_readl(dev, addr);
159 qpci_io_writel(dev, addr, pba_entry & ~(1 << bit_n));
160 return (pba_entry & (1 << bit_n)) != 0;
163 bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry)
167 void *vector_addr = dev->msix_table + (entry * PCI_MSIX_ENTRY_SIZE);
169 g_assert(dev->msix_enabled);
170 addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
171 g_assert_cmphex(addr, !=, 0);
172 val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
174 if (val & PCI_MSIX_FLAGS_MASKALL) {
177 return (qpci_io_readl(dev, vector_addr + PCI_MSIX_ENTRY_VECTOR_CTRL)
178 & PCI_MSIX_ENTRY_CTRL_MASKBIT) != 0;
182 uint16_t qpci_msix_table_size(QPCIDevice *dev)
187 addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
188 g_assert_cmphex(addr, !=, 0);
190 control = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
191 return (control & PCI_MSIX_FLAGS_QSIZE) + 1;
194 uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)
196 return dev->bus->config_readb(dev->bus, dev->devfn, offset);
199 uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset)
201 return dev->bus->config_readw(dev->bus, dev->devfn, offset);
204 uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset)
206 return dev->bus->config_readl(dev->bus, dev->devfn, offset);
210 void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value)
212 dev->bus->config_writeb(dev->bus, dev->devfn, offset, value);
215 void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value)
217 dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
220 void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value)
222 dev->bus->config_writel(dev->bus, dev->devfn, offset, value);
226 uint8_t qpci_io_readb(QPCIDevice *dev, void *data)
228 return dev->bus->io_readb(dev->bus, data);
231 uint16_t qpci_io_readw(QPCIDevice *dev, void *data)
233 return dev->bus->io_readw(dev->bus, data);
236 uint32_t qpci_io_readl(QPCIDevice *dev, void *data)
238 return dev->bus->io_readl(dev->bus, data);
242 void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value)
244 dev->bus->io_writeb(dev->bus, data, value);
247 void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value)
249 dev->bus->io_writew(dev->bus, data, value);
252 void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value)
254 dev->bus->io_writel(dev->bus, data, value);
257 void *qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr)
259 return dev->bus->iomap(dev->bus, dev, barno, sizeptr);
262 void qpci_iounmap(QPCIDevice *dev, void *data)
264 dev->bus->iounmap(dev->bus, data);