2 * Tiny Code Interpreter for QEMU
4 * Copyright (c) 2009, 2011 Stefan Weil
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 /* Defining NDEBUG disables assertions (which makes the code faster). */
23 #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
27 #include "qemu-common.h"
28 #include "exec/exec-all.h" /* MAX_OPC_PARAM_IARGS */
29 #include "exec/cpu_ldst.h"
32 /* Marker for missing code. */
35 fprintf(stderr, "TODO %s:%u: %s()\n", \
36 __FILE__, __LINE__, __func__); \
40 #if MAX_OPC_PARAM_IARGS != 5
41 # error Fix needed, number of supported input arguments changed!
43 #if TCG_TARGET_REG_BITS == 32
44 typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
45 tcg_target_ulong, tcg_target_ulong,
46 tcg_target_ulong, tcg_target_ulong,
47 tcg_target_ulong, tcg_target_ulong,
48 tcg_target_ulong, tcg_target_ulong);
50 typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
51 tcg_target_ulong, tcg_target_ulong,
55 /* Targets which don't use GETPC also don't need tci_tb_ptr
56 which makes them a little faster. */
61 static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS];
63 static tcg_target_ulong tci_read_reg(TCGReg index)
65 assert(index < ARRAY_SIZE(tci_reg));
66 return tci_reg[index];
69 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
70 static int8_t tci_read_reg8s(TCGReg index)
72 return (int8_t)tci_read_reg(index);
76 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
77 static int16_t tci_read_reg16s(TCGReg index)
79 return (int16_t)tci_read_reg(index);
83 #if TCG_TARGET_REG_BITS == 64
84 static int32_t tci_read_reg32s(TCGReg index)
86 return (int32_t)tci_read_reg(index);
90 static uint8_t tci_read_reg8(TCGReg index)
92 return (uint8_t)tci_read_reg(index);
95 static uint16_t tci_read_reg16(TCGReg index)
97 return (uint16_t)tci_read_reg(index);
100 static uint32_t tci_read_reg32(TCGReg index)
102 return (uint32_t)tci_read_reg(index);
105 #if TCG_TARGET_REG_BITS == 64
106 static uint64_t tci_read_reg64(TCGReg index)
108 return tci_read_reg(index);
112 static void tci_write_reg(TCGReg index, tcg_target_ulong value)
114 assert(index < ARRAY_SIZE(tci_reg));
115 assert(index != TCG_AREG0);
116 assert(index != TCG_REG_CALL_STACK);
117 tci_reg[index] = value;
120 #if TCG_TARGET_REG_BITS == 64
121 static void tci_write_reg32s(TCGReg index, int32_t value)
123 tci_write_reg(index, value);
127 static void tci_write_reg8(TCGReg index, uint8_t value)
129 tci_write_reg(index, value);
132 static void tci_write_reg32(TCGReg index, uint32_t value)
134 tci_write_reg(index, value);
137 #if TCG_TARGET_REG_BITS == 32
138 static void tci_write_reg64(uint32_t high_index, uint32_t low_index,
141 tci_write_reg(low_index, value);
142 tci_write_reg(high_index, value >> 32);
144 #elif TCG_TARGET_REG_BITS == 64
145 static void tci_write_reg64(TCGReg index, uint64_t value)
147 tci_write_reg(index, value);
151 #if TCG_TARGET_REG_BITS == 32
152 /* Create a 64 bit value from two 32 bit values. */
153 static uint64_t tci_uint64(uint32_t high, uint32_t low)
155 return ((uint64_t)high << 32) + low;
159 /* Read constant (native size) from bytecode. */
160 static tcg_target_ulong tci_read_i(uint8_t **tb_ptr)
162 tcg_target_ulong value = *(tcg_target_ulong *)(*tb_ptr);
163 *tb_ptr += sizeof(value);
167 /* Read unsigned constant (32 bit) from bytecode. */
168 static uint32_t tci_read_i32(uint8_t **tb_ptr)
170 uint32_t value = *(uint32_t *)(*tb_ptr);
171 *tb_ptr += sizeof(value);
175 /* Read signed constant (32 bit) from bytecode. */
176 static int32_t tci_read_s32(uint8_t **tb_ptr)
178 int32_t value = *(int32_t *)(*tb_ptr);
179 *tb_ptr += sizeof(value);
183 #if TCG_TARGET_REG_BITS == 64
184 /* Read constant (64 bit) from bytecode. */
185 static uint64_t tci_read_i64(uint8_t **tb_ptr)
187 uint64_t value = *(uint64_t *)(*tb_ptr);
188 *tb_ptr += sizeof(value);
193 /* Read indexed register (native size) from bytecode. */
194 static tcg_target_ulong tci_read_r(uint8_t **tb_ptr)
196 tcg_target_ulong value = tci_read_reg(**tb_ptr);
201 /* Read indexed register (8 bit) from bytecode. */
202 static uint8_t tci_read_r8(uint8_t **tb_ptr)
204 uint8_t value = tci_read_reg8(**tb_ptr);
209 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
210 /* Read indexed register (8 bit signed) from bytecode. */
211 static int8_t tci_read_r8s(uint8_t **tb_ptr)
213 int8_t value = tci_read_reg8s(**tb_ptr);
219 /* Read indexed register (16 bit) from bytecode. */
220 static uint16_t tci_read_r16(uint8_t **tb_ptr)
222 uint16_t value = tci_read_reg16(**tb_ptr);
227 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
228 /* Read indexed register (16 bit signed) from bytecode. */
229 static int16_t tci_read_r16s(uint8_t **tb_ptr)
231 int16_t value = tci_read_reg16s(**tb_ptr);
237 /* Read indexed register (32 bit) from bytecode. */
238 static uint32_t tci_read_r32(uint8_t **tb_ptr)
240 uint32_t value = tci_read_reg32(**tb_ptr);
245 #if TCG_TARGET_REG_BITS == 32
246 /* Read two indexed registers (2 * 32 bit) from bytecode. */
247 static uint64_t tci_read_r64(uint8_t **tb_ptr)
249 uint32_t low = tci_read_r32(tb_ptr);
250 return tci_uint64(tci_read_r32(tb_ptr), low);
252 #elif TCG_TARGET_REG_BITS == 64
253 /* Read indexed register (32 bit signed) from bytecode. */
254 static int32_t tci_read_r32s(uint8_t **tb_ptr)
256 int32_t value = tci_read_reg32s(**tb_ptr);
261 /* Read indexed register (64 bit) from bytecode. */
262 static uint64_t tci_read_r64(uint8_t **tb_ptr)
264 uint64_t value = tci_read_reg64(**tb_ptr);
270 /* Read indexed register(s) with target address from bytecode. */
271 static target_ulong tci_read_ulong(uint8_t **tb_ptr)
273 target_ulong taddr = tci_read_r(tb_ptr);
274 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
275 taddr += (uint64_t)tci_read_r(tb_ptr) << 32;
280 /* Read indexed register or constant (native size) from bytecode. */
281 static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr)
283 tcg_target_ulong value;
286 if (r == TCG_CONST) {
287 value = tci_read_i(tb_ptr);
289 value = tci_read_reg(r);
294 /* Read indexed register or constant (32 bit) from bytecode. */
295 static uint32_t tci_read_ri32(uint8_t **tb_ptr)
300 if (r == TCG_CONST) {
301 value = tci_read_i32(tb_ptr);
303 value = tci_read_reg32(r);
308 #if TCG_TARGET_REG_BITS == 32
309 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
310 static uint64_t tci_read_ri64(uint8_t **tb_ptr)
312 uint32_t low = tci_read_ri32(tb_ptr);
313 return tci_uint64(tci_read_ri32(tb_ptr), low);
315 #elif TCG_TARGET_REG_BITS == 64
316 /* Read indexed register or constant (64 bit) from bytecode. */
317 static uint64_t tci_read_ri64(uint8_t **tb_ptr)
322 if (r == TCG_CONST) {
323 value = tci_read_i64(tb_ptr);
325 value = tci_read_reg64(r);
331 static tcg_target_ulong tci_read_label(uint8_t **tb_ptr)
333 tcg_target_ulong label = tci_read_i(tb_ptr);
338 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
380 static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
422 #ifdef CONFIG_SOFTMMU
423 # define qemu_ld_ub \
424 helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
425 # define qemu_ld_leuw \
426 helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
427 # define qemu_ld_leul \
428 helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
429 # define qemu_ld_leq \
430 helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
431 # define qemu_ld_beuw \
432 helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
433 # define qemu_ld_beul \
434 helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
435 # define qemu_ld_beq \
436 helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr)
437 # define qemu_st_b(X) \
438 helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
439 # define qemu_st_lew(X) \
440 helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
441 # define qemu_st_lel(X) \
442 helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
443 # define qemu_st_leq(X) \
444 helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
445 # define qemu_st_bew(X) \
446 helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
447 # define qemu_st_bel(X) \
448 helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
449 # define qemu_st_beq(X) \
450 helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr)
452 # define qemu_ld_ub ldub_p(g2h(taddr))
453 # define qemu_ld_leuw lduw_le_p(g2h(taddr))
454 # define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr))
455 # define qemu_ld_leq ldq_le_p(g2h(taddr))
456 # define qemu_ld_beuw lduw_be_p(g2h(taddr))
457 # define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr))
458 # define qemu_ld_beq ldq_be_p(g2h(taddr))
459 # define qemu_st_b(X) stb_p(g2h(taddr), X)
460 # define qemu_st_lew(X) stw_le_p(g2h(taddr), X)
461 # define qemu_st_lel(X) stl_le_p(g2h(taddr), X)
462 # define qemu_st_leq(X) stq_le_p(g2h(taddr), X)
463 # define qemu_st_bew(X) stw_be_p(g2h(taddr), X)
464 # define qemu_st_bel(X) stl_be_p(g2h(taddr), X)
465 # define qemu_st_beq(X) stq_be_p(g2h(taddr), X)
468 /* Interpret pseudo code in tb. */
469 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
471 long tcg_temps[CPU_TEMP_BUF_NLONGS];
472 uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
473 uintptr_t next_tb = 0;
475 tci_reg[TCG_AREG0] = (tcg_target_ulong)env;
476 tci_reg[TCG_REG_CALL_STACK] = sp_value;
480 TCGOpcode opc = tb_ptr[0];
482 uint8_t op_size = tb_ptr[1];
483 uint8_t *old_code_ptr = tb_ptr;
488 tcg_target_ulong label;
495 #if TCG_TARGET_REG_BITS == 32
501 tci_tb_ptr = (uintptr_t)tb_ptr;
504 /* Skip opcode and size entry. */
509 t0 = tci_read_ri(&tb_ptr);
510 #if TCG_TARGET_REG_BITS == 32
511 tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
512 tci_read_reg(TCG_REG_R1),
513 tci_read_reg(TCG_REG_R2),
514 tci_read_reg(TCG_REG_R3),
515 tci_read_reg(TCG_REG_R5),
516 tci_read_reg(TCG_REG_R6),
517 tci_read_reg(TCG_REG_R7),
518 tci_read_reg(TCG_REG_R8),
519 tci_read_reg(TCG_REG_R9),
520 tci_read_reg(TCG_REG_R10));
521 tci_write_reg(TCG_REG_R0, tmp64);
522 tci_write_reg(TCG_REG_R1, tmp64 >> 32);
524 tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
525 tci_read_reg(TCG_REG_R1),
526 tci_read_reg(TCG_REG_R2),
527 tci_read_reg(TCG_REG_R3),
528 tci_read_reg(TCG_REG_R5));
529 tci_write_reg(TCG_REG_R0, tmp64);
533 label = tci_read_label(&tb_ptr);
534 assert(tb_ptr == old_code_ptr + op_size);
535 tb_ptr = (uint8_t *)label;
537 case INDEX_op_setcond_i32:
539 t1 = tci_read_r32(&tb_ptr);
540 t2 = tci_read_ri32(&tb_ptr);
541 condition = *tb_ptr++;
542 tci_write_reg32(t0, tci_compare32(t1, t2, condition));
544 #if TCG_TARGET_REG_BITS == 32
545 case INDEX_op_setcond2_i32:
547 tmp64 = tci_read_r64(&tb_ptr);
548 v64 = tci_read_ri64(&tb_ptr);
549 condition = *tb_ptr++;
550 tci_write_reg32(t0, tci_compare64(tmp64, v64, condition));
552 #elif TCG_TARGET_REG_BITS == 64
553 case INDEX_op_setcond_i64:
555 t1 = tci_read_r64(&tb_ptr);
556 t2 = tci_read_ri64(&tb_ptr);
557 condition = *tb_ptr++;
558 tci_write_reg64(t0, tci_compare64(t1, t2, condition));
561 case INDEX_op_mov_i32:
563 t1 = tci_read_r32(&tb_ptr);
564 tci_write_reg32(t0, t1);
566 case INDEX_op_movi_i32:
568 t1 = tci_read_i32(&tb_ptr);
569 tci_write_reg32(t0, t1);
572 /* Load/store operations (32 bit). */
574 case INDEX_op_ld8u_i32:
576 t1 = tci_read_r(&tb_ptr);
577 t2 = tci_read_s32(&tb_ptr);
578 tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
580 case INDEX_op_ld8s_i32:
581 case INDEX_op_ld16u_i32:
584 case INDEX_op_ld16s_i32:
587 case INDEX_op_ld_i32:
589 t1 = tci_read_r(&tb_ptr);
590 t2 = tci_read_s32(&tb_ptr);
591 tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
593 case INDEX_op_st8_i32:
594 t0 = tci_read_r8(&tb_ptr);
595 t1 = tci_read_r(&tb_ptr);
596 t2 = tci_read_s32(&tb_ptr);
597 *(uint8_t *)(t1 + t2) = t0;
599 case INDEX_op_st16_i32:
600 t0 = tci_read_r16(&tb_ptr);
601 t1 = tci_read_r(&tb_ptr);
602 t2 = tci_read_s32(&tb_ptr);
603 *(uint16_t *)(t1 + t2) = t0;
605 case INDEX_op_st_i32:
606 t0 = tci_read_r32(&tb_ptr);
607 t1 = tci_read_r(&tb_ptr);
608 t2 = tci_read_s32(&tb_ptr);
609 assert(t1 != sp_value || (int32_t)t2 < 0);
610 *(uint32_t *)(t1 + t2) = t0;
613 /* Arithmetic operations (32 bit). */
615 case INDEX_op_add_i32:
617 t1 = tci_read_ri32(&tb_ptr);
618 t2 = tci_read_ri32(&tb_ptr);
619 tci_write_reg32(t0, t1 + t2);
621 case INDEX_op_sub_i32:
623 t1 = tci_read_ri32(&tb_ptr);
624 t2 = tci_read_ri32(&tb_ptr);
625 tci_write_reg32(t0, t1 - t2);
627 case INDEX_op_mul_i32:
629 t1 = tci_read_ri32(&tb_ptr);
630 t2 = tci_read_ri32(&tb_ptr);
631 tci_write_reg32(t0, t1 * t2);
633 #if TCG_TARGET_HAS_div_i32
634 case INDEX_op_div_i32:
636 t1 = tci_read_ri32(&tb_ptr);
637 t2 = tci_read_ri32(&tb_ptr);
638 tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2);
640 case INDEX_op_divu_i32:
642 t1 = tci_read_ri32(&tb_ptr);
643 t2 = tci_read_ri32(&tb_ptr);
644 tci_write_reg32(t0, t1 / t2);
646 case INDEX_op_rem_i32:
648 t1 = tci_read_ri32(&tb_ptr);
649 t2 = tci_read_ri32(&tb_ptr);
650 tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2);
652 case INDEX_op_remu_i32:
654 t1 = tci_read_ri32(&tb_ptr);
655 t2 = tci_read_ri32(&tb_ptr);
656 tci_write_reg32(t0, t1 % t2);
658 #elif TCG_TARGET_HAS_div2_i32
659 case INDEX_op_div2_i32:
660 case INDEX_op_divu2_i32:
664 case INDEX_op_and_i32:
666 t1 = tci_read_ri32(&tb_ptr);
667 t2 = tci_read_ri32(&tb_ptr);
668 tci_write_reg32(t0, t1 & t2);
670 case INDEX_op_or_i32:
672 t1 = tci_read_ri32(&tb_ptr);
673 t2 = tci_read_ri32(&tb_ptr);
674 tci_write_reg32(t0, t1 | t2);
676 case INDEX_op_xor_i32:
678 t1 = tci_read_ri32(&tb_ptr);
679 t2 = tci_read_ri32(&tb_ptr);
680 tci_write_reg32(t0, t1 ^ t2);
683 /* Shift/rotate operations (32 bit). */
685 case INDEX_op_shl_i32:
687 t1 = tci_read_ri32(&tb_ptr);
688 t2 = tci_read_ri32(&tb_ptr);
689 tci_write_reg32(t0, t1 << (t2 & 31));
691 case INDEX_op_shr_i32:
693 t1 = tci_read_ri32(&tb_ptr);
694 t2 = tci_read_ri32(&tb_ptr);
695 tci_write_reg32(t0, t1 >> (t2 & 31));
697 case INDEX_op_sar_i32:
699 t1 = tci_read_ri32(&tb_ptr);
700 t2 = tci_read_ri32(&tb_ptr);
701 tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31)));
703 #if TCG_TARGET_HAS_rot_i32
704 case INDEX_op_rotl_i32:
706 t1 = tci_read_ri32(&tb_ptr);
707 t2 = tci_read_ri32(&tb_ptr);
708 tci_write_reg32(t0, rol32(t1, t2 & 31));
710 case INDEX_op_rotr_i32:
712 t1 = tci_read_ri32(&tb_ptr);
713 t2 = tci_read_ri32(&tb_ptr);
714 tci_write_reg32(t0, ror32(t1, t2 & 31));
717 #if TCG_TARGET_HAS_deposit_i32
718 case INDEX_op_deposit_i32:
720 t1 = tci_read_r32(&tb_ptr);
721 t2 = tci_read_r32(&tb_ptr);
724 tmp32 = (((1 << tmp8) - 1) << tmp16);
725 tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32));
728 case INDEX_op_brcond_i32:
729 t0 = tci_read_r32(&tb_ptr);
730 t1 = tci_read_ri32(&tb_ptr);
731 condition = *tb_ptr++;
732 label = tci_read_label(&tb_ptr);
733 if (tci_compare32(t0, t1, condition)) {
734 assert(tb_ptr == old_code_ptr + op_size);
735 tb_ptr = (uint8_t *)label;
739 #if TCG_TARGET_REG_BITS == 32
740 case INDEX_op_add2_i32:
743 tmp64 = tci_read_r64(&tb_ptr);
744 tmp64 += tci_read_r64(&tb_ptr);
745 tci_write_reg64(t1, t0, tmp64);
747 case INDEX_op_sub2_i32:
750 tmp64 = tci_read_r64(&tb_ptr);
751 tmp64 -= tci_read_r64(&tb_ptr);
752 tci_write_reg64(t1, t0, tmp64);
754 case INDEX_op_brcond2_i32:
755 tmp64 = tci_read_r64(&tb_ptr);
756 v64 = tci_read_ri64(&tb_ptr);
757 condition = *tb_ptr++;
758 label = tci_read_label(&tb_ptr);
759 if (tci_compare64(tmp64, v64, condition)) {
760 assert(tb_ptr == old_code_ptr + op_size);
761 tb_ptr = (uint8_t *)label;
765 case INDEX_op_mulu2_i32:
768 t2 = tci_read_r32(&tb_ptr);
769 tmp64 = tci_read_r32(&tb_ptr);
770 tci_write_reg64(t1, t0, t2 * tmp64);
772 #endif /* TCG_TARGET_REG_BITS == 32 */
773 #if TCG_TARGET_HAS_ext8s_i32
774 case INDEX_op_ext8s_i32:
776 t1 = tci_read_r8s(&tb_ptr);
777 tci_write_reg32(t0, t1);
780 #if TCG_TARGET_HAS_ext16s_i32
781 case INDEX_op_ext16s_i32:
783 t1 = tci_read_r16s(&tb_ptr);
784 tci_write_reg32(t0, t1);
787 #if TCG_TARGET_HAS_ext8u_i32
788 case INDEX_op_ext8u_i32:
790 t1 = tci_read_r8(&tb_ptr);
791 tci_write_reg32(t0, t1);
794 #if TCG_TARGET_HAS_ext16u_i32
795 case INDEX_op_ext16u_i32:
797 t1 = tci_read_r16(&tb_ptr);
798 tci_write_reg32(t0, t1);
801 #if TCG_TARGET_HAS_bswap16_i32
802 case INDEX_op_bswap16_i32:
804 t1 = tci_read_r16(&tb_ptr);
805 tci_write_reg32(t0, bswap16(t1));
808 #if TCG_TARGET_HAS_bswap32_i32
809 case INDEX_op_bswap32_i32:
811 t1 = tci_read_r32(&tb_ptr);
812 tci_write_reg32(t0, bswap32(t1));
815 #if TCG_TARGET_HAS_not_i32
816 case INDEX_op_not_i32:
818 t1 = tci_read_r32(&tb_ptr);
819 tci_write_reg32(t0, ~t1);
822 #if TCG_TARGET_HAS_neg_i32
823 case INDEX_op_neg_i32:
825 t1 = tci_read_r32(&tb_ptr);
826 tci_write_reg32(t0, -t1);
829 #if TCG_TARGET_REG_BITS == 64
830 case INDEX_op_mov_i64:
832 t1 = tci_read_r64(&tb_ptr);
833 tci_write_reg64(t0, t1);
835 case INDEX_op_movi_i64:
837 t1 = tci_read_i64(&tb_ptr);
838 tci_write_reg64(t0, t1);
841 /* Load/store operations (64 bit). */
843 case INDEX_op_ld8u_i64:
845 t1 = tci_read_r(&tb_ptr);
846 t2 = tci_read_s32(&tb_ptr);
847 tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
849 case INDEX_op_ld8s_i64:
850 case INDEX_op_ld16u_i64:
851 case INDEX_op_ld16s_i64:
854 case INDEX_op_ld32u_i64:
856 t1 = tci_read_r(&tb_ptr);
857 t2 = tci_read_s32(&tb_ptr);
858 tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
860 case INDEX_op_ld32s_i64:
862 t1 = tci_read_r(&tb_ptr);
863 t2 = tci_read_s32(&tb_ptr);
864 tci_write_reg32s(t0, *(int32_t *)(t1 + t2));
866 case INDEX_op_ld_i64:
868 t1 = tci_read_r(&tb_ptr);
869 t2 = tci_read_s32(&tb_ptr);
870 tci_write_reg64(t0, *(uint64_t *)(t1 + t2));
872 case INDEX_op_st8_i64:
873 t0 = tci_read_r8(&tb_ptr);
874 t1 = tci_read_r(&tb_ptr);
875 t2 = tci_read_s32(&tb_ptr);
876 *(uint8_t *)(t1 + t2) = t0;
878 case INDEX_op_st16_i64:
879 t0 = tci_read_r16(&tb_ptr);
880 t1 = tci_read_r(&tb_ptr);
881 t2 = tci_read_s32(&tb_ptr);
882 *(uint16_t *)(t1 + t2) = t0;
884 case INDEX_op_st32_i64:
885 t0 = tci_read_r32(&tb_ptr);
886 t1 = tci_read_r(&tb_ptr);
887 t2 = tci_read_s32(&tb_ptr);
888 *(uint32_t *)(t1 + t2) = t0;
890 case INDEX_op_st_i64:
891 t0 = tci_read_r64(&tb_ptr);
892 t1 = tci_read_r(&tb_ptr);
893 t2 = tci_read_s32(&tb_ptr);
894 assert(t1 != sp_value || (int32_t)t2 < 0);
895 *(uint64_t *)(t1 + t2) = t0;
898 /* Arithmetic operations (64 bit). */
900 case INDEX_op_add_i64:
902 t1 = tci_read_ri64(&tb_ptr);
903 t2 = tci_read_ri64(&tb_ptr);
904 tci_write_reg64(t0, t1 + t2);
906 case INDEX_op_sub_i64:
908 t1 = tci_read_ri64(&tb_ptr);
909 t2 = tci_read_ri64(&tb_ptr);
910 tci_write_reg64(t0, t1 - t2);
912 case INDEX_op_mul_i64:
914 t1 = tci_read_ri64(&tb_ptr);
915 t2 = tci_read_ri64(&tb_ptr);
916 tci_write_reg64(t0, t1 * t2);
918 #if TCG_TARGET_HAS_div_i64
919 case INDEX_op_div_i64:
920 case INDEX_op_divu_i64:
921 case INDEX_op_rem_i64:
922 case INDEX_op_remu_i64:
925 #elif TCG_TARGET_HAS_div2_i64
926 case INDEX_op_div2_i64:
927 case INDEX_op_divu2_i64:
931 case INDEX_op_and_i64:
933 t1 = tci_read_ri64(&tb_ptr);
934 t2 = tci_read_ri64(&tb_ptr);
935 tci_write_reg64(t0, t1 & t2);
937 case INDEX_op_or_i64:
939 t1 = tci_read_ri64(&tb_ptr);
940 t2 = tci_read_ri64(&tb_ptr);
941 tci_write_reg64(t0, t1 | t2);
943 case INDEX_op_xor_i64:
945 t1 = tci_read_ri64(&tb_ptr);
946 t2 = tci_read_ri64(&tb_ptr);
947 tci_write_reg64(t0, t1 ^ t2);
950 /* Shift/rotate operations (64 bit). */
952 case INDEX_op_shl_i64:
954 t1 = tci_read_ri64(&tb_ptr);
955 t2 = tci_read_ri64(&tb_ptr);
956 tci_write_reg64(t0, t1 << (t2 & 63));
958 case INDEX_op_shr_i64:
960 t1 = tci_read_ri64(&tb_ptr);
961 t2 = tci_read_ri64(&tb_ptr);
962 tci_write_reg64(t0, t1 >> (t2 & 63));
964 case INDEX_op_sar_i64:
966 t1 = tci_read_ri64(&tb_ptr);
967 t2 = tci_read_ri64(&tb_ptr);
968 tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63)));
970 #if TCG_TARGET_HAS_rot_i64
971 case INDEX_op_rotl_i64:
973 t1 = tci_read_ri64(&tb_ptr);
974 t2 = tci_read_ri64(&tb_ptr);
975 tci_write_reg64(t0, rol64(t1, t2 & 63));
977 case INDEX_op_rotr_i64:
979 t1 = tci_read_ri64(&tb_ptr);
980 t2 = tci_read_ri64(&tb_ptr);
981 tci_write_reg64(t0, ror64(t1, t2 & 63));
984 #if TCG_TARGET_HAS_deposit_i64
985 case INDEX_op_deposit_i64:
987 t1 = tci_read_r64(&tb_ptr);
988 t2 = tci_read_r64(&tb_ptr);
991 tmp64 = (((1ULL << tmp8) - 1) << tmp16);
992 tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
995 case INDEX_op_brcond_i64:
996 t0 = tci_read_r64(&tb_ptr);
997 t1 = tci_read_ri64(&tb_ptr);
998 condition = *tb_ptr++;
999 label = tci_read_label(&tb_ptr);
1000 if (tci_compare64(t0, t1, condition)) {
1001 assert(tb_ptr == old_code_ptr + op_size);
1002 tb_ptr = (uint8_t *)label;
1006 #if TCG_TARGET_HAS_ext8u_i64
1007 case INDEX_op_ext8u_i64:
1009 t1 = tci_read_r8(&tb_ptr);
1010 tci_write_reg64(t0, t1);
1013 #if TCG_TARGET_HAS_ext8s_i64
1014 case INDEX_op_ext8s_i64:
1016 t1 = tci_read_r8s(&tb_ptr);
1017 tci_write_reg64(t0, t1);
1020 #if TCG_TARGET_HAS_ext16s_i64
1021 case INDEX_op_ext16s_i64:
1023 t1 = tci_read_r16s(&tb_ptr);
1024 tci_write_reg64(t0, t1);
1027 #if TCG_TARGET_HAS_ext16u_i64
1028 case INDEX_op_ext16u_i64:
1030 t1 = tci_read_r16(&tb_ptr);
1031 tci_write_reg64(t0, t1);
1034 #if TCG_TARGET_HAS_ext32s_i64
1035 case INDEX_op_ext32s_i64:
1037 t1 = tci_read_r32s(&tb_ptr);
1038 tci_write_reg64(t0, t1);
1041 #if TCG_TARGET_HAS_ext32u_i64
1042 case INDEX_op_ext32u_i64:
1044 t1 = tci_read_r32(&tb_ptr);
1045 tci_write_reg64(t0, t1);
1048 #if TCG_TARGET_HAS_bswap16_i64
1049 case INDEX_op_bswap16_i64:
1052 t1 = tci_read_r16(&tb_ptr);
1053 tci_write_reg64(t0, bswap16(t1));
1056 #if TCG_TARGET_HAS_bswap32_i64
1057 case INDEX_op_bswap32_i64:
1059 t1 = tci_read_r32(&tb_ptr);
1060 tci_write_reg64(t0, bswap32(t1));
1063 #if TCG_TARGET_HAS_bswap64_i64
1064 case INDEX_op_bswap64_i64:
1066 t1 = tci_read_r64(&tb_ptr);
1067 tci_write_reg64(t0, bswap64(t1));
1070 #if TCG_TARGET_HAS_not_i64
1071 case INDEX_op_not_i64:
1073 t1 = tci_read_r64(&tb_ptr);
1074 tci_write_reg64(t0, ~t1);
1077 #if TCG_TARGET_HAS_neg_i64
1078 case INDEX_op_neg_i64:
1080 t1 = tci_read_r64(&tb_ptr);
1081 tci_write_reg64(t0, -t1);
1084 #endif /* TCG_TARGET_REG_BITS == 64 */
1086 /* QEMU specific operations. */
1088 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1089 case INDEX_op_debug_insn_start:
1093 case INDEX_op_debug_insn_start:
1097 case INDEX_op_exit_tb:
1098 next_tb = *(uint64_t *)tb_ptr;
1101 case INDEX_op_goto_tb:
1102 t0 = tci_read_i32(&tb_ptr);
1103 assert(tb_ptr == old_code_ptr + op_size);
1104 tb_ptr += (int32_t)t0;
1106 case INDEX_op_qemu_ld_i32:
1108 taddr = tci_read_ulong(&tb_ptr);
1109 oi = tci_read_i(&tb_ptr);
1110 switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
1115 tmp32 = (int8_t)qemu_ld_ub;
1118 tmp32 = qemu_ld_leuw;
1121 tmp32 = (int16_t)qemu_ld_leuw;
1124 tmp32 = qemu_ld_leul;
1127 tmp32 = qemu_ld_beuw;
1130 tmp32 = (int16_t)qemu_ld_beuw;
1133 tmp32 = qemu_ld_beul;
1138 tci_write_reg(t0, tmp32);
1140 case INDEX_op_qemu_ld_i64:
1142 if (TCG_TARGET_REG_BITS == 32) {
1145 taddr = tci_read_ulong(&tb_ptr);
1146 oi = tci_read_i(&tb_ptr);
1147 switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
1152 tmp64 = (int8_t)qemu_ld_ub;
1155 tmp64 = qemu_ld_leuw;
1158 tmp64 = (int16_t)qemu_ld_leuw;
1161 tmp64 = qemu_ld_leul;
1164 tmp64 = (int32_t)qemu_ld_leul;
1167 tmp64 = qemu_ld_leq;
1170 tmp64 = qemu_ld_beuw;
1173 tmp64 = (int16_t)qemu_ld_beuw;
1176 tmp64 = qemu_ld_beul;
1179 tmp64 = (int32_t)qemu_ld_beul;
1182 tmp64 = qemu_ld_beq;
1187 tci_write_reg(t0, tmp64);
1188 if (TCG_TARGET_REG_BITS == 32) {
1189 tci_write_reg(t1, tmp64 >> 32);
1192 case INDEX_op_qemu_st_i32:
1193 t0 = tci_read_r(&tb_ptr);
1194 taddr = tci_read_ulong(&tb_ptr);
1195 oi = tci_read_i(&tb_ptr);
1196 switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
1216 case INDEX_op_qemu_st_i64:
1217 tmp64 = tci_read_r64(&tb_ptr);
1218 taddr = tci_read_ulong(&tb_ptr);
1219 oi = tci_read_i(&tb_ptr);
1220 switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
1250 assert(tb_ptr == old_code_ptr + op_size);