2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include "exec/exec-all.h"
30 #include "exec/gdbstub.h"
31 #include "qemu/host-utils.h"
32 #if !defined(CONFIG_USER_ONLY)
33 #include "hw/loader.h"
36 static struct XtensaConfigList *xtensa_cores;
38 static void xtensa_core_class_init(ObjectClass *oc, void *data)
40 CPUClass *cc = CPU_CLASS(oc);
41 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
42 const XtensaConfig *config = data;
46 /* Use num_core_regs to see only non-privileged registers in an unmodified
47 * gdb. Use num_regs to see all registers. gdb modification is required
48 * for that: reset bit 0 in the 'flags' field of the registers definitions
49 * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
51 cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
54 void xtensa_finalize_config(XtensaConfig *config)
58 if (config->gdb_regmap.num_regs) {
62 for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) {
63 n += (config->gdb_regmap.reg[i].type != 6);
65 config->gdb_regmap.num_regs = n;
68 void xtensa_register_core(XtensaConfigList *node)
71 .parent = TYPE_XTENSA_CPU,
72 .class_init = xtensa_core_class_init,
73 .class_data = (void *)node->config,
76 node->next = xtensa_cores;
78 type.name = g_strdup_printf("%s-" TYPE_XTENSA_CPU, node->config->name);
80 g_free((gpointer)type.name);
83 static uint32_t check_hw_breakpoints(CPUXtensaState *env)
87 for (i = 0; i < env->config->ndbreak; ++i) {
88 if (env->cpu_watchpoint[i] &&
89 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
90 return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
96 void xtensa_breakpoint_handler(CPUState *cs)
98 XtensaCPU *cpu = XTENSA_CPU(cs);
99 CPUXtensaState *env = &cpu->env;
101 if (cs->watchpoint_hit) {
102 if (cs->watchpoint_hit->flags & BP_CPU) {
105 cs->watchpoint_hit = NULL;
106 cause = check_hw_breakpoints(env);
108 debug_exception_env(env, cause);
110 cpu_resume_from_signal(cs, NULL);
115 XtensaCPU *cpu_xtensa_init(const char *cpu_model)
121 oc = cpu_class_by_name(TYPE_XTENSA_CPU, cpu_model);
126 cpu = XTENSA_CPU(object_new(object_class_get_name(oc)));
129 xtensa_irq_init(env);
131 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
137 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
139 XtensaConfigList *core = xtensa_cores;
140 cpu_fprintf(f, "Available CPUs:\n");
141 for (; core; core = core->next) {
142 cpu_fprintf(f, " %s\n", core->config->name);
146 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
148 XtensaCPU *cpu = XTENSA_CPU(cs);
153 if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0,
154 &paddr, &page_size, &access) == 0) {
157 if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0,
158 &paddr, &page_size, &access) == 0) {
164 static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
166 if (xtensa_option_enabled(env->config,
167 XTENSA_OPTION_RELOCATABLE_VECTOR)) {
168 return vector - env->config->vecbase + env->sregs[VECBASE];
175 * Handle penging IRQ.
176 * For the high priority interrupt jump to the corresponding interrupt vector.
177 * For the level-1 interrupt convert it to either user, kernel or double
178 * exception with the 'level-1 interrupt' exception cause.
180 static void handle_interrupt(CPUXtensaState *env)
182 int level = env->pending_irq_level;
184 if (level > xtensa_get_cintlevel(env) &&
185 level <= env->config->nlevel &&
186 (env->config->level_mask[level] &
188 env->sregs[INTENABLE])) {
189 CPUState *cs = CPU(xtensa_env_get_cpu(env));
192 env->sregs[EPC1 + level - 1] = env->pc;
193 env->sregs[EPS2 + level - 2] = env->sregs[PS];
195 (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
196 env->pc = relocated_vector(env,
197 env->config->interrupt_vector[level]);
199 env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
201 if (env->sregs[PS] & PS_EXCM) {
202 if (env->config->ndepc) {
203 env->sregs[DEPC] = env->pc;
205 env->sregs[EPC1] = env->pc;
207 cs->exception_index = EXC_DOUBLE;
209 env->sregs[EPC1] = env->pc;
210 cs->exception_index =
211 (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
213 env->sregs[PS] |= PS_EXCM;
215 env->exception_taken = 1;
219 void xtensa_cpu_do_interrupt(CPUState *cs)
221 XtensaCPU *cpu = XTENSA_CPU(cs);
222 CPUXtensaState *env = &cpu->env;
224 if (cs->exception_index == EXC_IRQ) {
225 qemu_log_mask(CPU_LOG_INT,
226 "%s(EXC_IRQ) level = %d, cintlevel = %d, "
227 "pc = %08x, a0 = %08x, ps = %08x, "
228 "intset = %08x, intenable = %08x, "
230 __func__, env->pending_irq_level, xtensa_get_cintlevel(env),
231 env->pc, env->regs[0], env->sregs[PS],
232 env->sregs[INTSET], env->sregs[INTENABLE],
234 handle_interrupt(env);
237 switch (cs->exception_index) {
238 case EXC_WINDOW_OVERFLOW4:
239 case EXC_WINDOW_UNDERFLOW4:
240 case EXC_WINDOW_OVERFLOW8:
241 case EXC_WINDOW_UNDERFLOW8:
242 case EXC_WINDOW_OVERFLOW12:
243 case EXC_WINDOW_UNDERFLOW12:
248 qemu_log_mask(CPU_LOG_INT, "%s(%d) "
249 "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
250 __func__, cs->exception_index,
251 env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
252 if (env->config->exception_vector[cs->exception_index]) {
253 env->pc = relocated_vector(env,
254 env->config->exception_vector[cs->exception_index]);
255 env->exception_taken = 1;
257 qemu_log("%s(pc = %08x) bad exception_index: %d\n",
258 __func__, env->pc, cs->exception_index);
266 qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
267 __func__, env->pc, cs->exception_index);
270 check_interrupts(env);
273 bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
275 if (interrupt_request & CPU_INTERRUPT_HARD) {
276 cs->exception_index = EXC_IRQ;
277 xtensa_cpu_do_interrupt(cs);
283 static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
284 const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
288 for (wi = 0; wi < tlb->nways; ++wi) {
289 for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
290 entry[wi][ei].asid = 0;
291 entry[wi][ei].variable = true;
296 static void reset_tlb_mmu_ways56(CPUXtensaState *env,
297 const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
299 if (!tlb->varway56) {
300 static const xtensa_tlb_entry way5[] = {
315 static const xtensa_tlb_entry way6[] = {
330 memcpy(entry[5], way5, sizeof(way5));
331 memcpy(entry[6], way6, sizeof(way6));
334 for (ei = 0; ei < 8; ++ei) {
335 entry[6][ei].vaddr = ei << 29;
336 entry[6][ei].paddr = ei << 29;
337 entry[6][ei].asid = 1;
338 entry[6][ei].attr = 3;
343 static void reset_tlb_region_way0(CPUXtensaState *env,
344 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
348 for (ei = 0; ei < 8; ++ei) {
349 entry[0][ei].vaddr = ei << 29;
350 entry[0][ei].paddr = ei << 29;
351 entry[0][ei].asid = 1;
352 entry[0][ei].attr = 2;
353 entry[0][ei].variable = true;
357 void reset_mmu(CPUXtensaState *env)
359 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
360 env->sregs[RASID] = 0x04030201;
361 env->sregs[ITLBCFG] = 0;
362 env->sregs[DTLBCFG] = 0;
363 env->autorefill_idx = 0;
364 reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
365 reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
366 reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
367 reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
369 reset_tlb_region_way0(env, env->itlb);
370 reset_tlb_region_way0(env, env->dtlb);
374 static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
377 for (i = 0; i < 4; ++i) {
378 if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
386 * Lookup xtensa TLB for the given virtual address.
389 * \param pwi: [out] way index
390 * \param pei: [out] entry index
391 * \param pring: [out] access ring
392 * \return 0 if ok, exception cause code otherwise
394 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
395 uint32_t *pwi, uint32_t *pei, uint8_t *pring)
397 const xtensa_tlb *tlb = dtlb ?
398 &env->config->dtlb : &env->config->itlb;
399 const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
400 env->dtlb : env->itlb;
405 for (wi = 0; wi < tlb->nways; ++wi) {
408 split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
409 if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
410 unsigned ring = get_ring(env, entry[wi][ei].asid);
414 LOAD_STORE_TLB_MULTI_HIT_CAUSE :
415 INST_TLB_MULTI_HIT_CAUSE;
424 (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
428 * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask.
431 static unsigned mmu_attr_to_access(uint32_t attr)
441 access |= PAGE_WRITE;
444 switch (attr & 0xc) {
446 access |= PAGE_CACHE_BYPASS;
450 access |= PAGE_CACHE_WB;
454 access |= PAGE_CACHE_WT;
457 } else if (attr == 13) {
458 access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
464 * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask.
467 static unsigned region_attr_to_access(uint32_t attr)
469 static const unsigned access[16] = {
470 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
471 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
472 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
473 [3] = PAGE_EXEC | PAGE_CACHE_WB,
474 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
475 [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
476 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
479 return access[attr & 0xf];
483 * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask.
484 * See ISA, A.2.14 The Cache Attribute Register
486 static unsigned cacheattr_attr_to_access(uint32_t attr)
488 static const unsigned access[16] = {
489 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
490 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
491 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
492 [3] = PAGE_EXEC | PAGE_CACHE_WB,
493 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
494 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
497 return access[attr & 0xf];
500 static bool is_access_granted(unsigned access, int is_write)
504 return access & PAGE_READ;
507 return access & PAGE_WRITE;
510 return access & PAGE_EXEC;
517 static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
519 static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
520 uint32_t vaddr, int is_write, int mmu_idx,
521 uint32_t *paddr, uint32_t *page_size, unsigned *access,
524 bool dtlb = is_write != 2;
530 const xtensa_tlb_entry *entry = NULL;
531 xtensa_tlb_entry tmp_entry;
532 int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
534 if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
535 may_lookup_pt && get_pte(env, vaddr, &pte) == 0) {
536 ring = (pte >> 4) & 0x3;
538 split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
541 wi = ++env->autorefill_idx & 0x3;
542 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
543 env->sregs[EXCVADDR] = vaddr;
544 qemu_log("%s: autorefill(%08x): %08x -> %08x\n",
545 __func__, vaddr, vpn, pte);
547 xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
557 entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
560 if (ring < mmu_idx) {
562 LOAD_STORE_PRIVILEGE_CAUSE :
563 INST_FETCH_PRIVILEGE_CAUSE;
566 *access = mmu_attr_to_access(entry->attr) &
567 ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
568 if (!is_access_granted(*access, is_write)) {
571 STORE_PROHIBITED_CAUSE :
572 LOAD_PROHIBITED_CAUSE) :
573 INST_FETCH_PROHIBITED_CAUSE;
576 *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
577 *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
582 static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
584 CPUState *cs = CPU(xtensa_env_get_cpu(env));
589 (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
590 int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
591 &paddr, &page_size, &access, false);
593 qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__,
594 vaddr, ret ? ~0 : paddr);
597 *pte = ldl_phys(cs->as, paddr);
602 static int get_physical_addr_region(CPUXtensaState *env,
603 uint32_t vaddr, int is_write, int mmu_idx,
604 uint32_t *paddr, uint32_t *page_size, unsigned *access)
606 bool dtlb = is_write != 2;
608 uint32_t ei = (vaddr >> 29) & 0x7;
609 const xtensa_tlb_entry *entry =
610 xtensa_tlb_get_entry(env, dtlb, wi, ei);
612 *access = region_attr_to_access(entry->attr);
613 if (!is_access_granted(*access, is_write)) {
616 STORE_PROHIBITED_CAUSE :
617 LOAD_PROHIBITED_CAUSE) :
618 INST_FETCH_PROHIBITED_CAUSE;
621 *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
622 *page_size = ~REGION_PAGE_MASK + 1;
628 * Convert virtual address to physical addr.
629 * MMU may issue pagewalk and change xtensa autorefill TLB way entry.
631 * \return 0 if ok, exception cause code otherwise
633 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
634 uint32_t vaddr, int is_write, int mmu_idx,
635 uint32_t *paddr, uint32_t *page_size, unsigned *access)
637 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
638 return get_physical_addr_mmu(env, update_tlb,
639 vaddr, is_write, mmu_idx, paddr, page_size, access, true);
640 } else if (xtensa_option_bits_enabled(env->config,
641 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
642 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
643 return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
644 paddr, page_size, access);
647 *page_size = TARGET_PAGE_SIZE;
648 *access = cacheattr_attr_to_access(
649 env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27));
654 static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
655 CPUXtensaState *env, bool dtlb)
658 const xtensa_tlb *conf =
659 dtlb ? &env->config->dtlb : &env->config->itlb;
660 unsigned (*attr_to_access)(uint32_t) =
661 xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
662 mmu_attr_to_access : region_attr_to_access;
664 for (wi = 0; wi < conf->nways; ++wi) {
665 uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
667 bool print_header = true;
669 if (sz >= 0x100000) {
677 for (ei = 0; ei < conf->way_size[wi]; ++ei) {
678 const xtensa_tlb_entry *entry =
679 xtensa_tlb_get_entry(env, dtlb, wi, ei);
682 static const char * const cache_text[8] = {
683 [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
684 [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
685 [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
686 [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
688 unsigned access = attr_to_access(entry->attr);
689 unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
693 print_header = false;
694 cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
696 "\tVaddr Paddr ASID Attr RWX Cache\n"
697 "\t---------- ---------- ---- ---- --- -------\n");
700 "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n",
705 (access & PAGE_READ) ? 'R' : '-',
706 (access & PAGE_WRITE) ? 'W' : '-',
707 (access & PAGE_EXEC) ? 'X' : '-',
708 cache_text[cache_idx] ? cache_text[cache_idx] :
715 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
717 if (xtensa_option_bits_enabled(env->config,
718 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
719 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
720 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
722 cpu_fprintf(f, "ITLB:\n");
723 dump_tlb(f, cpu_fprintf, env, false);
724 cpu_fprintf(f, "\nDTLB:\n");
725 dump_tlb(f, cpu_fprintf, env, true);
727 cpu_fprintf(f, "No TLB for this CPU core\n");