2 * UniCore-F64 simulation helpers for QEMU.
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or any later version.
9 * See the COPYING file in the top-level directory.
11 #include "qemu/osdep.h"
13 #include "exec/helper-proto.h"
16 * The convention used for UniCore-F64 instructions:
17 * Single precition routines have a "s" suffix
18 * Double precision routines have a "d" suffix.
21 /* Convert host exception flags to f64 form. */
22 static inline int ucf64_exceptbits_from_host(int host_bits)
26 if (host_bits & float_flag_invalid) {
27 target_bits |= UCF64_FPSCR_FLAG_INVALID;
29 if (host_bits & float_flag_divbyzero) {
30 target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
32 if (host_bits & float_flag_overflow) {
33 target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
35 if (host_bits & float_flag_underflow) {
36 target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
38 if (host_bits & float_flag_inexact) {
39 target_bits |= UCF64_FPSCR_FLAG_INEXACT;
44 uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
49 fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
50 i = get_float_exception_flags(&env->ucf64.fp_status);
51 fpscr |= ucf64_exceptbits_from_host(i);
55 /* Convert ucf64 exception flags to target form. */
56 static inline int ucf64_exceptbits_to_host(int target_bits)
60 if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
61 host_bits |= float_flag_invalid;
63 if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
64 host_bits |= float_flag_divbyzero;
66 if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
67 host_bits |= float_flag_overflow;
69 if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
70 host_bits |= float_flag_underflow;
72 if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
73 host_bits |= float_flag_inexact;
78 void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
80 UniCore32CPU *cpu = uc32_env_get_cpu(env);
84 changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
85 env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
88 if (changed & (UCF64_FPSCR_RND_MASK)) {
89 i = UCF64_FPSCR_RND(val);
92 i = float_round_nearest_even;
95 i = float_round_to_zero;
101 i = float_round_down;
103 default: /* 100 and 101 not implement */
104 cpu_abort(CPU(cpu), "Unsupported UniCore-F64 round mode");
106 set_float_rounding_mode(i, &env->ucf64.fp_status);
109 i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
110 set_float_exception_flags(i, &env->ucf64.fp_status);
113 float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
115 return float32_add(a, b, &env->ucf64.fp_status);
118 float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
120 return float64_add(a, b, &env->ucf64.fp_status);
123 float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
125 return float32_sub(a, b, &env->ucf64.fp_status);
128 float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
130 return float64_sub(a, b, &env->ucf64.fp_status);
133 float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
135 return float32_mul(a, b, &env->ucf64.fp_status);
138 float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
140 return float64_mul(a, b, &env->ucf64.fp_status);
143 float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
145 return float32_div(a, b, &env->ucf64.fp_status);
148 float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env)
150 return float64_div(a, b, &env->ucf64.fp_status);
153 float32 HELPER(ucf64_negs)(float32 a)
155 return float32_chs(a);
158 float64 HELPER(ucf64_negd)(float64 a)
160 return float64_chs(a);
163 float32 HELPER(ucf64_abss)(float32 a)
165 return float32_abs(a);
168 float64 HELPER(ucf64_absd)(float64 a)
170 return float64_abs(a);
173 void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c,
174 CPUUniCore32State *env)
177 flag = float32_compare_quiet(a, b, &env->ucf64.fp_status);
193 if ((flag == 0) || (flag == 2)) {
203 if ((flag == -1) || (flag == 2)) {
208 if ((flag == -1) || (flag == 0)) {
218 env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
219 | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
222 void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c,
223 CPUUniCore32State *env)
226 flag = float64_compare_quiet(a, b, &env->ucf64.fp_status);
242 if ((flag == 0) || (flag == 2)) {
252 if ((flag == -1) || (flag == 2)) {
257 if ((flag == -1) || (flag == 0)) {
267 env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
268 | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
271 /* Helper routines to perform bitwise copies between float and int. */
272 static inline float32 ucf64_itos(uint32_t i)
283 static inline uint32_t ucf64_stoi(float32 s)
294 /* Integer to float conversion. */
295 float32 HELPER(ucf64_si2sf)(float32 x, CPUUniCore32State *env)
297 return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
300 float64 HELPER(ucf64_si2df)(float32 x, CPUUniCore32State *env)
302 return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
305 /* Float to integer conversion. */
306 float32 HELPER(ucf64_sf2si)(float32 x, CPUUniCore32State *env)
308 return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
311 float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env)
313 return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
316 /* floating point conversion */
317 float64 HELPER(ucf64_sf2df)(float32 x, CPUUniCore32State *env)
319 return float32_to_float64(x, &env->ucf64.fp_status);
322 float32 HELPER(ucf64_df2sf)(float64 x, CPUUniCore32State *env)
324 return float64_to_float32(x, &env->ucf64.fp_status);