2 * UniCore32 translation
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or (at your option) any
9 * later version. See the COPYING file in the top-level directory.
11 #include "qemu/osdep.h"
14 #include "disas/disas.h"
17 #include "exec/cpu_ldst.h"
19 #include "exec/helper-proto.h"
20 #include "exec/helper-gen.h"
22 #include "trace-tcg.h"
26 /* internal defines */
27 typedef struct DisasContext {
30 /* Nonzero if this instruction has been conditionally skipped. */
32 /* The label that will be jumped to when the instruction is skipped. */
34 struct TranslationBlock *tb;
35 int singlestep_enabled;
36 #ifndef CONFIG_USER_ONLY
41 #ifndef CONFIG_USER_ONLY
42 #define IS_USER(s) (s->user)
47 /* These instructions trap after executing, so defer them until after the
48 conditional executions state has been updated. */
49 #define DISAS_SYSCALL 5
51 static TCGv_env cpu_env;
52 static TCGv_i32 cpu_R[32];
54 /* FIXME: These should be removed. */
55 static TCGv cpu_F0s, cpu_F1s;
56 static TCGv_i64 cpu_F0d, cpu_F1d;
58 #include "exec/gen-icount.h"
60 static const char *regnames[] = {
61 "r00", "r01", "r02", "r03", "r04", "r05", "r06", "r07",
62 "r08", "r09", "r10", "r11", "r12", "r13", "r14", "r15",
63 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
64 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "pc" };
66 /* initialize TCG globals. */
67 void uc32_translate_init(void)
71 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
73 for (i = 0; i < 32; i++) {
74 cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
75 offsetof(CPUUniCore32State, regs[i]), regnames[i]);
81 /* Allocate a temporary variable. */
82 static TCGv_i32 new_tmp(void)
85 return tcg_temp_new_i32();
88 /* Release a temporary variable. */
89 static void dead_tmp(TCGv tmp)
95 static inline TCGv load_cpu_offset(int offset)
98 tcg_gen_ld_i32(tmp, cpu_env, offset);
102 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUUniCore32State, name))
104 static inline void store_cpu_offset(TCGv var, int offset)
106 tcg_gen_st_i32(var, cpu_env, offset);
110 #define store_cpu_field(var, name) \
111 store_cpu_offset(var, offsetof(CPUUniCore32State, name))
113 /* Set a variable to the value of a CPU register. */
114 static void load_reg_var(DisasContext *s, TCGv var, int reg)
118 /* normaly, since we updated PC */
120 tcg_gen_movi_i32(var, addr);
122 tcg_gen_mov_i32(var, cpu_R[reg]);
126 /* Create a new temporary and set it to the value of a CPU register. */
127 static inline TCGv load_reg(DisasContext *s, int reg)
129 TCGv tmp = new_tmp();
130 load_reg_var(s, tmp, reg);
134 /* Set a CPU register. The source must be a temporary and will be
136 static void store_reg(DisasContext *s, int reg, TCGv var)
139 tcg_gen_andi_i32(var, var, ~3);
140 s->is_jmp = DISAS_JUMP;
142 tcg_gen_mov_i32(cpu_R[reg], var);
146 /* Value extensions. */
147 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
148 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
149 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
150 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
152 #define UCOP_REG_M (((insn) >> 0) & 0x1f)
153 #define UCOP_REG_N (((insn) >> 19) & 0x1f)
154 #define UCOP_REG_D (((insn) >> 14) & 0x1f)
155 #define UCOP_REG_S (((insn) >> 9) & 0x1f)
156 #define UCOP_REG_LO (((insn) >> 14) & 0x1f)
157 #define UCOP_REG_HI (((insn) >> 9) & 0x1f)
158 #define UCOP_SH_OP (((insn) >> 6) & 0x03)
159 #define UCOP_SH_IM (((insn) >> 9) & 0x1f)
160 #define UCOP_OPCODES (((insn) >> 25) & 0x0f)
161 #define UCOP_IMM_9 (((insn) >> 0) & 0x1ff)
162 #define UCOP_IMM10 (((insn) >> 0) & 0x3ff)
163 #define UCOP_IMM14 (((insn) >> 0) & 0x3fff)
164 #define UCOP_COND (((insn) >> 25) & 0x0f)
165 #define UCOP_CMOV_COND (((insn) >> 19) & 0x0f)
166 #define UCOP_CPNUM (((insn) >> 10) & 0x0f)
167 #define UCOP_UCF64_FMT (((insn) >> 24) & 0x03)
168 #define UCOP_UCF64_FUNC (((insn) >> 6) & 0x0f)
169 #define UCOP_UCF64_COND (((insn) >> 6) & 0x0f)
171 #define UCOP_SET(i) ((insn) & (1 << (i)))
172 #define UCOP_SET_P UCOP_SET(28)
173 #define UCOP_SET_U UCOP_SET(27)
174 #define UCOP_SET_B UCOP_SET(26)
175 #define UCOP_SET_W UCOP_SET(25)
176 #define UCOP_SET_L UCOP_SET(24)
177 #define UCOP_SET_S UCOP_SET(24)
179 #define ILLEGAL cpu_abort(CPU(cpu), \
180 "Illegal UniCore32 instruction %x at line %d!", \
183 #ifndef CONFIG_USER_ONLY
184 static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
187 UniCore32CPU *cpu = uc32_env_get_cpu(env);
188 TCGv tmp, tmp2, tmp3;
189 if ((insn & 0xfe000000) == 0xe0000000) {
192 tcg_gen_movi_i32(tmp2, UCOP_REG_N);
193 tcg_gen_movi_i32(tmp3, UCOP_IMM10);
196 gen_helper_cp0_get(tmp, cpu_env, tmp2, tmp3);
197 store_reg(s, UCOP_REG_D, tmp);
199 tmp = load_reg(s, UCOP_REG_D);
200 gen_helper_cp0_set(cpu_env, tmp, tmp2, tmp3);
210 static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s,
213 UniCore32CPU *cpu = uc32_env_get_cpu(env);
216 if ((insn & 0xff003fff) == 0xe1000400) {
218 * movc rd, pp.nn, #imm9
220 * nn: UCOP_REG_N (must be 0)
223 if (UCOP_REG_N == 0) {
225 tcg_gen_movi_i32(tmp, 0);
226 store_reg(s, UCOP_REG_D, tmp);
232 if ((insn & 0xff003fff) == 0xe0000401) {
234 * movc pp.nn, rn, #imm9
236 * nn: UCOP_REG_N (must be 1)
239 if (UCOP_REG_N == 1) {
240 tmp = load_reg(s, UCOP_REG_D);
241 gen_helper_cp1_putc(tmp);
252 static inline void gen_set_asr(TCGv var, uint32_t mask)
254 TCGv tmp_mask = tcg_const_i32(mask);
255 gen_helper_asr_write(cpu_env, var, tmp_mask);
256 tcg_temp_free_i32(tmp_mask);
258 /* Set NZCV flags from the high 4 bits of var. */
259 #define gen_set_nzcv(var) gen_set_asr(var, ASR_NZCV)
261 static void gen_exception(int excp)
263 TCGv tmp = new_tmp();
264 tcg_gen_movi_i32(tmp, excp);
265 gen_helper_exception(cpu_env, tmp);
269 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, CF))
271 /* Set CF to the top bit of var. */
272 static void gen_set_CF_bit31(TCGv var)
274 TCGv tmp = new_tmp();
275 tcg_gen_shri_i32(tmp, var, 31);
280 /* Set N and Z flags from var. */
281 static inline void gen_logic_CC(TCGv var)
283 tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, NF));
284 tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, ZF));
287 /* dest = T0 + T1 + CF. */
288 static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
291 tcg_gen_add_i32(dest, t0, t1);
292 tmp = load_cpu_field(CF);
293 tcg_gen_add_i32(dest, dest, tmp);
297 /* dest = T0 - T1 + CF - 1. */
298 static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
301 tcg_gen_sub_i32(dest, t0, t1);
302 tmp = load_cpu_field(CF);
303 tcg_gen_add_i32(dest, dest, tmp);
304 tcg_gen_subi_i32(dest, dest, 1);
308 static void shifter_out_im(TCGv var, int shift)
310 TCGv tmp = new_tmp();
312 tcg_gen_andi_i32(tmp, var, 1);
314 tcg_gen_shri_i32(tmp, var, shift);
316 tcg_gen_andi_i32(tmp, tmp, 1);
323 /* Shift by immediate. Includes special handling for shift == 0. */
324 static inline void gen_uc32_shift_im(TCGv var, int shiftop, int shift,
331 shifter_out_im(var, 32 - shift);
333 tcg_gen_shli_i32(var, var, shift);
339 tcg_gen_shri_i32(var, var, 31);
342 tcg_gen_movi_i32(var, 0);
345 shifter_out_im(var, shift - 1);
347 tcg_gen_shri_i32(var, var, shift);
355 shifter_out_im(var, shift - 1);
360 tcg_gen_sari_i32(var, var, shift);
362 case 3: /* ROR/RRX */
365 shifter_out_im(var, shift - 1);
367 tcg_gen_rotri_i32(var, var, shift); break;
369 TCGv tmp = load_cpu_field(CF);
371 shifter_out_im(var, 0);
373 tcg_gen_shri_i32(var, var, 1);
374 tcg_gen_shli_i32(tmp, tmp, 31);
375 tcg_gen_or_i32(var, var, tmp);
381 static inline void gen_uc32_shift_reg(TCGv var, int shiftop,
382 TCGv shift, int flags)
387 gen_helper_shl_cc(var, cpu_env, var, shift);
390 gen_helper_shr_cc(var, cpu_env, var, shift);
393 gen_helper_sar_cc(var, cpu_env, var, shift);
396 gen_helper_ror_cc(var, cpu_env, var, shift);
402 gen_helper_shl(var, var, shift);
405 gen_helper_shr(var, var, shift);
408 gen_helper_sar(var, var, shift);
411 tcg_gen_andi_i32(shift, shift, 0x1f);
412 tcg_gen_rotr_i32(var, var, shift);
419 static void gen_test_cc(int cc, TCGLabel *label)
427 tmp = load_cpu_field(ZF);
428 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
431 tmp = load_cpu_field(ZF);
432 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
435 tmp = load_cpu_field(CF);
436 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
439 tmp = load_cpu_field(CF);
440 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
443 tmp = load_cpu_field(NF);
444 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
447 tmp = load_cpu_field(NF);
448 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
451 tmp = load_cpu_field(VF);
452 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
455 tmp = load_cpu_field(VF);
456 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
458 case 8: /* hi: C && !Z */
459 inv = gen_new_label();
460 tmp = load_cpu_field(CF);
461 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
463 tmp = load_cpu_field(ZF);
464 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
467 case 9: /* ls: !C || Z */
468 tmp = load_cpu_field(CF);
469 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
471 tmp = load_cpu_field(ZF);
472 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
474 case 10: /* ge: N == V -> N ^ V == 0 */
475 tmp = load_cpu_field(VF);
476 tmp2 = load_cpu_field(NF);
477 tcg_gen_xor_i32(tmp, tmp, tmp2);
479 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
481 case 11: /* lt: N != V -> N ^ V != 0 */
482 tmp = load_cpu_field(VF);
483 tmp2 = load_cpu_field(NF);
484 tcg_gen_xor_i32(tmp, tmp, tmp2);
486 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
488 case 12: /* gt: !Z && N == V */
489 inv = gen_new_label();
490 tmp = load_cpu_field(ZF);
491 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
493 tmp = load_cpu_field(VF);
494 tmp2 = load_cpu_field(NF);
495 tcg_gen_xor_i32(tmp, tmp, tmp2);
497 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
500 case 13: /* le: Z || N != V */
501 tmp = load_cpu_field(ZF);
502 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
504 tmp = load_cpu_field(VF);
505 tmp2 = load_cpu_field(NF);
506 tcg_gen_xor_i32(tmp, tmp, tmp2);
508 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
511 fprintf(stderr, "Bad condition code 0x%x\n", cc);
517 static const uint8_t table_logic_cc[16] = {
518 1, /* and */ 1, /* xor */ 0, /* sub */ 0, /* rsb */
519 0, /* add */ 0, /* adc */ 0, /* sbc */ 0, /* rsc */
520 1, /* andl */ 1, /* xorl */ 0, /* cmp */ 0, /* cmn */
521 1, /* orr */ 1, /* mov */ 1, /* bic */ 1, /* mvn */
524 /* Set PC state from an immediate address. */
525 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
527 s->is_jmp = DISAS_UPDATE;
528 tcg_gen_movi_i32(cpu_R[31], addr & ~3);
531 /* Set PC state from var. var is marked as dead. */
532 static inline void gen_bx(DisasContext *s, TCGv var)
534 s->is_jmp = DISAS_UPDATE;
535 tcg_gen_andi_i32(cpu_R[31], var, ~3);
539 static inline void store_reg_bx(DisasContext *s, int reg, TCGv var)
541 store_reg(s, reg, var);
544 static inline TCGv gen_ld8s(TCGv addr, int index)
546 TCGv tmp = new_tmp();
547 tcg_gen_qemu_ld8s(tmp, addr, index);
551 static inline TCGv gen_ld8u(TCGv addr, int index)
553 TCGv tmp = new_tmp();
554 tcg_gen_qemu_ld8u(tmp, addr, index);
558 static inline TCGv gen_ld16s(TCGv addr, int index)
560 TCGv tmp = new_tmp();
561 tcg_gen_qemu_ld16s(tmp, addr, index);
565 static inline TCGv gen_ld16u(TCGv addr, int index)
567 TCGv tmp = new_tmp();
568 tcg_gen_qemu_ld16u(tmp, addr, index);
572 static inline TCGv gen_ld32(TCGv addr, int index)
574 TCGv tmp = new_tmp();
575 tcg_gen_qemu_ld32u(tmp, addr, index);
579 static inline void gen_st8(TCGv val, TCGv addr, int index)
581 tcg_gen_qemu_st8(val, addr, index);
585 static inline void gen_st16(TCGv val, TCGv addr, int index)
587 tcg_gen_qemu_st16(val, addr, index);
591 static inline void gen_st32(TCGv val, TCGv addr, int index)
593 tcg_gen_qemu_st32(val, addr, index);
597 static inline void gen_set_pc_im(uint32_t val)
599 tcg_gen_movi_i32(cpu_R[31], val);
602 /* Force a TB lookup after an instruction that changes the CPU state. */
603 static inline void gen_lookup_tb(DisasContext *s)
605 tcg_gen_movi_i32(cpu_R[31], s->pc & ~1);
606 s->is_jmp = DISAS_UPDATE;
609 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
622 tcg_gen_addi_i32(var, var, val);
626 offset = load_reg(s, UCOP_REG_M);
627 gen_uc32_shift_im(offset, UCOP_SH_OP, UCOP_SH_IM, 0);
629 tcg_gen_sub_i32(var, var, offset);
631 tcg_gen_add_i32(var, var, offset);
637 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
645 val = (insn & 0x1f) | ((insn >> 4) & 0x3e0);
650 tcg_gen_addi_i32(var, var, val);
654 offset = load_reg(s, UCOP_REG_M);
656 tcg_gen_sub_i32(var, var, offset);
658 tcg_gen_add_i32(var, var, offset);
664 static inline long ucf64_reg_offset(int reg)
667 return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1])
668 + offsetof(CPU_DoubleU, l.upper);
670 return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1])
671 + offsetof(CPU_DoubleU, l.lower);
675 #define ucf64_gen_ld32(reg) load_cpu_offset(ucf64_reg_offset(reg))
676 #define ucf64_gen_st32(var, reg) store_cpu_offset(var, ucf64_reg_offset(reg))
678 /* UniCore-F64 single load/store I_offset */
679 static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
681 UniCore32CPU *cpu = uc32_env_get_cpu(env);
686 addr = load_reg(s, UCOP_REG_N);
687 if (!UCOP_SET_P && !UCOP_SET_W) {
692 offset = UCOP_IMM10 << 2;
697 tcg_gen_addi_i32(addr, addr, offset);
701 if (UCOP_SET_L) { /* load */
702 tmp = gen_ld32(addr, IS_USER(s));
703 ucf64_gen_st32(tmp, UCOP_REG_D);
705 tmp = ucf64_gen_ld32(UCOP_REG_D);
706 gen_st32(tmp, addr, IS_USER(s));
710 offset = UCOP_IMM10 << 2;
715 tcg_gen_addi_i32(addr, addr, offset);
719 store_reg(s, UCOP_REG_N, addr);
725 /* UniCore-F64 load/store multiple words */
726 static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
728 UniCore32CPU *cpu = uc32_env_get_cpu(env);
734 if (UCOP_REG_D != 0) {
737 if (UCOP_REG_N == 31) {
740 if ((insn << 24) == 0) {
744 addr = load_reg(s, UCOP_REG_N);
747 for (i = 0; i < 8; i++) {
754 if (UCOP_SET_P) { /* pre increment */
755 tcg_gen_addi_i32(addr, addr, 4);
756 } /* unnecessary to do anything when post increment */
758 if (UCOP_SET_P) { /* pre decrement */
759 tcg_gen_addi_i32(addr, addr, -(n * 4));
760 } else { /* post decrement */
762 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
767 freg = ((insn >> 8) & 3) << 3; /* freg should be 0, 8, 16, 24 */
769 for (i = 0, j = 0; i < 8; i++, freg++) {
774 if (UCOP_SET_L) { /* load */
775 tmp = gen_ld32(addr, IS_USER(s));
776 ucf64_gen_st32(tmp, freg);
778 tmp = ucf64_gen_ld32(freg);
779 gen_st32(tmp, addr, IS_USER(s));
783 /* unnecessary to add after the last transfer */
785 tcg_gen_addi_i32(addr, addr, 4);
789 if (UCOP_SET_W) { /* write back */
791 if (!UCOP_SET_P) { /* post increment */
792 tcg_gen_addi_i32(addr, addr, 4);
793 } /* unnecessary to do anything when pre increment */
798 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
802 tcg_gen_addi_i32(addr, addr, -(n * 4));
805 store_reg(s, UCOP_REG_N, addr);
811 /* UniCore-F64 mrc/mcr */
812 static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
814 UniCore32CPU *cpu = uc32_env_get_cpu(env);
817 if ((insn & 0xfe0003ff) == 0xe2000000) {
818 /* control register */
819 if ((UCOP_REG_N != UC32_UCF64_FPSCR) || (UCOP_REG_D == 31)) {
825 gen_helper_ucf64_get_fpscr(tmp, cpu_env);
826 store_reg(s, UCOP_REG_D, tmp);
829 tmp = load_reg(s, UCOP_REG_D);
830 gen_helper_ucf64_set_fpscr(cpu_env, tmp);
836 if ((insn & 0xfe0003ff) == 0xe0000000) {
837 /* general register */
838 if (UCOP_REG_D == 31) {
841 if (UCOP_SET(24)) { /* MFF */
842 tmp = ucf64_gen_ld32(UCOP_REG_N);
843 store_reg(s, UCOP_REG_D, tmp);
845 tmp = load_reg(s, UCOP_REG_D);
846 ucf64_gen_st32(tmp, UCOP_REG_N);
850 if ((insn & 0xfb000000) == 0xe9000000) {
852 if (UCOP_REG_D != 31) {
855 if (UCOP_UCF64_COND & 0x8) {
860 tcg_gen_movi_i32(tmp, UCOP_UCF64_COND);
862 tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_N));
863 tcg_gen_ld_i64(cpu_F1d, cpu_env, ucf64_reg_offset(UCOP_REG_M));
864 gen_helper_ucf64_cmpd(cpu_F0d, cpu_F1d, tmp, cpu_env);
866 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_N));
867 tcg_gen_ld_i32(cpu_F1s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
868 gen_helper_ucf64_cmps(cpu_F0s, cpu_F1s, tmp, cpu_env);
876 /* UniCore-F64 convert instructions */
877 static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
879 UniCore32CPU *cpu = uc32_env_get_cpu(env);
881 if (UCOP_UCF64_FMT == 3) {
884 if (UCOP_REG_N != 0) {
887 switch (UCOP_UCF64_FUNC) {
889 switch (UCOP_UCF64_FMT) {
891 tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_M));
892 gen_helper_ucf64_df2sf(cpu_F0s, cpu_F0d, cpu_env);
893 tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));
896 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
897 gen_helper_ucf64_si2sf(cpu_F0s, cpu_F0s, cpu_env);
898 tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));
906 switch (UCOP_UCF64_FMT) {
908 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
909 gen_helper_ucf64_sf2df(cpu_F0d, cpu_F0s, cpu_env);
910 tcg_gen_st_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_D));
913 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
914 gen_helper_ucf64_si2df(cpu_F0d, cpu_F0s, cpu_env);
915 tcg_gen_st_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_D));
923 switch (UCOP_UCF64_FMT) {
925 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
926 gen_helper_ucf64_sf2si(cpu_F0s, cpu_F0s, cpu_env);
927 tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));
930 tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_M));
931 gen_helper_ucf64_df2si(cpu_F0s, cpu_F0d, cpu_env);
932 tcg_gen_st_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_D));
944 /* UniCore-F64 compare instructions */
945 static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
947 UniCore32CPU *cpu = uc32_env_get_cpu(env);
952 if (UCOP_REG_D != 0) {
958 tcg_gen_ld_i64(cpu_F0d, cpu_env, ucf64_reg_offset(UCOP_REG_N));
959 tcg_gen_ld_i64(cpu_F1d, cpu_env, ucf64_reg_offset(UCOP_REG_M));
960 /* gen_helper_ucf64_cmpd(cpu_F0d, cpu_F1d, cpu_env); */
962 tcg_gen_ld_i32(cpu_F0s, cpu_env, ucf64_reg_offset(UCOP_REG_N));
963 tcg_gen_ld_i32(cpu_F1s, cpu_env, ucf64_reg_offset(UCOP_REG_M));
964 /* gen_helper_ucf64_cmps(cpu_F0s, cpu_F1s, cpu_env); */
968 #define gen_helper_ucf64_movs(x, y) do { } while (0)
969 #define gen_helper_ucf64_movd(x, y) do { } while (0)
971 #define UCF64_OP1(name) do { \
972 if (UCOP_REG_N != 0) { \
975 switch (UCOP_UCF64_FMT) { \
977 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
978 ucf64_reg_offset(UCOP_REG_M)); \
979 gen_helper_ucf64_##name##s(cpu_F0s, cpu_F0s); \
980 tcg_gen_st_i32(cpu_F0s, cpu_env, \
981 ucf64_reg_offset(UCOP_REG_D)); \
984 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
985 ucf64_reg_offset(UCOP_REG_M)); \
986 gen_helper_ucf64_##name##d(cpu_F0d, cpu_F0d); \
987 tcg_gen_st_i64(cpu_F0d, cpu_env, \
988 ucf64_reg_offset(UCOP_REG_D)); \
996 #define UCF64_OP2(name) do { \
997 switch (UCOP_UCF64_FMT) { \
999 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
1000 ucf64_reg_offset(UCOP_REG_N)); \
1001 tcg_gen_ld_i32(cpu_F1s, cpu_env, \
1002 ucf64_reg_offset(UCOP_REG_M)); \
1003 gen_helper_ucf64_##name##s(cpu_F0s, \
1004 cpu_F0s, cpu_F1s, cpu_env); \
1005 tcg_gen_st_i32(cpu_F0s, cpu_env, \
1006 ucf64_reg_offset(UCOP_REG_D)); \
1009 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
1010 ucf64_reg_offset(UCOP_REG_N)); \
1011 tcg_gen_ld_i64(cpu_F1d, cpu_env, \
1012 ucf64_reg_offset(UCOP_REG_M)); \
1013 gen_helper_ucf64_##name##d(cpu_F0d, \
1014 cpu_F0d, cpu_F1d, cpu_env); \
1015 tcg_gen_st_i64(cpu_F0d, cpu_env, \
1016 ucf64_reg_offset(UCOP_REG_D)); \
1024 /* UniCore-F64 data processing */
1025 static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1027 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1029 if (UCOP_UCF64_FMT == 3) {
1032 switch (UCOP_UCF64_FUNC) {
1059 /* Disassemble an F64 instruction */
1060 static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1062 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1064 if (!UCOP_SET(29)) {
1066 do_ucf64_ldst_m(env, s, insn);
1068 do_ucf64_ldst_i(env, s, insn);
1072 switch ((insn >> 26) & 0x3) {
1074 do_ucf64_datap(env, s, insn);
1080 do_ucf64_fcvt(env, s, insn);
1083 do_ucf64_fcmp(env, s, insn);
1087 do_ucf64_trans(env, s, insn);
1092 static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
1094 TranslationBlock *tb;
1097 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
1099 gen_set_pc_im(dest);
1100 tcg_gen_exit_tb((uintptr_t)tb + n);
1102 gen_set_pc_im(dest);
1107 static inline void gen_jmp(DisasContext *s, uint32_t dest)
1109 if (unlikely(s->singlestep_enabled)) {
1110 /* An indirect jump so that we still trigger the debug exception. */
1113 gen_goto_tb(s, 0, dest);
1114 s->is_jmp = DISAS_TB_JUMP;
1118 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
1119 static int gen_set_psr(DisasContext *s, uint32_t mask, int bsr, TCGv t0)
1123 /* ??? This is also undefined in system mode. */
1128 tmp = load_cpu_field(bsr);
1129 tcg_gen_andi_i32(tmp, tmp, ~mask);
1130 tcg_gen_andi_i32(t0, t0, mask);
1131 tcg_gen_or_i32(tmp, tmp, t0);
1132 store_cpu_field(tmp, bsr);
1134 gen_set_asr(t0, mask);
1141 /* Generate an old-style exception return. Marks pc as dead. */
1142 static void gen_exception_return(DisasContext *s, TCGv pc)
1145 store_reg(s, 31, pc);
1146 tmp = load_cpu_field(bsr);
1147 gen_set_asr(tmp, 0xffffffff);
1149 s->is_jmp = DISAS_UPDATE;
1152 static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
1155 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1157 switch (UCOP_CPNUM) {
1158 #ifndef CONFIG_USER_ONLY
1160 disas_cp0_insn(env, s, insn);
1163 disas_ocd_insn(env, s, insn);
1167 disas_ucf64_insn(env, s, insn);
1170 /* Unknown coprocessor. */
1171 cpu_abort(CPU(cpu), "Unknown coprocessor!");
1175 /* data processing instructions */
1176 static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1178 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1183 if (UCOP_OPCODES == 0x0f || UCOP_OPCODES == 0x0d) {
1184 if (UCOP_SET(23)) { /* CMOV instructions */
1185 if ((UCOP_CMOV_COND == 0xe) || (UCOP_CMOV_COND == 0xf)) {
1188 /* if not always execute, we generate a conditional jump to
1190 s->condlabel = gen_new_label();
1191 gen_test_cc(UCOP_CMOV_COND ^ 1, s->condlabel);
1196 logic_cc = table_logic_cc[UCOP_OPCODES] & (UCOP_SET_S >> 24);
1200 /* immediate operand */
1203 val = (val >> UCOP_SH_IM) | (val << (32 - UCOP_SH_IM));
1206 tcg_gen_movi_i32(tmp2, val);
1207 if (logic_cc && UCOP_SH_IM) {
1208 gen_set_CF_bit31(tmp2);
1212 tmp2 = load_reg(s, UCOP_REG_M);
1214 tmp = load_reg(s, UCOP_REG_S);
1215 gen_uc32_shift_reg(tmp2, UCOP_SH_OP, tmp, logic_cc);
1217 gen_uc32_shift_im(tmp2, UCOP_SH_OP, UCOP_SH_IM, logic_cc);
1221 if (UCOP_OPCODES != 0x0f && UCOP_OPCODES != 0x0d) {
1222 tmp = load_reg(s, UCOP_REG_N);
1227 switch (UCOP_OPCODES) {
1229 tcg_gen_and_i32(tmp, tmp, tmp2);
1233 store_reg_bx(s, UCOP_REG_D, tmp);
1236 tcg_gen_xor_i32(tmp, tmp, tmp2);
1240 store_reg_bx(s, UCOP_REG_D, tmp);
1243 if (UCOP_SET_S && UCOP_REG_D == 31) {
1244 /* SUBS r31, ... is used for exception return. */
1248 gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
1249 gen_exception_return(s, tmp);
1252 gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
1254 tcg_gen_sub_i32(tmp, tmp, tmp2);
1256 store_reg_bx(s, UCOP_REG_D, tmp);
1261 gen_helper_sub_cc(tmp, cpu_env, tmp2, tmp);
1263 tcg_gen_sub_i32(tmp, tmp2, tmp);
1265 store_reg_bx(s, UCOP_REG_D, tmp);
1269 gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
1271 tcg_gen_add_i32(tmp, tmp, tmp2);
1273 store_reg_bx(s, UCOP_REG_D, tmp);
1277 gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
1279 gen_add_carry(tmp, tmp, tmp2);
1281 store_reg_bx(s, UCOP_REG_D, tmp);
1285 gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
1287 gen_sub_carry(tmp, tmp, tmp2);
1289 store_reg_bx(s, UCOP_REG_D, tmp);
1293 gen_helper_sbc_cc(tmp, cpu_env, tmp2, tmp);
1295 gen_sub_carry(tmp, tmp2, tmp);
1297 store_reg_bx(s, UCOP_REG_D, tmp);
1301 tcg_gen_and_i32(tmp, tmp, tmp2);
1308 tcg_gen_xor_i32(tmp, tmp, tmp2);
1315 gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
1321 gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
1326 tcg_gen_or_i32(tmp, tmp, tmp2);
1330 store_reg_bx(s, UCOP_REG_D, tmp);
1333 if (logic_cc && UCOP_REG_D == 31) {
1334 /* MOVS r31, ... is used for exception return. */
1338 gen_exception_return(s, tmp2);
1343 store_reg_bx(s, UCOP_REG_D, tmp2);
1347 tcg_gen_andc_i32(tmp, tmp, tmp2);
1351 store_reg_bx(s, UCOP_REG_D, tmp);
1355 tcg_gen_not_i32(tmp2, tmp2);
1359 store_reg_bx(s, UCOP_REG_D, tmp2);
1362 if (UCOP_OPCODES != 0x0f && UCOP_OPCODES != 0x0d) {
1368 static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1370 TCGv tmp, tmp2, tmp3, tmp4;
1374 tmp = load_reg(s, UCOP_REG_M);
1375 tmp2 = load_reg(s, UCOP_REG_N);
1377 tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2);
1379 tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2);
1381 if (UCOP_SET(25)) { /* mult accumulate */
1382 tmp3 = load_reg(s, UCOP_REG_LO);
1383 tmp4 = load_reg(s, UCOP_REG_HI);
1384 tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, tmp3, tmp4);
1388 store_reg(s, UCOP_REG_LO, tmp);
1389 store_reg(s, UCOP_REG_HI, tmp2);
1392 tmp = load_reg(s, UCOP_REG_M);
1393 tmp2 = load_reg(s, UCOP_REG_N);
1394 tcg_gen_mul_i32(tmp, tmp, tmp2);
1398 tmp2 = load_reg(s, UCOP_REG_S);
1399 tcg_gen_add_i32(tmp, tmp, tmp2);
1405 store_reg(s, UCOP_REG_D, tmp);
1409 /* miscellaneous instructions */
1410 static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1412 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1416 if ((insn & 0xffffffe0) == 0x10ffc120) {
1417 /* Trivial implementation equivalent to bx. */
1418 tmp = load_reg(s, UCOP_REG_M);
1423 if ((insn & 0xfbffc000) == 0x30ffc000) {
1424 /* PSR = immediate */
1427 val = (val >> UCOP_SH_IM) | (val << (32 - UCOP_SH_IM));
1430 tcg_gen_movi_i32(tmp, val);
1431 if (gen_set_psr(s, ~ASR_RESERVED, UCOP_SET_B, tmp)) {
1437 if ((insn & 0xfbffffe0) == 0x12ffc020) {
1438 /* PSR.flag = reg */
1439 tmp = load_reg(s, UCOP_REG_M);
1440 if (gen_set_psr(s, ASR_NZCV, UCOP_SET_B, tmp)) {
1446 if ((insn & 0xfbffffe0) == 0x10ffc020) {
1448 tmp = load_reg(s, UCOP_REG_M);
1449 if (gen_set_psr(s, ~ASR_RESERVED, UCOP_SET_B, tmp)) {
1455 if ((insn & 0xfbf83fff) == 0x10f80000) {
1461 tmp = load_cpu_field(bsr);
1464 gen_helper_asr_read(tmp, cpu_env);
1466 store_reg(s, UCOP_REG_D, tmp);
1470 if ((insn & 0xfbf83fe0) == 0x12f80120) {
1472 tmp = load_reg(s, UCOP_REG_M);
1474 gen_helper_clo(tmp, tmp);
1476 gen_helper_clz(tmp, tmp);
1478 store_reg(s, UCOP_REG_D, tmp);
1486 /* load/store I_offset and R_offset */
1487 static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1489 unsigned int mmu_idx;
1493 tmp2 = load_reg(s, UCOP_REG_N);
1494 mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
1498 gen_add_data_offset(s, insn, tmp2);
1504 tmp = gen_ld8u(tmp2, mmu_idx);
1506 tmp = gen_ld32(tmp2, mmu_idx);
1510 tmp = load_reg(s, UCOP_REG_D);
1512 gen_st8(tmp, tmp2, mmu_idx);
1514 gen_st32(tmp, tmp2, mmu_idx);
1518 gen_add_data_offset(s, insn, tmp2);
1519 store_reg(s, UCOP_REG_N, tmp2);
1520 } else if (UCOP_SET_W) {
1521 store_reg(s, UCOP_REG_N, tmp2);
1526 /* Complete the load. */
1527 if (UCOP_REG_D == 31) {
1530 store_reg(s, UCOP_REG_D, tmp);
1535 /* SWP instruction */
1536 static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1538 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1543 if ((insn & 0xff003fe0) != 0x40000120) {
1547 /* ??? This is not really atomic. However we know
1548 we never have multiple CPUs running in parallel,
1549 so it is good enough. */
1550 addr = load_reg(s, UCOP_REG_N);
1551 tmp = load_reg(s, UCOP_REG_M);
1553 tmp2 = gen_ld8u(addr, IS_USER(s));
1554 gen_st8(tmp, addr, IS_USER(s));
1556 tmp2 = gen_ld32(addr, IS_USER(s));
1557 gen_st32(tmp, addr, IS_USER(s));
1560 store_reg(s, UCOP_REG_D, tmp2);
1563 /* load/store hw/sb */
1564 static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1566 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1570 if (UCOP_SH_OP == 0) {
1571 do_swap(env, s, insn);
1575 addr = load_reg(s, UCOP_REG_N);
1577 gen_add_datah_offset(s, insn, addr);
1580 if (UCOP_SET_L) { /* load */
1581 switch (UCOP_SH_OP) {
1583 tmp = gen_ld16u(addr, IS_USER(s));
1586 tmp = gen_ld8s(addr, IS_USER(s));
1588 default: /* see do_swap */
1590 tmp = gen_ld16s(addr, IS_USER(s));
1593 } else { /* store */
1594 if (UCOP_SH_OP != 1) {
1597 tmp = load_reg(s, UCOP_REG_D);
1598 gen_st16(tmp, addr, IS_USER(s));
1600 /* Perform base writeback before the loaded value to
1601 ensure correct behavior with overlapping index registers. */
1603 gen_add_datah_offset(s, insn, addr);
1604 store_reg(s, UCOP_REG_N, addr);
1605 } else if (UCOP_SET_W) {
1606 store_reg(s, UCOP_REG_N, addr);
1611 /* Complete the load. */
1612 store_reg(s, UCOP_REG_D, tmp);
1616 /* load/store multiple words */
1617 static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1619 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1620 unsigned int val, i, mmu_idx;
1621 int j, n, reg, user, loaded_base;
1630 /* XXX: store correct base if write back */
1632 if (UCOP_SET_B) { /* S bit in instruction table */
1634 ILLEGAL; /* only usable in supervisor mode */
1636 if (UCOP_SET(18) == 0) { /* pc reg */
1641 mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
1642 addr = load_reg(s, UCOP_REG_N);
1644 /* compute total size */
1646 TCGV_UNUSED(loaded_var);
1648 for (i = 0; i < 6; i++) {
1653 for (i = 9; i < 19; i++) {
1658 /* XXX: test invalid n == 0 case ? */
1662 tcg_gen_addi_i32(addr, addr, 4);
1664 /* post increment */
1669 tcg_gen_addi_i32(addr, addr, -(n * 4));
1671 /* post decrement */
1673 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
1679 reg = UCOP_SET(6) ? 16 : 0;
1680 for (i = 0; i < 19; i++, reg++) {
1685 if (UCOP_SET_L) { /* load */
1686 tmp = gen_ld32(addr, mmu_idx);
1690 tmp2 = tcg_const_i32(reg);
1691 gen_helper_set_user_reg(cpu_env, tmp2, tmp);
1692 tcg_temp_free_i32(tmp2);
1694 } else if (reg == UCOP_REG_N) {
1698 store_reg(s, reg, tmp);
1700 } else { /* store */
1702 /* special case: r31 = PC + 4 */
1705 tcg_gen_movi_i32(tmp, val);
1708 tmp2 = tcg_const_i32(reg);
1709 gen_helper_get_user_reg(tmp, cpu_env, tmp2);
1710 tcg_temp_free_i32(tmp2);
1712 tmp = load_reg(s, reg);
1714 gen_st32(tmp, addr, mmu_idx);
1717 /* no need to add after the last transfer */
1719 tcg_gen_addi_i32(addr, addr, 4);
1723 if (UCOP_SET_W) { /* write back */
1728 /* post increment */
1729 tcg_gen_addi_i32(addr, addr, 4);
1735 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
1738 /* post decrement */
1739 tcg_gen_addi_i32(addr, addr, -(n * 4));
1742 store_reg(s, UCOP_REG_N, addr);
1747 store_reg(s, UCOP_REG_N, loaded_var);
1749 if (UCOP_SET_B && !user) {
1750 /* Restore ASR from BSR. */
1751 tmp = load_cpu_field(bsr);
1752 gen_set_asr(tmp, 0xffffffff);
1754 s->is_jmp = DISAS_UPDATE;
1758 /* branch (and link) */
1759 static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
1761 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1766 if (UCOP_COND == 0xf) {
1770 if (UCOP_COND != 0xe) {
1771 /* if not always execute, we generate a conditional jump to
1773 s->condlabel = gen_new_label();
1774 gen_test_cc(UCOP_COND ^ 1, s->condlabel);
1778 val = (int32_t)s->pc;
1781 tcg_gen_movi_i32(tmp, val);
1782 store_reg(s, 30, tmp);
1784 offset = (((int32_t)insn << 8) >> 8);
1785 val += (offset << 2); /* unicore is pc+4 */
1789 static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
1791 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1794 insn = cpu_ldl_code(env, s->pc);
1797 /* UniCore instructions class:
1798 * AAAB BBBC xxxx xxxx xxxx xxxD xxEx xxxx
1799 * AAA : see switch case
1800 * BBBB : opcodes or cond or PUBW
1805 switch (insn >> 29) {
1807 if (UCOP_SET(5) && UCOP_SET(8) && !UCOP_SET(28)) {
1808 do_mult(env, s, insn);
1813 do_misc(env, s, insn);
1817 if (((UCOP_OPCODES >> 2) == 2) && !UCOP_SET_S) {
1818 do_misc(env, s, insn);
1821 do_datap(env, s, insn);
1825 if (UCOP_SET(8) && UCOP_SET(5)) {
1826 do_ldst_hwsb(env, s, insn);
1829 if (UCOP_SET(8) || UCOP_SET(5)) {
1833 do_ldst_ir(env, s, insn);
1838 ILLEGAL; /* extended instructions */
1840 do_ldst_m(env, s, insn);
1843 do_branch(env, s, insn);
1847 disas_coproc_insn(env, s, insn);
1850 if (!UCOP_SET(28)) {
1851 disas_coproc_insn(env, s, insn);
1854 if ((insn & 0xff000000) == 0xff000000) { /* syscall */
1855 gen_set_pc_im(s->pc);
1856 s->is_jmp = DISAS_SYSCALL;
1863 /* generate intermediate code for basic block 'tb'. */
1864 void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
1866 UniCore32CPU *cpu = uc32_env_get_cpu(env);
1867 CPUState *cs = CPU(cpu);
1868 DisasContext dc1, *dc = &dc1;
1869 target_ulong pc_start;
1870 uint32_t next_page_start;
1874 /* generate intermediate code */
1881 dc->is_jmp = DISAS_NEXT;
1883 dc->singlestep_enabled = cs->singlestep_enabled;
1885 cpu_F0s = tcg_temp_new_i32();
1886 cpu_F1s = tcg_temp_new_i32();
1887 cpu_F0d = tcg_temp_new_i64();
1888 cpu_F1d = tcg_temp_new_i64();
1889 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1891 max_insns = tb->cflags & CF_COUNT_MASK;
1892 if (max_insns == 0) {
1893 max_insns = CF_COUNT_MASK;
1895 if (max_insns > TCG_MAX_INSNS) {
1896 max_insns = TCG_MAX_INSNS;
1899 #ifndef CONFIG_USER_ONLY
1900 if ((env->uncached_asr & ASR_M) == ASR_MODE_USER) {
1909 tcg_gen_insn_start(dc->pc);
1912 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
1913 gen_set_pc_im(dc->pc);
1914 gen_exception(EXCP_DEBUG);
1915 dc->is_jmp = DISAS_JUMP;
1916 /* The address covered by the breakpoint must be included in
1917 [tb->pc, tb->pc + tb->size) in order to for it to be
1918 properly cleared -- thus we increment the PC here so that
1919 the logic setting tb->size below does the right thing. */
1921 goto done_generating;
1924 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
1928 disas_uc32_insn(env, dc);
1931 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
1935 if (dc->condjmp && !dc->is_jmp) {
1936 gen_set_label(dc->condlabel);
1939 /* Translation stops when a conditional branch is encountered.
1940 * Otherwise the subsequent code could get translated several times.
1941 * Also stop translation when a page boundary is reached. This
1942 * ensures prefetch aborts occur at the right place. */
1943 } while (!dc->is_jmp && !tcg_op_buf_full() &&
1944 !cs->singlestep_enabled &&
1946 dc->pc < next_page_start &&
1947 num_insns < max_insns);
1949 if (tb->cflags & CF_LAST_IO) {
1951 /* FIXME: This can theoretically happen with self-modifying
1953 cpu_abort(cs, "IO on conditional branch instruction");
1958 /* At this stage dc->condjmp will only be set when the skipped
1959 instruction was a conditional branch or trap, and the PC has
1960 already been written. */
1961 if (unlikely(cs->singlestep_enabled)) {
1962 /* Make sure the pc is updated, and raise a debug exception. */
1964 if (dc->is_jmp == DISAS_SYSCALL) {
1965 gen_exception(UC32_EXCP_PRIV);
1967 gen_exception(EXCP_DEBUG);
1969 gen_set_label(dc->condlabel);
1971 if (dc->condjmp || !dc->is_jmp) {
1972 gen_set_pc_im(dc->pc);
1975 if (dc->is_jmp == DISAS_SYSCALL && !dc->condjmp) {
1976 gen_exception(UC32_EXCP_PRIV);
1978 gen_exception(EXCP_DEBUG);
1981 /* While branches must always occur at the end of an IT block,
1982 there are a few other things that can cause us to terminate
1983 the TB in the middel of an IT block:
1984 - Exception generating instructions (bkpt, swi, undefined).
1986 - Hardware watchpoints.
1987 Hardware breakpoints have already been handled and skip this code.
1989 switch (dc->is_jmp) {
1991 gen_goto_tb(dc, 1, dc->pc);
1996 /* indicate that the hash table must be used to find the next TB */
2000 /* nothing more to generate */
2003 gen_exception(UC32_EXCP_PRIV);
2007 gen_set_label(dc->condlabel);
2008 gen_goto_tb(dc, 1, dc->pc);
2014 gen_tb_end(tb, num_insns);
2017 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
2018 qemu_log("----------------\n");
2019 qemu_log("IN: %s\n", lookup_symbol(pc_start));
2020 log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
2024 tb->size = dc->pc - pc_start;
2025 tb->icount = num_insns;
2028 static const char *cpu_mode_names[16] = {
2029 "USER", "REAL", "INTR", "PRIV", "UM14", "UM15", "UM16", "TRAP",
2030 "UM18", "UM19", "UM1A", "EXTN", "UM1C", "UM1D", "UM1E", "SUSR"
2033 #undef UCF64_DUMP_STATE
2034 #ifdef UCF64_DUMP_STATE
2035 static void cpu_dump_state_ucf64(CPUUniCore32State *env, FILE *f,
2036 fprintf_function cpu_fprintf, int flags)
2044 /* ??? This assumes float64 and double have the same layout.
2045 Oh well, it's only debug dumps. */
2051 for (i = 0; i < 16; i++) {
2052 d.d = env->ucf64.regs[i];
2056 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g)",
2057 i * 2, (int)s0.i, s0.s,
2058 i * 2 + 1, (int)s1.i, s1.s);
2059 cpu_fprintf(f, " d%02d=%" PRIx64 "(%8g)\n",
2060 i, (uint64_t)d0.f64, d0.d);
2062 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->ucf64.xregs[UC32_UCF64_FPSCR]);
2065 #define cpu_dump_state_ucf64(env, file, pr, flags) do { } while (0)
2068 void uc32_cpu_dump_state(CPUState *cs, FILE *f,
2069 fprintf_function cpu_fprintf, int flags)
2071 UniCore32CPU *cpu = UNICORE32_CPU(cs);
2072 CPUUniCore32State *env = &cpu->env;
2076 for (i = 0; i < 32; i++) {
2077 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
2079 cpu_fprintf(f, "\n");
2081 cpu_fprintf(f, " ");
2084 psr = cpu_asr_read(env);
2085 cpu_fprintf(f, "PSR=%08x %c%c%c%c %s\n",
2087 psr & (1 << 31) ? 'N' : '-',
2088 psr & (1 << 30) ? 'Z' : '-',
2089 psr & (1 << 29) ? 'C' : '-',
2090 psr & (1 << 28) ? 'V' : '-',
2091 cpu_mode_names[psr & 0xf]);
2093 cpu_dump_state_ucf64(env, f, cpu_fprintf, flags);
2096 void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb,
2099 env->regs[31] = data[0];