2 * Copyright (C) 2010-2012 Guan Xuetao
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Contributions from 2012-04-01 on are considered under GPL version 2,
9 * or (at your option) any later version.
12 #include "qemu/osdep.h"
14 #include "exec/gdbstub.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/host-utils.h"
17 #ifndef CONFIG_USER_ONLY
18 #include "ui/console.h"
24 #define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
26 #define DPRINTF(fmt, ...) do {} while (0)
29 UniCore32CPU *uc32_cpu_init(const char *cpu_model)
31 return UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model));
34 uint32_t HELPER(clo)(uint32_t x)
39 uint32_t HELPER(clz)(uint32_t x)
44 #ifndef CONFIG_USER_ONLY
45 void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
48 UniCore32CPU *cpu = uc32_env_get_cpu(env);
51 * movc pp.nn, rn, #imm9
55 * 2: page table base reg.
56 * 3: data fault status reg.
57 * 4: insn fault status reg.
60 * imm9: split UCOP_IMM10 with bit5 is 0
67 env->cp0.c1_sys = val;
73 env->cp0.c2_base = val;
79 env->cp0.c3_faultstatus = val;
85 env->cp0.c4_faultaddr = val;
90 DPRINTF("Invalidate Entire I&D cache\n");
93 DPRINTF("Invalidate Entire Icache\n");
96 DPRINTF("Invalidate Entire Dcache\n");
99 DPRINTF("Clean Entire Dcache\n");
102 DPRINTF("Flush Entire Dcache\n");
105 DPRINTF("Invalidate Dcache line\n");
108 DPRINTF("Clean Dcache line\n");
111 DPRINTF("Flush Dcache line\n");
116 if ((cop <= 6) && (cop >= 2)) {
117 /* invalid all tlb */
118 tlb_flush(CPU(cpu), 1);
127 DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
131 uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
134 * movc rd, pp.nn, #imm9
137 * 0: cpuid and cachetype
138 * 1: sys control reg.
139 * 2: page table base reg.
140 * 3: data fault status reg.
141 * 4: insn fault status reg.
142 * imm9: split UCOP_IMM10 with bit5 is 0
148 return env->cp0.c0_cpuid;
150 return env->cp0.c0_cachetype;
155 return env->cp0.c1_sys;
160 return env->cp0.c2_base;
165 return env->cp0.c3_faultstatus;
170 return env->cp0.c4_faultaddr;
174 DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
182 * 1. curses windows will be blank when switching back
183 * 2. backspace is not handled yet
185 static void putc_on_screen(unsigned char ch)
187 static WINDOW *localwin;
191 /* Assume 80 * 30 screen to minimize the implementation */
192 localwin = newwin(30, 80, 0, 0);
193 scrollok(localwin, TRUE);
198 wprintw(localwin, "%c", ch);
202 wprintw(localwin, "%c", ch);
205 /* If '\r' is put before '\n', the curses window will destroy the
206 * last print line. And meanwhile, '\n' implifies '\r' inside. */
208 default: /* Not handled, so just print it hex code */
209 wprintw(localwin, "-- 0x%x --", ch);
216 #define putc_on_screen(c) do { } while (0)
219 void helper_cp1_putc(target_ulong x)
221 putc_on_screen((unsigned char)x); /* Output to screen */
222 DPRINTF("%c", x); /* Output to stdout */
226 #ifdef CONFIG_USER_ONLY
227 void switch_mode(CPUUniCore32State *env, int mode)
229 UniCore32CPU *cpu = uc32_env_get_cpu(env);
231 if (mode != ASR_MODE_USER) {
232 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
236 void uc32_cpu_do_interrupt(CPUState *cs)
238 cpu_abort(cs, "NO interrupt in user mode\n");
241 int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
242 int access_type, int mmu_idx)
244 cpu_abort(cs, "NO mmu fault in user mode\n");
249 bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
251 if (interrupt_request & CPU_INTERRUPT_HARD) {
252 UniCore32CPU *cpu = UNICORE32_CPU(cs);
253 CPUUniCore32State *env = &cpu->env;
255 if (!(env->uncached_asr & ASR_I)) {
256 cs->exception_index = UC32_EXCP_INTR;
257 uc32_cpu_do_interrupt(cs);