2 * Helpers for loads and stores
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/helper-proto.h"
23 #include "exec/cpu_ldst.h"
27 //#define DEBUG_UNALIGNED
28 //#define DEBUG_UNASSIGNED
30 //#define DEBUG_CACHE_CONTROL
33 #define DPRINTF_MMU(fmt, ...) \
34 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
36 #define DPRINTF_MMU(fmt, ...) do {} while (0)
40 #define DPRINTF_MXCC(fmt, ...) \
41 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
43 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
47 #define DPRINTF_ASI(fmt, ...) \
48 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
51 #ifdef DEBUG_CACHE_CONTROL
52 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
53 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
55 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
60 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
62 #define AM_CHECK(env1) (1)
66 #define QT0 (env->qt0)
67 #define QT1 (env->qt1)
69 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
70 /* Calculates TSB pointer value for fault page size 8k or 64k */
71 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
72 uint64_t tag_access_register,
75 uint64_t tsb_base = tsb_register & ~0x1fffULL;
76 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
77 int tsb_size = tsb_register & 0xf;
79 /* discard lower 13 bits which hold tag access context */
80 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
82 /* now reorder bits */
83 uint64_t tsb_base_mask = ~0x1fffULL;
84 uint64_t va = tag_access_va;
86 /* move va bits to correct position */
87 if (page_size == 8*1024) {
89 } else if (page_size == 64*1024) {
94 tsb_base_mask <<= tsb_size;
97 /* calculate tsb_base mask and adjust va if split is in use */
99 if (page_size == 8*1024) {
100 va &= ~(1ULL << (13 + tsb_size));
101 } else if (page_size == 64*1024) {
102 va |= (1ULL << (13 + tsb_size));
107 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
110 /* Calculates tag target register value by reordering bits
111 in tag access register */
112 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
114 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
117 static void replace_tlb_entry(SparcTLBEntry *tlb,
118 uint64_t tlb_tag, uint64_t tlb_tte,
121 target_ulong mask, size, va, offset;
123 /* flush page range if translation is valid */
124 if (TTE_IS_VALID(tlb->tte)) {
125 CPUState *cs = CPU(sparc_env_get_cpu(env1));
127 mask = 0xffffffffffffe000ULL;
128 mask <<= 3 * ((tlb->tte >> 61) & 3);
131 va = tlb->tag & mask;
133 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
134 tlb_flush_page(cs, va + offset);
142 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
143 const char *strmmu, CPUSPARCState *env1)
149 int is_demap_context = (demap_addr >> 6) & 1;
152 switch ((demap_addr >> 4) & 3) {
153 case 0: /* primary */
154 context = env1->dmmu.mmu_primary_context;
156 case 1: /* secondary */
157 context = env1->dmmu.mmu_secondary_context;
159 case 2: /* nucleus */
162 case 3: /* reserved */
167 for (i = 0; i < 64; i++) {
168 if (TTE_IS_VALID(tlb[i].tte)) {
170 if (is_demap_context) {
171 /* will remove non-global entries matching context value */
172 if (TTE_IS_GLOBAL(tlb[i].tte) ||
173 !tlb_compare_context(&tlb[i], context)) {
178 will remove any entry matching VA */
179 mask = 0xffffffffffffe000ULL;
180 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
182 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
186 /* entry should be global or matching context value */
187 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
188 !tlb_compare_context(&tlb[i], context)) {
193 replace_tlb_entry(&tlb[i], 0, 0, env1);
195 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
196 dump_mmu(stdout, fprintf, env1);
202 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
203 uint64_t tlb_tag, uint64_t tlb_tte,
204 const char *strmmu, CPUSPARCState *env1)
206 unsigned int i, replace_used;
208 /* Try replacing invalid entry */
209 for (i = 0; i < 64; i++) {
210 if (!TTE_IS_VALID(tlb[i].tte)) {
211 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
213 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
214 dump_mmu(stdout, fprintf, env1);
220 /* All entries are valid, try replacing unlocked entry */
222 for (replace_used = 0; replace_used < 2; ++replace_used) {
224 /* Used entries are not replaced on first pass */
226 for (i = 0; i < 64; i++) {
227 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
229 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
231 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
232 strmmu, (replace_used ? "used" : "unused"), i);
233 dump_mmu(stdout, fprintf, env1);
239 /* Now reset used bit and search for unused entries again */
241 for (i = 0; i < 64; i++) {
242 TTE_SET_UNUSED(tlb[i].tte);
247 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
254 #if defined(TARGET_SPARC64) || defined(CONFIG_USER_ONLY)
255 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
257 #ifdef TARGET_SPARC64
258 if (AM_CHECK(env1)) {
259 addr &= 0xffffffffULL;
266 #ifdef TARGET_SPARC64
267 /* returns true if access using this ASI is to have address translated by MMU
268 otherwise access is to raw physical address */
269 /* TODO: check sparc32 bits */
270 static inline int is_translating_asi(int asi)
272 /* Ultrasparc IIi translating asi
273 - note this list is defined by cpu implementation
290 static inline target_ulong asi_address_mask(CPUSPARCState *env,
291 int asi, target_ulong addr)
293 if (is_translating_asi(asi)) {
294 return address_mask(env, addr);
301 void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
304 #ifdef DEBUG_UNALIGNED
305 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
306 "\n", addr, env->pc);
308 helper_raise_exception(env, TT_UNALIGNED);
312 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
314 static void dump_mxcc(CPUSPARCState *env)
316 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
318 env->mxccdata[0], env->mxccdata[1],
319 env->mxccdata[2], env->mxccdata[3]);
320 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
322 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
324 env->mxccregs[0], env->mxccregs[1],
325 env->mxccregs[2], env->mxccregs[3],
326 env->mxccregs[4], env->mxccregs[5],
327 env->mxccregs[6], env->mxccregs[7]);
331 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
332 && defined(DEBUG_ASI)
333 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
338 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
339 addr, asi, r1 & 0xff);
342 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
343 addr, asi, r1 & 0xffff);
346 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
347 addr, asi, r1 & 0xffffffff);
350 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
357 #ifndef TARGET_SPARC64
358 #ifndef CONFIG_USER_ONLY
361 /* Leon3 cache control */
363 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
364 uint64_t val, int size)
366 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
370 DPRINTF_CACHE_CONTROL("32bits only\n");
375 case 0x00: /* Cache control */
377 /* These values must always be read as zeros */
378 val &= ~CACHE_CTRL_FD;
379 val &= ~CACHE_CTRL_FI;
380 val &= ~CACHE_CTRL_IB;
381 val &= ~CACHE_CTRL_IP;
382 val &= ~CACHE_CTRL_DP;
384 env->cache_control = val;
386 case 0x04: /* Instruction cache configuration */
387 case 0x08: /* Data cache configuration */
391 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
396 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
402 DPRINTF_CACHE_CONTROL("32bits only\n");
407 case 0x00: /* Cache control */
408 ret = env->cache_control;
411 /* Configuration registers are read and only always keep those
414 case 0x04: /* Instruction cache configuration */
417 case 0x08: /* Data cache configuration */
421 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
424 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
429 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
432 CPUState *cs = CPU(sparc_env_get_cpu(env));
434 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
435 uint32_t last_addr = addr;
438 helper_check_align(env, addr, size - 1);
440 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
442 case 0x00: /* Leon3 Cache Control */
443 case 0x08: /* Leon3 Instruction Cache config */
444 case 0x0C: /* Leon3 Date Cache config */
445 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
446 ret = leon3_cache_control_ld(env, addr, size);
449 case 0x01c00a00: /* MXCC control register */
451 ret = env->mxccregs[3];
453 qemu_log_mask(LOG_UNIMP,
454 "%08x: unimplemented access size: %d\n", addr,
458 case 0x01c00a04: /* MXCC control register */
460 ret = env->mxccregs[3];
462 qemu_log_mask(LOG_UNIMP,
463 "%08x: unimplemented access size: %d\n", addr,
467 case 0x01c00c00: /* Module reset register */
469 ret = env->mxccregs[5];
470 /* should we do something here? */
472 qemu_log_mask(LOG_UNIMP,
473 "%08x: unimplemented access size: %d\n", addr,
477 case 0x01c00f00: /* MBus port address register */
479 ret = env->mxccregs[7];
481 qemu_log_mask(LOG_UNIMP,
482 "%08x: unimplemented access size: %d\n", addr,
487 qemu_log_mask(LOG_UNIMP,
488 "%08x: unimplemented address, size: %d\n", addr,
492 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
493 "addr = %08x -> ret = %" PRIx64 ","
494 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
499 case 3: /* MMU probe */
500 case 0x18: /* LEON3 MMU probe */
504 mmulev = (addr >> 8) & 15;
508 ret = mmu_probe(env, addr, mmulev);
510 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
514 case 4: /* read MMU regs */
515 case 0x19: /* LEON3 read MMU regs */
517 int reg = (addr >> 8) & 0x1f;
519 ret = env->mmuregs[reg];
520 if (reg == 3) { /* Fault status cleared on read */
522 } else if (reg == 0x13) { /* Fault status read */
523 ret = env->mmuregs[3];
524 } else if (reg == 0x14) { /* Fault address read */
525 ret = env->mmuregs[4];
527 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
530 case 5: /* Turbosparc ITLB Diagnostic */
531 case 6: /* Turbosparc DTLB Diagnostic */
532 case 7: /* Turbosparc IOTLB Diagnostic */
534 case 9: /* Supervisor code access */
537 ret = cpu_ldub_code(env, addr);
540 ret = cpu_lduw_code(env, addr);
544 ret = cpu_ldl_code(env, addr);
547 ret = cpu_ldq_code(env, addr);
551 case 0xa: /* User data access */
554 ret = cpu_ldub_user(env, addr);
557 ret = cpu_lduw_user(env, addr);
561 ret = cpu_ldl_user(env, addr);
564 ret = cpu_ldq_user(env, addr);
568 case 0xb: /* Supervisor data access */
572 ret = cpu_ldub_kernel(env, addr);
575 ret = cpu_lduw_kernel(env, addr);
579 ret = cpu_ldl_kernel(env, addr);
582 ret = cpu_ldq_kernel(env, addr);
586 case 0xc: /* I-cache tag */
587 case 0xd: /* I-cache data */
588 case 0xe: /* D-cache tag */
589 case 0xf: /* D-cache data */
591 case 0x20: /* MMU passthrough */
592 case 0x1c: /* LEON MMU passthrough */
595 ret = ldub_phys(cs->as, addr);
598 ret = lduw_phys(cs->as, addr);
602 ret = ldl_phys(cs->as, addr);
605 ret = ldq_phys(cs->as, addr);
609 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
612 ret = ldub_phys(cs->as, (hwaddr)addr
613 | ((hwaddr)(asi & 0xf) << 32));
616 ret = lduw_phys(cs->as, (hwaddr)addr
617 | ((hwaddr)(asi & 0xf) << 32));
621 ret = ldl_phys(cs->as, (hwaddr)addr
622 | ((hwaddr)(asi & 0xf) << 32));
625 ret = ldq_phys(cs->as, (hwaddr)addr
626 | ((hwaddr)(asi & 0xf) << 32));
630 case 0x30: /* Turbosparc secondary cache diagnostic */
631 case 0x31: /* Turbosparc RAM snoop */
632 case 0x32: /* Turbosparc page table descriptor diagnostic */
633 case 0x39: /* data cache diagnostic register */
636 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
638 int reg = (addr >> 8) & 3;
641 case 0: /* Breakpoint Value (Addr) */
642 ret = env->mmubpregs[reg];
644 case 1: /* Breakpoint Mask */
645 ret = env->mmubpregs[reg];
647 case 2: /* Breakpoint Control */
648 ret = env->mmubpregs[reg];
650 case 3: /* Breakpoint Status */
651 ret = env->mmubpregs[reg];
652 env->mmubpregs[reg] = 0ULL;
655 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
659 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
660 ret = env->mmubpctrv;
662 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
663 ret = env->mmubpctrc;
665 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
666 ret = env->mmubpctrs;
668 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
669 ret = env->mmubpaction;
671 case 8: /* User code access, XXX */
673 cpu_unassigned_access(cs, addr, false, false, asi, size);
693 dump_asi("read ", last_addr, asi, size, ret);
698 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
701 SPARCCPU *cpu = sparc_env_get_cpu(env);
702 CPUState *cs = CPU(cpu);
704 helper_check_align(env, addr, size - 1);
706 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
708 case 0x00: /* Leon3 Cache Control */
709 case 0x08: /* Leon3 Instruction Cache config */
710 case 0x0C: /* Leon3 Date Cache config */
711 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
712 leon3_cache_control_st(env, addr, val, size);
716 case 0x01c00000: /* MXCC stream data register 0 */
718 env->mxccdata[0] = val;
720 qemu_log_mask(LOG_UNIMP,
721 "%08x: unimplemented access size: %d\n", addr,
725 case 0x01c00008: /* MXCC stream data register 1 */
727 env->mxccdata[1] = val;
729 qemu_log_mask(LOG_UNIMP,
730 "%08x: unimplemented access size: %d\n", addr,
734 case 0x01c00010: /* MXCC stream data register 2 */
736 env->mxccdata[2] = val;
738 qemu_log_mask(LOG_UNIMP,
739 "%08x: unimplemented access size: %d\n", addr,
743 case 0x01c00018: /* MXCC stream data register 3 */
745 env->mxccdata[3] = val;
747 qemu_log_mask(LOG_UNIMP,
748 "%08x: unimplemented access size: %d\n", addr,
752 case 0x01c00100: /* MXCC stream source */
754 env->mxccregs[0] = val;
756 qemu_log_mask(LOG_UNIMP,
757 "%08x: unimplemented access size: %d\n", addr,
760 env->mxccdata[0] = ldq_phys(cs->as,
761 (env->mxccregs[0] & 0xffffffffULL) +
763 env->mxccdata[1] = ldq_phys(cs->as,
764 (env->mxccregs[0] & 0xffffffffULL) +
766 env->mxccdata[2] = ldq_phys(cs->as,
767 (env->mxccregs[0] & 0xffffffffULL) +
769 env->mxccdata[3] = ldq_phys(cs->as,
770 (env->mxccregs[0] & 0xffffffffULL) +
773 case 0x01c00200: /* MXCC stream destination */
775 env->mxccregs[1] = val;
777 qemu_log_mask(LOG_UNIMP,
778 "%08x: unimplemented access size: %d\n", addr,
781 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 0,
783 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 8,
785 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 16,
787 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 24,
790 case 0x01c00a00: /* MXCC control register */
792 env->mxccregs[3] = val;
794 qemu_log_mask(LOG_UNIMP,
795 "%08x: unimplemented access size: %d\n", addr,
799 case 0x01c00a04: /* MXCC control register */
801 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
804 qemu_log_mask(LOG_UNIMP,
805 "%08x: unimplemented access size: %d\n", addr,
809 case 0x01c00e00: /* MXCC error register */
810 /* writing a 1 bit clears the error */
812 env->mxccregs[6] &= ~val;
814 qemu_log_mask(LOG_UNIMP,
815 "%08x: unimplemented access size: %d\n", addr,
819 case 0x01c00f00: /* MBus port address register */
821 env->mxccregs[7] = val;
823 qemu_log_mask(LOG_UNIMP,
824 "%08x: unimplemented access size: %d\n", addr,
829 qemu_log_mask(LOG_UNIMP,
830 "%08x: unimplemented address, size: %d\n", addr,
834 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
835 asi, size, addr, val);
840 case 3: /* MMU flush */
841 case 0x18: /* LEON3 MMU flush */
845 mmulev = (addr >> 8) & 15;
846 DPRINTF_MMU("mmu flush level %d\n", mmulev);
848 case 0: /* flush page */
849 tlb_flush_page(CPU(cpu), addr & 0xfffff000);
851 case 1: /* flush segment (256k) */
852 case 2: /* flush region (16M) */
853 case 3: /* flush context (4G) */
854 case 4: /* flush entire */
855 tlb_flush(CPU(cpu), 1);
861 dump_mmu(stdout, fprintf, env);
865 case 4: /* write MMU regs */
866 case 0x19: /* LEON3 write MMU regs */
868 int reg = (addr >> 8) & 0x1f;
871 oldreg = env->mmuregs[reg];
873 case 0: /* Control Register */
874 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
876 /* Mappings generated during no-fault mode or MMU
877 disabled mode are invalid in normal mode */
878 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
879 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
880 tlb_flush(CPU(cpu), 1);
883 case 1: /* Context Table Pointer Register */
884 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
886 case 2: /* Context Register */
887 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
888 if (oldreg != env->mmuregs[reg]) {
889 /* we flush when the MMU context changes because
890 QEMU has no MMU context support */
891 tlb_flush(CPU(cpu), 1);
894 case 3: /* Synchronous Fault Status Register with Clear */
895 case 4: /* Synchronous Fault Address Register */
897 case 0x10: /* TLB Replacement Control Register */
898 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
900 case 0x13: /* Synchronous Fault Status Register with Read
902 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
904 case 0x14: /* Synchronous Fault Address Register */
905 env->mmuregs[4] = val;
908 env->mmuregs[reg] = val;
911 if (oldreg != env->mmuregs[reg]) {
912 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
913 reg, oldreg, env->mmuregs[reg]);
916 dump_mmu(stdout, fprintf, env);
920 case 5: /* Turbosparc ITLB Diagnostic */
921 case 6: /* Turbosparc DTLB Diagnostic */
922 case 7: /* Turbosparc IOTLB Diagnostic */
924 case 0xa: /* User data access */
927 cpu_stb_user(env, addr, val);
930 cpu_stw_user(env, addr, val);
934 cpu_stl_user(env, addr, val);
937 cpu_stq_user(env, addr, val);
941 case 0xb: /* Supervisor data access */
945 cpu_stb_kernel(env, addr, val);
948 cpu_stw_kernel(env, addr, val);
952 cpu_stl_kernel(env, addr, val);
955 cpu_stq_kernel(env, addr, val);
959 case 0xc: /* I-cache tag */
960 case 0xd: /* I-cache data */
961 case 0xe: /* D-cache tag */
962 case 0xf: /* D-cache data */
963 case 0x10: /* I/D-cache flush page */
964 case 0x11: /* I/D-cache flush segment */
965 case 0x12: /* I/D-cache flush region */
966 case 0x13: /* I/D-cache flush context */
967 case 0x14: /* I/D-cache flush user */
969 case 0x17: /* Block copy, sta access */
975 uint32_t src = val & ~3, dst = addr & ~3, temp;
977 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
978 temp = cpu_ldl_kernel(env, src);
979 cpu_stl_kernel(env, dst, temp);
983 case 0x1f: /* Block fill, stda access */
986 fill 32 bytes with val */
988 uint32_t dst = addr & 7;
990 for (i = 0; i < 32; i += 8, dst += 8) {
991 cpu_stq_kernel(env, dst, val);
995 case 0x20: /* MMU passthrough */
996 case 0x1c: /* LEON MMU passthrough */
1000 stb_phys(cs->as, addr, val);
1003 stw_phys(cs->as, addr, val);
1007 stl_phys(cs->as, addr, val);
1010 stq_phys(cs->as, addr, val);
1015 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1019 stb_phys(cs->as, (hwaddr)addr
1020 | ((hwaddr)(asi & 0xf) << 32), val);
1023 stw_phys(cs->as, (hwaddr)addr
1024 | ((hwaddr)(asi & 0xf) << 32), val);
1028 stl_phys(cs->as, (hwaddr)addr
1029 | ((hwaddr)(asi & 0xf) << 32), val);
1032 stq_phys(cs->as, (hwaddr)addr
1033 | ((hwaddr)(asi & 0xf) << 32), val);
1038 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1039 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1040 Turbosparc snoop RAM */
1041 case 0x32: /* store buffer control or Turbosparc page table
1042 descriptor diagnostic */
1043 case 0x36: /* I-cache flash clear */
1044 case 0x37: /* D-cache flash clear */
1046 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1048 int reg = (addr >> 8) & 3;
1051 case 0: /* Breakpoint Value (Addr) */
1052 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1054 case 1: /* Breakpoint Mask */
1055 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1057 case 2: /* Breakpoint Control */
1058 env->mmubpregs[reg] = (val & 0x7fULL);
1060 case 3: /* Breakpoint Status */
1061 env->mmubpregs[reg] = (val & 0xfULL);
1064 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1068 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1069 env->mmubpctrv = val & 0xffffffff;
1071 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1072 env->mmubpctrc = val & 0x3;
1074 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1075 env->mmubpctrs = val & 0x3;
1077 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1078 env->mmubpaction = val & 0x1fff;
1080 case 8: /* User code access, XXX */
1081 case 9: /* Supervisor code access, XXX */
1083 cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
1084 addr, true, false, asi, size);
1088 dump_asi("write", addr, asi, size, val);
1092 #endif /* CONFIG_USER_ONLY */
1093 #else /* TARGET_SPARC64 */
1095 #ifdef CONFIG_USER_ONLY
1096 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1100 #if defined(DEBUG_ASI)
1101 target_ulong last_addr = addr;
1105 helper_raise_exception(env, TT_PRIV_ACT);
1108 helper_check_align(env, addr, size - 1);
1109 addr = asi_address_mask(env, asi, addr);
1112 case 0x82: /* Primary no-fault */
1113 case 0x8a: /* Primary no-fault LE */
1114 if (page_check_range(addr, size, PAGE_READ) == -1) {
1116 dump_asi("read ", last_addr, asi, size, ret);
1121 case 0x80: /* Primary */
1122 case 0x88: /* Primary LE */
1126 ret = cpu_ldub_data(env, addr);
1129 ret = cpu_lduw_data(env, addr);
1132 ret = cpu_ldl_data(env, addr);
1136 ret = cpu_ldq_data(env, addr);
1141 case 0x83: /* Secondary no-fault */
1142 case 0x8b: /* Secondary no-fault LE */
1143 if (page_check_range(addr, size, PAGE_READ) == -1) {
1145 dump_asi("read ", last_addr, asi, size, ret);
1150 case 0x81: /* Secondary */
1151 case 0x89: /* Secondary LE */
1158 /* Convert from little endian */
1160 case 0x88: /* Primary LE */
1161 case 0x89: /* Secondary LE */
1162 case 0x8a: /* Primary no-fault LE */
1163 case 0x8b: /* Secondary no-fault LE */
1181 /* Convert to signed number */
1188 ret = (int16_t) ret;
1191 ret = (int32_t) ret;
1198 dump_asi("read ", last_addr, asi, size, ret);
1203 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1207 dump_asi("write", addr, asi, size, val);
1210 helper_raise_exception(env, TT_PRIV_ACT);
1213 helper_check_align(env, addr, size - 1);
1214 addr = asi_address_mask(env, asi, addr);
1216 /* Convert to little endian */
1218 case 0x88: /* Primary LE */
1219 case 0x89: /* Secondary LE */
1238 case 0x80: /* Primary */
1239 case 0x88: /* Primary LE */
1243 cpu_stb_data(env, addr, val);
1246 cpu_stw_data(env, addr, val);
1249 cpu_stl_data(env, addr, val);
1253 cpu_stq_data(env, addr, val);
1258 case 0x81: /* Secondary */
1259 case 0x89: /* Secondary LE */
1263 case 0x82: /* Primary no-fault, RO */
1264 case 0x83: /* Secondary no-fault, RO */
1265 case 0x8a: /* Primary no-fault LE, RO */
1266 case 0x8b: /* Secondary no-fault LE, RO */
1268 helper_raise_exception(env, TT_DATA_ACCESS);
1273 #else /* CONFIG_USER_ONLY */
1275 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1278 CPUState *cs = CPU(sparc_env_get_cpu(env));
1280 #if defined(DEBUG_ASI)
1281 target_ulong last_addr = addr;
1286 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1287 || (cpu_has_hypervisor(env)
1288 && asi >= 0x30 && asi < 0x80
1289 && !(env->hpstate & HS_PRIV))) {
1290 helper_raise_exception(env, TT_PRIV_ACT);
1293 helper_check_align(env, addr, size - 1);
1294 addr = asi_address_mask(env, asi, addr);
1296 /* process nonfaulting loads first */
1297 if ((asi & 0xf6) == 0x82) {
1300 /* secondary space access has lowest asi bit equal to 1 */
1301 if (env->pstate & PS_PRIV) {
1302 mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
1304 mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
1307 if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
1309 dump_asi("read ", last_addr, asi, size, ret);
1311 /* env->exception_index is set in get_physical_address_data(). */
1312 helper_raise_exception(env, cs->exception_index);
1315 /* convert nonfaulting load ASIs to normal load ASIs */
1320 case 0x10: /* As if user primary */
1321 case 0x11: /* As if user secondary */
1322 case 0x18: /* As if user primary LE */
1323 case 0x19: /* As if user secondary LE */
1324 case 0x80: /* Primary */
1325 case 0x81: /* Secondary */
1326 case 0x88: /* Primary LE */
1327 case 0x89: /* Secondary LE */
1328 case 0xe2: /* UA2007 Primary block init */
1329 case 0xe3: /* UA2007 Secondary block init */
1330 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1331 if (cpu_hypervisor_mode(env)) {
1334 ret = cpu_ldub_hypv(env, addr);
1337 ret = cpu_lduw_hypv(env, addr);
1340 ret = cpu_ldl_hypv(env, addr);
1344 ret = cpu_ldq_hypv(env, addr);
1348 /* secondary space access has lowest asi bit equal to 1 */
1352 ret = cpu_ldub_kernel_secondary(env, addr);
1355 ret = cpu_lduw_kernel_secondary(env, addr);
1358 ret = cpu_ldl_kernel_secondary(env, addr);
1362 ret = cpu_ldq_kernel_secondary(env, addr);
1368 ret = cpu_ldub_kernel(env, addr);
1371 ret = cpu_lduw_kernel(env, addr);
1374 ret = cpu_ldl_kernel(env, addr);
1378 ret = cpu_ldq_kernel(env, addr);
1384 /* secondary space access has lowest asi bit equal to 1 */
1388 ret = cpu_ldub_user_secondary(env, addr);
1391 ret = cpu_lduw_user_secondary(env, addr);
1394 ret = cpu_ldl_user_secondary(env, addr);
1398 ret = cpu_ldq_user_secondary(env, addr);
1404 ret = cpu_ldub_user(env, addr);
1407 ret = cpu_lduw_user(env, addr);
1410 ret = cpu_ldl_user(env, addr);
1414 ret = cpu_ldq_user(env, addr);
1420 case 0x14: /* Bypass */
1421 case 0x15: /* Bypass, non-cacheable */
1422 case 0x1c: /* Bypass LE */
1423 case 0x1d: /* Bypass, non-cacheable LE */
1427 ret = ldub_phys(cs->as, addr);
1430 ret = lduw_phys(cs->as, addr);
1433 ret = ldl_phys(cs->as, addr);
1437 ret = ldq_phys(cs->as, addr);
1442 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1443 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1444 Only ldda allowed */
1445 helper_raise_exception(env, TT_ILL_INSN);
1447 case 0x04: /* Nucleus */
1448 case 0x0c: /* Nucleus Little Endian (LE) */
1452 ret = cpu_ldub_nucleus(env, addr);
1455 ret = cpu_lduw_nucleus(env, addr);
1458 ret = cpu_ldl_nucleus(env, addr);
1462 ret = cpu_ldq_nucleus(env, addr);
1467 case 0x4a: /* UPA config */
1470 case 0x45: /* LSU */
1473 case 0x50: /* I-MMU regs */
1475 int reg = (addr >> 3) & 0xf;
1478 /* I-TSB Tag Target register */
1479 ret = ultrasparc_tag_target(env->immu.tag_access);
1481 ret = env->immuregs[reg];
1486 case 0x51: /* I-MMU 8k TSB pointer */
1488 /* env->immuregs[5] holds I-MMU TSB register value
1489 env->immuregs[6] holds I-MMU Tag Access register value */
1490 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1494 case 0x52: /* I-MMU 64k TSB pointer */
1496 /* env->immuregs[5] holds I-MMU TSB register value
1497 env->immuregs[6] holds I-MMU Tag Access register value */
1498 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1502 case 0x55: /* I-MMU data access */
1504 int reg = (addr >> 3) & 0x3f;
1506 ret = env->itlb[reg].tte;
1509 case 0x56: /* I-MMU tag read */
1511 int reg = (addr >> 3) & 0x3f;
1513 ret = env->itlb[reg].tag;
1516 case 0x58: /* D-MMU regs */
1518 int reg = (addr >> 3) & 0xf;
1521 /* D-TSB Tag Target register */
1522 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1524 ret = env->dmmuregs[reg];
1528 case 0x59: /* D-MMU 8k TSB pointer */
1530 /* env->dmmuregs[5] holds D-MMU TSB register value
1531 env->dmmuregs[6] holds D-MMU Tag Access register value */
1532 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1536 case 0x5a: /* D-MMU 64k TSB pointer */
1538 /* env->dmmuregs[5] holds D-MMU TSB register value
1539 env->dmmuregs[6] holds D-MMU Tag Access register value */
1540 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1544 case 0x5d: /* D-MMU data access */
1546 int reg = (addr >> 3) & 0x3f;
1548 ret = env->dtlb[reg].tte;
1551 case 0x5e: /* D-MMU tag read */
1553 int reg = (addr >> 3) & 0x3f;
1555 ret = env->dtlb[reg].tag;
1558 case 0x48: /* Interrupt dispatch, RO */
1560 case 0x49: /* Interrupt data receive */
1561 ret = env->ivec_status;
1563 case 0x7f: /* Incoming interrupt vector, RO */
1565 int reg = (addr >> 4) & 0x3;
1567 ret = env->ivec_data[reg];
1571 case 0x46: /* D-cache data */
1572 case 0x47: /* D-cache tag access */
1573 case 0x4b: /* E-cache error enable */
1574 case 0x4c: /* E-cache asynchronous fault status */
1575 case 0x4d: /* E-cache asynchronous fault address */
1576 case 0x4e: /* E-cache tag data */
1577 case 0x66: /* I-cache instruction access */
1578 case 0x67: /* I-cache tag access */
1579 case 0x6e: /* I-cache predecode */
1580 case 0x6f: /* I-cache LRU etc. */
1581 case 0x76: /* E-cache tag */
1582 case 0x7e: /* E-cache tag */
1584 case 0x5b: /* D-MMU data pointer */
1585 case 0x54: /* I-MMU data in, WO */
1586 case 0x57: /* I-MMU demap, WO */
1587 case 0x5c: /* D-MMU data in, WO */
1588 case 0x5f: /* D-MMU demap, WO */
1589 case 0x77: /* Interrupt vector, WO */
1591 cpu_unassigned_access(cs, addr, false, false, 1, size);
1596 /* Convert from little endian */
1598 case 0x0c: /* Nucleus Little Endian (LE) */
1599 case 0x18: /* As if user primary LE */
1600 case 0x19: /* As if user secondary LE */
1601 case 0x1c: /* Bypass LE */
1602 case 0x1d: /* Bypass, non-cacheable LE */
1603 case 0x88: /* Primary LE */
1604 case 0x89: /* Secondary LE */
1622 /* Convert to signed number */
1629 ret = (int16_t) ret;
1632 ret = (int32_t) ret;
1639 dump_asi("read ", last_addr, asi, size, ret);
1644 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1647 SPARCCPU *cpu = sparc_env_get_cpu(env);
1648 CPUState *cs = CPU(cpu);
1651 dump_asi("write", addr, asi, size, val);
1656 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1657 || (cpu_has_hypervisor(env)
1658 && asi >= 0x30 && asi < 0x80
1659 && !(env->hpstate & HS_PRIV))) {
1660 helper_raise_exception(env, TT_PRIV_ACT);
1663 helper_check_align(env, addr, size - 1);
1664 addr = asi_address_mask(env, asi, addr);
1666 /* Convert to little endian */
1668 case 0x0c: /* Nucleus Little Endian (LE) */
1669 case 0x18: /* As if user primary LE */
1670 case 0x19: /* As if user secondary LE */
1671 case 0x1c: /* Bypass LE */
1672 case 0x1d: /* Bypass, non-cacheable LE */
1673 case 0x88: /* Primary LE */
1674 case 0x89: /* Secondary LE */
1693 case 0x10: /* As if user primary */
1694 case 0x11: /* As if user secondary */
1695 case 0x18: /* As if user primary LE */
1696 case 0x19: /* As if user secondary LE */
1697 case 0x80: /* Primary */
1698 case 0x81: /* Secondary */
1699 case 0x88: /* Primary LE */
1700 case 0x89: /* Secondary LE */
1701 case 0xe2: /* UA2007 Primary block init */
1702 case 0xe3: /* UA2007 Secondary block init */
1703 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1704 if (cpu_hypervisor_mode(env)) {
1707 cpu_stb_hypv(env, addr, val);
1710 cpu_stw_hypv(env, addr, val);
1713 cpu_stl_hypv(env, addr, val);
1717 cpu_stq_hypv(env, addr, val);
1721 /* secondary space access has lowest asi bit equal to 1 */
1725 cpu_stb_kernel_secondary(env, addr, val);
1728 cpu_stw_kernel_secondary(env, addr, val);
1731 cpu_stl_kernel_secondary(env, addr, val);
1735 cpu_stq_kernel_secondary(env, addr, val);
1741 cpu_stb_kernel(env, addr, val);
1744 cpu_stw_kernel(env, addr, val);
1747 cpu_stl_kernel(env, addr, val);
1751 cpu_stq_kernel(env, addr, val);
1757 /* secondary space access has lowest asi bit equal to 1 */
1761 cpu_stb_user_secondary(env, addr, val);
1764 cpu_stw_user_secondary(env, addr, val);
1767 cpu_stl_user_secondary(env, addr, val);
1771 cpu_stq_user_secondary(env, addr, val);
1777 cpu_stb_user(env, addr, val);
1780 cpu_stw_user(env, addr, val);
1783 cpu_stl_user(env, addr, val);
1787 cpu_stq_user(env, addr, val);
1793 case 0x14: /* Bypass */
1794 case 0x15: /* Bypass, non-cacheable */
1795 case 0x1c: /* Bypass LE */
1796 case 0x1d: /* Bypass, non-cacheable LE */
1800 stb_phys(cs->as, addr, val);
1803 stw_phys(cs->as, addr, val);
1806 stl_phys(cs->as, addr, val);
1810 stq_phys(cs->as, addr, val);
1815 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1816 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1817 Only ldda allowed */
1818 helper_raise_exception(env, TT_ILL_INSN);
1820 case 0x04: /* Nucleus */
1821 case 0x0c: /* Nucleus Little Endian (LE) */
1825 cpu_stb_nucleus(env, addr, val);
1828 cpu_stw_nucleus(env, addr, val);
1831 cpu_stl_nucleus(env, addr, val);
1835 cpu_stq_nucleus(env, addr, val);
1841 case 0x4a: /* UPA config */
1844 case 0x45: /* LSU */
1849 env->lsu = val & (DMMU_E | IMMU_E);
1850 /* Mappings generated during D/I MMU disabled mode are
1851 invalid in normal mode */
1852 if (oldreg != env->lsu) {
1853 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1856 dump_mmu(stdout, fprintf, env);
1858 tlb_flush(CPU(cpu), 1);
1862 case 0x50: /* I-MMU regs */
1864 int reg = (addr >> 3) & 0xf;
1867 oldreg = env->immuregs[reg];
1871 case 1: /* Not in I-MMU */
1875 if ((val & 1) == 0) {
1876 val = 0; /* Clear SFSR */
1878 env->immu.sfsr = val;
1882 case 5: /* TSB access */
1883 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1884 PRIx64 "\n", env->immu.tsb, val);
1885 env->immu.tsb = val;
1887 case 6: /* Tag access */
1888 env->immu.tag_access = val;
1897 if (oldreg != env->immuregs[reg]) {
1898 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1899 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1902 dump_mmu(stdout, fprintf, env);
1906 case 0x54: /* I-MMU data in */
1907 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1909 case 0x55: /* I-MMU data access */
1911 /* TODO: auto demap */
1913 unsigned int i = (addr >> 3) & 0x3f;
1915 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1918 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1919 dump_mmu(stdout, fprintf, env);
1923 case 0x57: /* I-MMU demap */
1924 demap_tlb(env->itlb, addr, "immu", env);
1926 case 0x58: /* D-MMU regs */
1928 int reg = (addr >> 3) & 0xf;
1931 oldreg = env->dmmuregs[reg];
1937 if ((val & 1) == 0) {
1938 val = 0; /* Clear SFSR, Fault address */
1941 env->dmmu.sfsr = val;
1943 case 1: /* Primary context */
1944 env->dmmu.mmu_primary_context = val;
1945 /* can be optimized to only flush MMU_USER_IDX
1946 and MMU_KERNEL_IDX entries */
1947 tlb_flush(CPU(cpu), 1);
1949 case 2: /* Secondary context */
1950 env->dmmu.mmu_secondary_context = val;
1951 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1952 and MMU_KERNEL_SECONDARY_IDX entries */
1953 tlb_flush(CPU(cpu), 1);
1955 case 5: /* TSB access */
1956 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1957 PRIx64 "\n", env->dmmu.tsb, val);
1958 env->dmmu.tsb = val;
1960 case 6: /* Tag access */
1961 env->dmmu.tag_access = val;
1963 case 7: /* Virtual Watchpoint */
1964 case 8: /* Physical Watchpoint */
1966 env->dmmuregs[reg] = val;
1970 if (oldreg != env->dmmuregs[reg]) {
1971 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1972 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1975 dump_mmu(stdout, fprintf, env);
1979 case 0x5c: /* D-MMU data in */
1980 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
1982 case 0x5d: /* D-MMU data access */
1984 unsigned int i = (addr >> 3) & 0x3f;
1986 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
1989 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1990 dump_mmu(stdout, fprintf, env);
1994 case 0x5f: /* D-MMU demap */
1995 demap_tlb(env->dtlb, addr, "dmmu", env);
1997 case 0x49: /* Interrupt data receive */
1998 env->ivec_status = val & 0x20;
2000 case 0x46: /* D-cache data */
2001 case 0x47: /* D-cache tag access */
2002 case 0x4b: /* E-cache error enable */
2003 case 0x4c: /* E-cache asynchronous fault status */
2004 case 0x4d: /* E-cache asynchronous fault address */
2005 case 0x4e: /* E-cache tag data */
2006 case 0x66: /* I-cache instruction access */
2007 case 0x67: /* I-cache tag access */
2008 case 0x6e: /* I-cache predecode */
2009 case 0x6f: /* I-cache LRU etc. */
2010 case 0x76: /* E-cache tag */
2011 case 0x7e: /* E-cache tag */
2013 case 0x51: /* I-MMU 8k TSB pointer, RO */
2014 case 0x52: /* I-MMU 64k TSB pointer, RO */
2015 case 0x56: /* I-MMU tag read, RO */
2016 case 0x59: /* D-MMU 8k TSB pointer, RO */
2017 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2018 case 0x5b: /* D-MMU data pointer, RO */
2019 case 0x5e: /* D-MMU tag read, RO */
2020 case 0x48: /* Interrupt dispatch, RO */
2021 case 0x7f: /* Incoming interrupt vector, RO */
2022 case 0x82: /* Primary no-fault, RO */
2023 case 0x83: /* Secondary no-fault, RO */
2024 case 0x8a: /* Primary no-fault LE, RO */
2025 case 0x8b: /* Secondary no-fault LE, RO */
2027 cpu_unassigned_access(cs, addr, true, false, 1, size);
2031 #endif /* CONFIG_USER_ONLY */
2033 void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi, int rd)
2035 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2036 || (cpu_has_hypervisor(env)
2037 && asi >= 0x30 && asi < 0x80
2038 && !(env->hpstate & HS_PRIV))) {
2039 helper_raise_exception(env, TT_PRIV_ACT);
2042 addr = asi_address_mask(env, asi, addr);
2045 #if !defined(CONFIG_USER_ONLY)
2046 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2047 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2048 helper_check_align(env, addr, 0xf);
2050 env->gregs[1] = cpu_ldq_nucleus(env, addr + 8);
2052 bswap64s(&env->gregs[1]);
2054 } else if (rd < 8) {
2055 env->gregs[rd] = cpu_ldq_nucleus(env, addr);
2056 env->gregs[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2058 bswap64s(&env->gregs[rd]);
2059 bswap64s(&env->gregs[rd + 1]);
2062 env->regwptr[rd - 8] = cpu_ldq_nucleus(env, addr);
2063 env->regwptr[rd + 1 - 8] = cpu_ldq_nucleus(env, addr + 8);
2065 bswap64s(&env->regwptr[rd - 8]);
2066 bswap64s(&env->regwptr[rd + 1 - 8]);
2072 helper_check_align(env, addr, 0x3);
2074 env->gregs[1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2075 } else if (rd < 8) {
2076 env->gregs[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2077 env->gregs[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2079 env->regwptr[rd - 8] = helper_ld_asi(env, addr, asi, 4, 0);
2080 env->regwptr[rd + 1 - 8] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2086 void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2092 helper_check_align(env, addr, 3);
2093 addr = asi_address_mask(env, asi, addr);
2096 case 0xf0: /* UA2007/JPS1 Block load primary */
2097 case 0xf1: /* UA2007/JPS1 Block load secondary */
2098 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2099 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2101 helper_raise_exception(env, TT_ILL_INSN);
2104 helper_check_align(env, addr, 0x3f);
2105 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2106 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, 8, 0);
2110 case 0x16: /* UA2007 Block load primary, user privilege */
2111 case 0x17: /* UA2007 Block load secondary, user privilege */
2112 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2113 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2114 case 0x70: /* JPS1 Block load primary, user privilege */
2115 case 0x71: /* JPS1 Block load secondary, user privilege */
2116 case 0x78: /* JPS1 Block load primary LE, user privilege */
2117 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2119 helper_raise_exception(env, TT_ILL_INSN);
2122 helper_check_align(env, addr, 0x3f);
2123 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2124 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
2135 val = helper_ld_asi(env, addr, asi, size, 0);
2137 env->fpr[rd / 2].l.lower = val;
2139 env->fpr[rd / 2].l.upper = val;
2143 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, size, 0);
2146 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, 8, 0);
2147 env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, 8, 0);
2152 void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2158 addr = asi_address_mask(env, asi, addr);
2161 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2162 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2163 case 0xf0: /* UA2007/JPS1 Block store primary */
2164 case 0xf1: /* UA2007/JPS1 Block store secondary */
2165 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2166 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2168 helper_raise_exception(env, TT_ILL_INSN);
2171 helper_check_align(env, addr, 0x3f);
2172 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2173 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, 8);
2177 case 0x16: /* UA2007 Block load primary, user privilege */
2178 case 0x17: /* UA2007 Block load secondary, user privilege */
2179 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2180 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2181 case 0x70: /* JPS1 Block store primary, user privilege */
2182 case 0x71: /* JPS1 Block store secondary, user privilege */
2183 case 0x78: /* JPS1 Block load primary LE, user privilege */
2184 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2186 helper_raise_exception(env, TT_ILL_INSN);
2189 helper_check_align(env, addr, 0x3f);
2190 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2191 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8);
2195 case 0xd2: /* 16-bit floating point load primary */
2196 case 0xd3: /* 16-bit floating point load secondary */
2197 case 0xda: /* 16-bit floating point load primary, LE */
2198 case 0xdb: /* 16-bit floating point load secondary, LE */
2199 helper_check_align(env, addr, 1);
2201 case 0xd0: /* 8-bit floating point load primary */
2202 case 0xd1: /* 8-bit floating point load secondary */
2203 case 0xd8: /* 8-bit floating point load primary, LE */
2204 case 0xd9: /* 8-bit floating point load secondary, LE */
2205 val = env->fpr[rd / 2].l.lower;
2206 helper_st_asi(env, addr, val, asi & 0x8d, ((asi & 2) >> 1) + 1);
2209 helper_check_align(env, addr, 3);
2217 val = env->fpr[rd / 2].l.lower;
2219 val = env->fpr[rd / 2].l.upper;
2221 helper_st_asi(env, addr, val, asi, size);
2224 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, size);
2227 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, 8);
2228 helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, 8);
2233 target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
2234 target_ulong val1, target_ulong val2,
2239 ret = helper_ld_asi(env, addr, asi, 8, 0);
2241 helper_st_asi(env, addr, val1, asi, 8);
2245 #endif /* TARGET_SPARC64 */
2247 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2248 target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
2249 target_ulong val1, target_ulong val2, uint32_t asi)
2253 val2 &= 0xffffffffUL;
2254 ret = helper_ld_asi(env, addr, asi, 4, 0);
2255 ret &= 0xffffffffUL;
2257 helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
2261 #endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */
2263 void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2265 /* XXX add 128 bit load */
2268 helper_check_align(env, addr, 7);
2269 #if !defined(CONFIG_USER_ONLY)
2272 u.ll.upper = cpu_ldq_user(env, addr);
2273 u.ll.lower = cpu_ldq_user(env, addr + 8);
2276 case MMU_KERNEL_IDX:
2277 u.ll.upper = cpu_ldq_kernel(env, addr);
2278 u.ll.lower = cpu_ldq_kernel(env, addr + 8);
2281 #ifdef TARGET_SPARC64
2283 u.ll.upper = cpu_ldq_hypv(env, addr);
2284 u.ll.lower = cpu_ldq_hypv(env, addr + 8);
2289 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
2293 u.ll.upper = cpu_ldq_data(env, address_mask(env, addr));
2294 u.ll.lower = cpu_ldq_data(env, address_mask(env, addr + 8));
2299 void helper_stqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2301 /* XXX add 128 bit store */
2304 helper_check_align(env, addr, 7);
2305 #if !defined(CONFIG_USER_ONLY)
2309 cpu_stq_user(env, addr, u.ll.upper);
2310 cpu_stq_user(env, addr + 8, u.ll.lower);
2312 case MMU_KERNEL_IDX:
2314 cpu_stq_kernel(env, addr, u.ll.upper);
2315 cpu_stq_kernel(env, addr + 8, u.ll.lower);
2317 #ifdef TARGET_SPARC64
2320 cpu_stq_hypv(env, addr, u.ll.upper);
2321 cpu_stq_hypv(env, addr + 8, u.ll.lower);
2325 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
2330 cpu_stq_data(env, address_mask(env, addr), u.ll.upper);
2331 cpu_stq_data(env, address_mask(env, addr + 8), u.ll.lower);
2335 #if !defined(CONFIG_USER_ONLY)
2336 #ifndef TARGET_SPARC64
2337 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2338 bool is_write, bool is_exec, int is_asi,
2341 SPARCCPU *cpu = SPARC_CPU(cs);
2342 CPUSPARCState *env = &cpu->env;
2345 #ifdef DEBUG_UNASSIGNED
2347 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2348 " asi 0x%02x from " TARGET_FMT_lx "\n",
2349 is_exec ? "exec" : is_write ? "write" : "read", size,
2350 size == 1 ? "" : "s", addr, is_asi, env->pc);
2352 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2353 " from " TARGET_FMT_lx "\n",
2354 is_exec ? "exec" : is_write ? "write" : "read", size,
2355 size == 1 ? "" : "s", addr, env->pc);
2358 /* Don't overwrite translation and access faults */
2359 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
2360 if ((fault_type > 4) || (fault_type == 0)) {
2361 env->mmuregs[3] = 0; /* Fault status register */
2363 env->mmuregs[3] |= 1 << 16;
2366 env->mmuregs[3] |= 1 << 5;
2369 env->mmuregs[3] |= 1 << 6;
2372 env->mmuregs[3] |= 1 << 7;
2374 env->mmuregs[3] |= (5 << 2) | 2;
2375 /* SuperSPARC will never place instruction fault addresses in the FAR */
2377 env->mmuregs[4] = addr; /* Fault address register */
2380 /* overflow (same type fault was not read before another fault) */
2381 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
2382 env->mmuregs[3] |= 1;
2385 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2387 helper_raise_exception(env, TT_CODE_ACCESS);
2389 helper_raise_exception(env, TT_DATA_ACCESS);
2393 /* flush neverland mappings created during no-fault mode,
2394 so the sequential MMU faults report proper fault types */
2395 if (env->mmuregs[0] & MMU_NF) {
2400 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2401 bool is_write, bool is_exec, int is_asi,
2404 SPARCCPU *cpu = SPARC_CPU(cs);
2405 CPUSPARCState *env = &cpu->env;
2407 #ifdef DEBUG_UNASSIGNED
2408 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2409 "\n", addr, env->pc);
2413 helper_raise_exception(env, TT_CODE_ACCESS);
2415 helper_raise_exception(env, TT_DATA_ACCESS);
2421 #if !defined(CONFIG_USER_ONLY)
2422 void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs,
2423 vaddr addr, int is_write,
2424 int is_user, uintptr_t retaddr)
2426 SPARCCPU *cpu = SPARC_CPU(cs);
2427 CPUSPARCState *env = &cpu->env;
2429 #ifdef DEBUG_UNALIGNED
2430 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2431 "\n", addr, env->pc);
2434 cpu_restore_state(CPU(cpu), retaddr);
2436 helper_raise_exception(env, TT_UNALIGNED);
2439 /* try to fill the TLB and return an exception if error. If retaddr is
2440 NULL, it means that the function was called in C code (i.e. not
2441 from generated code or from helper.c) */
2442 /* XXX: fix it to restore all registers */
2443 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2448 ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2451 cpu_restore_state(cs, retaddr);