4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "exec/helper-proto.h"
22 #include "exec/cpu_ldst.h"
24 #ifndef CONFIG_USER_ONLY
26 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
31 ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
33 /* now we have a real cpu fault */
35 cpu_restore_state(cs, retaddr);
43 void helper_ldtlb(CPUSH4State *env)
45 #ifdef CONFIG_USER_ONLY
46 SuperHCPU *cpu = sh_env_get_cpu(env);
49 cpu_abort(CPU(cpu), "Unhandled ldtlb");
55 static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
58 CPUState *cs = CPU(sh_env_get_cpu(env));
60 cs->exception_index = index;
62 cpu_restore_state(cs, retaddr);
67 void helper_raise_illegal_instruction(CPUSH4State *env)
69 raise_exception(env, 0x180, 0);
72 void helper_raise_slot_illegal_instruction(CPUSH4State *env)
74 raise_exception(env, 0x1a0, 0);
77 void helper_raise_fpu_disable(CPUSH4State *env)
79 raise_exception(env, 0x800, 0);
82 void helper_raise_slot_fpu_disable(CPUSH4State *env)
84 raise_exception(env, 0x820, 0);
87 void helper_debug(CPUSH4State *env)
89 raise_exception(env, EXCP_DEBUG, 0);
92 void helper_sleep(CPUSH4State *env)
94 CPUState *cs = CPU(sh_env_get_cpu(env));
98 raise_exception(env, EXCP_HLT, 0);
101 void helper_trapa(CPUSH4State *env, uint32_t tra)
104 raise_exception(env, 0x160, 0);
107 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
109 if (cpu_sh4_is_cached (env, address))
111 memory_content *r = malloc (sizeof(memory_content));
112 r->address = address;
116 *(env->movcal_backup_tail) = r;
117 env->movcal_backup_tail = &(r->next);
121 void helper_discard_movcal_backup(CPUSH4State *env)
123 memory_content *current = env->movcal_backup;
127 memory_content *next = current->next;
129 env->movcal_backup = current = next;
131 env->movcal_backup_tail = &(env->movcal_backup);
135 void helper_ocbi(CPUSH4State *env, uint32_t address)
137 memory_content **current = &(env->movcal_backup);
140 uint32_t a = (*current)->address;
141 if ((a & ~0x1F) == (address & ~0x1F))
143 memory_content *next = (*current)->next;
144 cpu_stl_data(env, a, (*current)->value);
148 env->movcal_backup_tail = current;
158 void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
162 res = ((uint64_t) env->mach << 32) | env->macl;
163 res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
164 env->mach = (res >> 32) & 0xffffffff;
165 env->macl = res & 0xffffffff;
166 if (env->sr & (1u << SR_S)) {
168 env->mach |= 0xffff0000;
170 env->mach &= 0x00007fff;
174 void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
178 res = ((uint64_t) env->mach << 32) | env->macl;
179 res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
180 env->mach = (res >> 32) & 0xffffffff;
181 env->macl = res & 0xffffffff;
182 if (env->sr & (1u << SR_S)) {
183 if (res < -0x80000000) {
185 env->macl = 0x80000000;
186 } else if (res > 0x000000007fffffff) {
188 env->macl = 0x7fffffff;
193 void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
195 env->fpscr = val & FPSCR_MASK;
196 if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
197 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
199 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
201 set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
204 static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
206 int xcpt, cause, enable;
208 xcpt = get_float_exception_flags(&env->fp_status);
210 /* Clear the flag entries */
211 env->fpscr &= ~FPSCR_FLAG_MASK;
213 if (unlikely(xcpt)) {
214 if (xcpt & float_flag_invalid) {
215 env->fpscr |= FPSCR_FLAG_V;
217 if (xcpt & float_flag_divbyzero) {
218 env->fpscr |= FPSCR_FLAG_Z;
220 if (xcpt & float_flag_overflow) {
221 env->fpscr |= FPSCR_FLAG_O;
223 if (xcpt & float_flag_underflow) {
224 env->fpscr |= FPSCR_FLAG_U;
226 if (xcpt & float_flag_inexact) {
227 env->fpscr |= FPSCR_FLAG_I;
230 /* Accumulate in cause entries */
231 env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
232 << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
234 /* Generate an exception if enabled */
235 cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
236 enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
237 if (cause & enable) {
238 raise_exception(env, 0x120, retaddr);
243 float32 helper_fabs_FT(float32 t0)
245 return float32_abs(t0);
248 float64 helper_fabs_DT(float64 t0)
250 return float64_abs(t0);
253 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
255 set_float_exception_flags(0, &env->fp_status);
256 t0 = float32_add(t0, t1, &env->fp_status);
257 update_fpscr(env, GETPC());
261 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
263 set_float_exception_flags(0, &env->fp_status);
264 t0 = float64_add(t0, t1, &env->fp_status);
265 update_fpscr(env, GETPC());
269 void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
273 set_float_exception_flags(0, &env->fp_status);
274 relation = float32_compare(t0, t1, &env->fp_status);
275 if (unlikely(relation == float_relation_unordered)) {
276 update_fpscr(env, GETPC());
278 env->sr_t = (relation == float_relation_equal);
282 void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
286 set_float_exception_flags(0, &env->fp_status);
287 relation = float64_compare(t0, t1, &env->fp_status);
288 if (unlikely(relation == float_relation_unordered)) {
289 update_fpscr(env, GETPC());
291 env->sr_t = (relation == float_relation_equal);
295 void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
299 set_float_exception_flags(0, &env->fp_status);
300 relation = float32_compare(t0, t1, &env->fp_status);
301 if (unlikely(relation == float_relation_unordered)) {
302 update_fpscr(env, GETPC());
304 env->sr_t = (relation == float_relation_greater);
308 void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
312 set_float_exception_flags(0, &env->fp_status);
313 relation = float64_compare(t0, t1, &env->fp_status);
314 if (unlikely(relation == float_relation_unordered)) {
315 update_fpscr(env, GETPC());
317 env->sr_t = (relation == float_relation_greater);
321 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
324 set_float_exception_flags(0, &env->fp_status);
325 ret = float32_to_float64(t0, &env->fp_status);
326 update_fpscr(env, GETPC());
330 float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
333 set_float_exception_flags(0, &env->fp_status);
334 ret = float64_to_float32(t0, &env->fp_status);
335 update_fpscr(env, GETPC());
339 float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
341 set_float_exception_flags(0, &env->fp_status);
342 t0 = float32_div(t0, t1, &env->fp_status);
343 update_fpscr(env, GETPC());
347 float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
349 set_float_exception_flags(0, &env->fp_status);
350 t0 = float64_div(t0, t1, &env->fp_status);
351 update_fpscr(env, GETPC());
355 float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
358 set_float_exception_flags(0, &env->fp_status);
359 ret = int32_to_float32(t0, &env->fp_status);
360 update_fpscr(env, GETPC());
364 float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
367 set_float_exception_flags(0, &env->fp_status);
368 ret = int32_to_float64(t0, &env->fp_status);
369 update_fpscr(env, GETPC());
373 float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
375 set_float_exception_flags(0, &env->fp_status);
376 t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
377 update_fpscr(env, GETPC());
381 float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
383 set_float_exception_flags(0, &env->fp_status);
384 t0 = float32_mul(t0, t1, &env->fp_status);
385 update_fpscr(env, GETPC());
389 float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
391 set_float_exception_flags(0, &env->fp_status);
392 t0 = float64_mul(t0, t1, &env->fp_status);
393 update_fpscr(env, GETPC());
397 float32 helper_fneg_T(float32 t0)
399 return float32_chs(t0);
402 float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
404 set_float_exception_flags(0, &env->fp_status);
405 t0 = float32_sqrt(t0, &env->fp_status);
406 update_fpscr(env, GETPC());
410 float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
412 set_float_exception_flags(0, &env->fp_status);
413 t0 = float64_sqrt(t0, &env->fp_status);
414 update_fpscr(env, GETPC());
418 float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
420 set_float_exception_flags(0, &env->fp_status);
421 t0 = float32_sub(t0, t1, &env->fp_status);
422 update_fpscr(env, GETPC());
426 float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
428 set_float_exception_flags(0, &env->fp_status);
429 t0 = float64_sub(t0, t1, &env->fp_status);
430 update_fpscr(env, GETPC());
434 uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
437 set_float_exception_flags(0, &env->fp_status);
438 ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
439 update_fpscr(env, GETPC());
443 uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
446 set_float_exception_flags(0, &env->fp_status);
447 ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
448 update_fpscr(env, GETPC());
452 void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
457 bank = (env->sr & FPSCR_FR) ? 16 : 0;
459 set_float_exception_flags(0, &env->fp_status);
461 for (i = 0 ; i < 4 ; i++) {
462 p = float32_mul(env->fregs[bank + m + i],
463 env->fregs[bank + n + i],
465 r = float32_add(r, p, &env->fp_status);
467 update_fpscr(env, GETPC());
469 env->fregs[bank + n + 3] = r;
472 void helper_ftrv(CPUSH4State *env, uint32_t n)
474 int bank_matrix, bank_vector;
479 bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
480 bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
481 set_float_exception_flags(0, &env->fp_status);
482 for (i = 0 ; i < 4 ; i++) {
484 for (j = 0 ; j < 4 ; j++) {
485 p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
486 env->fregs[bank_vector + j],
488 r[i] = float32_add(r[i], p, &env->fp_status);
491 update_fpscr(env, GETPC());
493 for (i = 0 ; i < 4 ; i++) {
494 env->fregs[bank_vector + i] = r[i];