2 * I/O instructions for S/390
4 * Copyright 2012, 2015 IBM Corp.
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
8 * your option) any later version. See the COPYING file in the top-level
12 #include <sys/types.h>
17 #include "hw/s390x/s390-pci-bus.h"
19 int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
22 if (!IOINST_SCHID_ONE(value)) {
25 if (!IOINST_SCHID_M(value)) {
26 if (IOINST_SCHID_CSSID(value)) {
32 *cssid = IOINST_SCHID_CSSID(value);
35 *ssid = IOINST_SCHID_SSID(value);
36 *schid = IOINST_SCHID_NR(value);
40 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1)
42 int cssid, ssid, schid, m;
47 if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
48 program_interrupt(&cpu->env, PGM_OPERAND, 2);
51 trace_ioinst_sch_id("xsch", cssid, ssid, schid);
52 sch = css_find_subch(m, cssid, ssid, schid);
53 if (sch && css_subch_visible(sch)) {
54 ret = css_do_xsch(sch);
73 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1)
75 int cssid, ssid, schid, m;
80 if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
81 program_interrupt(&cpu->env, PGM_OPERAND, 2);
84 trace_ioinst_sch_id("csch", cssid, ssid, schid);
85 sch = css_find_subch(m, cssid, ssid, schid);
86 if (sch && css_subch_visible(sch)) {
87 ret = css_do_csch(sch);
97 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1)
99 int cssid, ssid, schid, m;
104 if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
105 program_interrupt(&cpu->env, PGM_OPERAND, 2);
108 trace_ioinst_sch_id("hsch", cssid, ssid, schid);
109 sch = css_find_subch(m, cssid, ssid, schid);
110 if (sch && css_subch_visible(sch)) {
111 ret = css_do_hsch(sch);
130 static int ioinst_schib_valid(SCHIB *schib)
132 if ((be16_to_cpu(schib->pmcw.flags) & PMCW_FLAGS_MASK_INVALID) ||
133 (be32_to_cpu(schib->pmcw.chars) & PMCW_CHARS_MASK_INVALID)) {
136 /* Disallow extended measurements for now. */
137 if (be32_to_cpu(schib->pmcw.chars) & PMCW_CHARS_MASK_XMWME) {
143 void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
145 int cssid, ssid, schid, m;
151 CPUS390XState *env = &cpu->env;
154 addr = decode_basedisp_s(env, ipb, &ar);
156 program_interrupt(env, PGM_SPECIFICATION, 2);
159 if (s390_cpu_virt_mem_read(cpu, addr, ar, &schib, sizeof(schib))) {
162 if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid) ||
163 !ioinst_schib_valid(&schib)) {
164 program_interrupt(env, PGM_OPERAND, 2);
167 trace_ioinst_sch_id("msch", cssid, ssid, schid);
168 sch = css_find_subch(m, cssid, ssid, schid);
169 if (sch && css_subch_visible(sch)) {
170 ret = css_do_msch(sch, &schib);
189 static void copy_orb_from_guest(ORB *dest, const ORB *src)
191 dest->intparm = be32_to_cpu(src->intparm);
192 dest->ctrl0 = be16_to_cpu(src->ctrl0);
193 dest->lpm = src->lpm;
194 dest->ctrl1 = src->ctrl1;
195 dest->cpa = be32_to_cpu(src->cpa);
198 static int ioinst_orb_valid(ORB *orb)
200 if ((orb->ctrl0 & ORB_CTRL0_MASK_INVALID) ||
201 (orb->ctrl1 & ORB_CTRL1_MASK_INVALID)) {
204 if ((orb->cpa & HIGH_ORDER_BIT) != 0) {
210 void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
212 int cssid, ssid, schid, m;
218 CPUS390XState *env = &cpu->env;
221 addr = decode_basedisp_s(env, ipb, &ar);
223 program_interrupt(env, PGM_SPECIFICATION, 2);
226 if (s390_cpu_virt_mem_read(cpu, addr, ar, &orig_orb, sizeof(orb))) {
229 copy_orb_from_guest(&orb, &orig_orb);
230 if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid) ||
231 !ioinst_orb_valid(&orb)) {
232 program_interrupt(env, PGM_OPERAND, 2);
235 trace_ioinst_sch_id("ssch", cssid, ssid, schid);
236 sch = css_find_subch(m, cssid, ssid, schid);
237 if (sch && css_subch_visible(sch)) {
238 ret = css_do_ssch(sch, &orb);
257 void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb)
262 CPUS390XState *env = &cpu->env;
265 addr = decode_basedisp_s(env, ipb, &ar);
267 program_interrupt(env, PGM_SPECIFICATION, 2);
271 cc = css_do_stcrw(&crw);
272 /* 0 - crw stored, 1 - zeroes stored */
274 if (s390_cpu_virt_mem_write(cpu, addr, ar, &crw, sizeof(crw)) == 0) {
276 } else if (cc == 0) {
277 /* Write failed: requeue CRW since STCRW is a suppressing instruction */
278 css_undo_stcrw(&crw);
282 void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
284 int cssid, ssid, schid, m;
289 CPUS390XState *env = &cpu->env;
292 addr = decode_basedisp_s(env, ipb, &ar);
294 program_interrupt(env, PGM_SPECIFICATION, 2);
298 if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
300 * As operand exceptions have a lower priority than access exceptions,
301 * we check whether the memory area is writeable (injecting the
302 * access execption if it is not) first.
304 if (!s390_cpu_virt_mem_check_write(cpu, addr, ar, sizeof(schib))) {
305 program_interrupt(env, PGM_OPERAND, 2);
309 trace_ioinst_sch_id("stsch", cssid, ssid, schid);
310 sch = css_find_subch(m, cssid, ssid, schid);
312 if (css_subch_visible(sch)) {
313 css_do_stsch(sch, &schib);
316 /* Indicate no more subchannels in this css/ss */
320 if (css_schid_final(m, cssid, ssid, schid)) {
321 cc = 3; /* No more subchannels in this css/ss */
323 /* Store an empty schib. */
324 memset(&schib, 0, sizeof(schib));
329 if (s390_cpu_virt_mem_write(cpu, addr, ar, &schib,
330 sizeof(schib)) != 0) {
334 /* Access exceptions have a higher priority than cc3 */
335 if (s390_cpu_virt_mem_check_write(cpu, addr, ar, sizeof(schib)) != 0) {
342 int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
344 CPUS390XState *env = &cpu->env;
345 int cssid, ssid, schid, m;
352 if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
353 program_interrupt(env, PGM_OPERAND, 2);
356 trace_ioinst_sch_id("tsch", cssid, ssid, schid);
357 addr = decode_basedisp_s(env, ipb, &ar);
359 program_interrupt(env, PGM_SPECIFICATION, 2);
363 sch = css_find_subch(m, cssid, ssid, schid);
364 if (sch && css_subch_visible(sch)) {
365 cc = css_do_tsch_get_irb(sch, &irb, &irb_len);
369 /* 0 - status pending, 1 - not status pending, 3 - not operational */
371 if (s390_cpu_virt_mem_write(cpu, addr, ar, &irb, irb_len) != 0) {
374 css_do_tsch_update_subch(sch);
376 irb_len = sizeof(irb) - sizeof(irb.emw);
377 /* Access exceptions have a higher priority than cc3 */
378 if (s390_cpu_virt_mem_check_write(cpu, addr, ar, irb_len) != 0) {
387 typedef struct ChscReq {
393 } QEMU_PACKED ChscReq;
395 typedef struct ChscResp {
400 } QEMU_PACKED ChscResp;
402 #define CHSC_MIN_RESP_LEN 0x0008
404 #define CHSC_SCPD 0x0002
405 #define CHSC_SCSC 0x0010
406 #define CHSC_SDA 0x0031
407 #define CHSC_SEI 0x000e
409 #define CHSC_SCPD_0_M 0x20000000
410 #define CHSC_SCPD_0_C 0x10000000
411 #define CHSC_SCPD_0_FMT 0x0f000000
412 #define CHSC_SCPD_0_CSSID 0x00ff0000
413 #define CHSC_SCPD_0_RFMT 0x00000f00
414 #define CHSC_SCPD_0_RES 0xc000f000
415 #define CHSC_SCPD_1_RES 0xffffff00
416 #define CHSC_SCPD_01_CHPID 0x000000ff
417 static void ioinst_handle_chsc_scpd(ChscReq *req, ChscResp *res)
419 uint16_t len = be16_to_cpu(req->len);
420 uint32_t param0 = be32_to_cpu(req->param0);
421 uint32_t param1 = be32_to_cpu(req->param1);
425 uint8_t f_chpid, l_chpid;
429 rfmt = (param0 & CHSC_SCPD_0_RFMT) >> 8;
430 if ((rfmt == 0) || (rfmt == 1)) {
431 rfmt = !!(param0 & CHSC_SCPD_0_C);
433 if ((len != 0x0010) || (param0 & CHSC_SCPD_0_RES) ||
434 (param1 & CHSC_SCPD_1_RES) || req->param2) {
438 if (param0 & CHSC_SCPD_0_FMT) {
442 cssid = (param0 & CHSC_SCPD_0_CSSID) >> 16;
443 m = param0 & CHSC_SCPD_0_M;
445 if (!m || !css_present(cssid)) {
450 f_chpid = param0 & CHSC_SCPD_01_CHPID;
451 l_chpid = param1 & CHSC_SCPD_01_CHPID;
452 if (l_chpid < f_chpid) {
456 /* css_collect_chp_desc() is endian-aware */
457 desc_size = css_collect_chp_desc(m, cssid, f_chpid, l_chpid, rfmt,
459 res->code = cpu_to_be16(0x0001);
460 res->len = cpu_to_be16(8 + desc_size);
461 res->param = cpu_to_be32(rfmt);
465 res->code = cpu_to_be16(resp_code);
466 res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
467 res->param = cpu_to_be32(rfmt);
470 #define CHSC_SCSC_0_M 0x20000000
471 #define CHSC_SCSC_0_FMT 0x000f0000
472 #define CHSC_SCSC_0_CSSID 0x0000ff00
473 #define CHSC_SCSC_0_RES 0xdff000ff
474 static void ioinst_handle_chsc_scsc(ChscReq *req, ChscResp *res)
476 uint16_t len = be16_to_cpu(req->len);
477 uint32_t param0 = be32_to_cpu(req->param0);
480 uint32_t general_chars[510];
481 uint32_t chsc_chars[508];
488 if (param0 & CHSC_SCSC_0_FMT) {
492 cssid = (param0 & CHSC_SCSC_0_CSSID) >> 8;
494 if (!(param0 & CHSC_SCSC_0_M) || !css_present(cssid)) {
499 if ((param0 & CHSC_SCSC_0_RES) || req->param1 || req->param2) {
503 res->code = cpu_to_be16(0x0001);
504 res->len = cpu_to_be16(4080);
507 memset(general_chars, 0, sizeof(general_chars));
508 memset(chsc_chars, 0, sizeof(chsc_chars));
510 general_chars[0] = cpu_to_be32(0x03000000);
511 general_chars[1] = cpu_to_be32(0x00059000);
513 chsc_chars[0] = cpu_to_be32(0x40000000);
514 chsc_chars[3] = cpu_to_be32(0x00040000);
516 memcpy(res->data, general_chars, sizeof(general_chars));
517 memcpy(res->data + sizeof(general_chars), chsc_chars, sizeof(chsc_chars));
521 res->code = cpu_to_be16(resp_code);
522 res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
526 #define CHSC_SDA_0_FMT 0x0f000000
527 #define CHSC_SDA_0_OC 0x0000ffff
528 #define CHSC_SDA_0_RES 0xf0ff0000
529 #define CHSC_SDA_OC_MCSSE 0x0
530 #define CHSC_SDA_OC_MSS 0x2
531 static void ioinst_handle_chsc_sda(ChscReq *req, ChscResp *res)
533 uint16_t resp_code = 0x0001;
534 uint16_t len = be16_to_cpu(req->len);
535 uint32_t param0 = be32_to_cpu(req->param0);
539 if ((len != 0x0400) || (param0 & CHSC_SDA_0_RES)) {
544 if (param0 & CHSC_SDA_0_FMT) {
549 oc = param0 & CHSC_SDA_0_OC;
551 case CHSC_SDA_OC_MCSSE:
552 ret = css_enable_mcsse();
553 if (ret == -EINVAL) {
558 case CHSC_SDA_OC_MSS:
559 ret = css_enable_mss();
560 if (ret == -EINVAL) {
571 res->code = cpu_to_be16(resp_code);
572 res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
576 static int chsc_sei_nt0_get_event(void *res)
582 static int chsc_sei_nt0_have_event(void)
588 #define CHSC_SEI_NT0 (1ULL << 63)
589 #define CHSC_SEI_NT2 (1ULL << 61)
590 static void ioinst_handle_chsc_sei(ChscReq *req, ChscResp *res)
592 uint64_t selection_mask = ldq_p(&req->param1);
593 uint8_t *res_flags = (uint8_t *)res->data;
597 /* regarding architecture nt0 can not be masked */
598 have_event = !chsc_sei_nt0_get_event(res);
599 have_more = chsc_sei_nt0_have_event();
601 if (selection_mask & CHSC_SEI_NT2) {
603 have_event = !chsc_sei_nt2_get_event(res);
607 have_more = chsc_sei_nt2_have_event();
612 res->code = cpu_to_be16(0x0001);
614 (*res_flags) |= 0x80;
616 (*res_flags) &= ~0x80;
619 res->code = cpu_to_be16(0x0004);
623 static void ioinst_handle_chsc_unimplemented(ChscResp *res)
625 res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
626 res->code = cpu_to_be16(0x0004);
630 void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb)
638 CPUS390XState *env = &cpu->env;
639 uint8_t buf[TARGET_PAGE_SIZE];
641 trace_ioinst("chsc");
642 reg = (ipb >> 20) & 0x00f;
643 addr = env->regs[reg];
646 program_interrupt(env, PGM_SPECIFICATION, 2);
650 * Reading sizeof(ChscReq) bytes is currently enough for all of our
651 * present CHSC sub-handlers ... if we ever need more, we should take
652 * care of req->len here first.
654 if (s390_cpu_virt_mem_read(cpu, addr, reg, buf, sizeof(ChscReq))) {
657 req = (ChscReq *)buf;
658 len = be16_to_cpu(req->len);
659 /* Length field valid? */
660 if ((len < 16) || (len > 4088) || (len & 7)) {
661 program_interrupt(env, PGM_OPERAND, 2);
664 memset((char *)req + len, 0, TARGET_PAGE_SIZE - len);
665 res = (void *)((char *)req + len);
666 command = be16_to_cpu(req->command);
667 trace_ioinst_chsc_cmd(command, len);
670 ioinst_handle_chsc_scsc(req, res);
673 ioinst_handle_chsc_scpd(req, res);
676 ioinst_handle_chsc_sda(req, res);
679 ioinst_handle_chsc_sei(req, res);
682 ioinst_handle_chsc_unimplemented(res);
686 if (!s390_cpu_virt_mem_write(cpu, addr + len, reg, res,
687 be16_to_cpu(res->len))) {
688 setcc(cpu, 0); /* Command execution complete */
692 int ioinst_handle_tpi(S390CPU *cpu, uint32_t ipb)
694 CPUS390XState *env = &cpu->env;
703 addr = decode_basedisp_s(env, ipb, &ar);
705 program_interrupt(env, PGM_SPECIFICATION, 2);
709 lowcore = addr ? 0 : 1;
710 len = lowcore ? 8 /* two words */ : 12 /* three words */;
711 ret = css_do_tpi(&int_code, lowcore);
713 s390_cpu_virt_mem_write(cpu, lowcore ? 184 : addr, ar, &int_code, len);
718 #define SCHM_REG1_RES(_reg) (_reg & 0x000000000ffffffc)
719 #define SCHM_REG1_MBK(_reg) ((_reg & 0x00000000f0000000) >> 28)
720 #define SCHM_REG1_UPD(_reg) ((_reg & 0x0000000000000002) >> 1)
721 #define SCHM_REG1_DCT(_reg) (_reg & 0x0000000000000001)
723 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
729 CPUS390XState *env = &cpu->env;
731 trace_ioinst("schm");
733 if (SCHM_REG1_RES(reg1)) {
734 program_interrupt(env, PGM_OPERAND, 2);
738 mbk = SCHM_REG1_MBK(reg1);
739 update = SCHM_REG1_UPD(reg1);
740 dct = SCHM_REG1_DCT(reg1);
742 if (update && (reg2 & 0x000000000000001f)) {
743 program_interrupt(env, PGM_OPERAND, 2);
747 css_do_schm(mbk, update, dct, update ? reg2 : 0);
750 void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1)
752 int cssid, ssid, schid, m;
757 if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
758 program_interrupt(&cpu->env, PGM_OPERAND, 2);
761 trace_ioinst_sch_id("rsch", cssid, ssid, schid);
762 sch = css_find_subch(m, cssid, ssid, schid);
763 if (sch && css_subch_visible(sch)) {
764 ret = css_do_rsch(sch);
783 #define RCHP_REG1_RES(_reg) (_reg & 0x00000000ff00ff00)
784 #define RCHP_REG1_CSSID(_reg) ((_reg & 0x0000000000ff0000) >> 16)
785 #define RCHP_REG1_CHPID(_reg) (_reg & 0x00000000000000ff)
786 void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1)
792 CPUS390XState *env = &cpu->env;
794 if (RCHP_REG1_RES(reg1)) {
795 program_interrupt(env, PGM_OPERAND, 2);
799 cssid = RCHP_REG1_CSSID(reg1);
800 chpid = RCHP_REG1_CHPID(reg1);
802 trace_ioinst_chp_id("rchp", cssid, chpid);
804 ret = css_do_rchp(cssid, chpid);
817 /* Invalid channel subsystem. */
818 program_interrupt(env, PGM_OPERAND, 2);
824 #define SAL_REG1_INVALID(_reg) (_reg & 0x0000000080000000)
825 void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1)
827 /* We do not provide address limit checking, so let's suppress it. */
828 if (SAL_REG1_INVALID(reg1) || reg1 & 0x000000000000ffff) {
829 program_interrupt(&cpu->env, PGM_OPERAND, 2);