2 * PowerPC floating point and SPE emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "exec/helper-proto.h"
23 #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
24 #define float32_snan_to_qnan(x) ((x) | 0x00400000)
26 /*****************************************************************************/
27 /* Floating point operations helpers */
28 uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg)
34 d.d = float32_to_float64(f.f, &env->fp_status);
38 uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg)
44 f.f = float64_to_float32(d.d, &env->fp_status);
48 static inline int isden(float64 d)
54 return ((u.ll >> 52) & 0x7FF) == 0;
57 static inline int ppc_float32_get_unbiased_exp(float32 f)
59 return ((f >> 23) & 0xFF) - 127;
62 static inline int ppc_float64_get_unbiased_exp(float64 f)
64 return ((f >> 52) & 0x7FF) - 1023;
67 void helper_compute_fprf(CPUPPCState *env, uint64_t arg)
74 isneg = float64_is_neg(farg.d);
75 if (unlikely(float64_is_any_nan(farg.d))) {
76 if (float64_is_signaling_nan(farg.d)) {
77 /* Signaling NaN: flags are undefined */
83 } else if (unlikely(float64_is_infinity(farg.d))) {
91 if (float64_is_zero(farg.d)) {
100 /* Denormalized numbers */
103 /* Normalized numbers */
113 /* We update FPSCR_FPRF */
114 env->fpscr &= ~(0x1F << FPSCR_FPRF);
115 env->fpscr |= fprf << FPSCR_FPRF;
118 /* Floating-point invalid operations exception */
119 static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op,
122 CPUState *cs = CPU(ppc_env_get_cpu(env));
128 case POWERPC_EXCP_FP_VXSNAN:
129 env->fpscr |= 1 << FPSCR_VXSNAN;
131 case POWERPC_EXCP_FP_VXSOFT:
132 env->fpscr |= 1 << FPSCR_VXSOFT;
134 case POWERPC_EXCP_FP_VXISI:
135 /* Magnitude subtraction of infinities */
136 env->fpscr |= 1 << FPSCR_VXISI;
138 case POWERPC_EXCP_FP_VXIDI:
139 /* Division of infinity by infinity */
140 env->fpscr |= 1 << FPSCR_VXIDI;
142 case POWERPC_EXCP_FP_VXZDZ:
143 /* Division of zero by zero */
144 env->fpscr |= 1 << FPSCR_VXZDZ;
146 case POWERPC_EXCP_FP_VXIMZ:
147 /* Multiplication of zero by infinity */
148 env->fpscr |= 1 << FPSCR_VXIMZ;
150 case POWERPC_EXCP_FP_VXVC:
151 /* Ordered comparison of NaN */
152 env->fpscr |= 1 << FPSCR_VXVC;
154 env->fpscr &= ~(0xF << FPSCR_FPCC);
155 env->fpscr |= 0x11 << FPSCR_FPCC;
157 /* We must update the target FPR before raising the exception */
159 cs->exception_index = POWERPC_EXCP_PROGRAM;
160 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
161 /* Update the floating-point enabled exception summary */
162 env->fpscr |= 1 << FPSCR_FEX;
163 /* Exception is differed */
167 case POWERPC_EXCP_FP_VXSQRT:
168 /* Square root of a negative number */
169 env->fpscr |= 1 << FPSCR_VXSQRT;
171 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
173 /* Set the result to quiet NaN */
174 ret = 0x7FF8000000000000ULL;
176 env->fpscr &= ~(0xF << FPSCR_FPCC);
177 env->fpscr |= 0x11 << FPSCR_FPCC;
181 case POWERPC_EXCP_FP_VXCVI:
182 /* Invalid conversion */
183 env->fpscr |= 1 << FPSCR_VXCVI;
184 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
186 /* Set the result to quiet NaN */
187 ret = 0x7FF8000000000000ULL;
189 env->fpscr &= ~(0xF << FPSCR_FPCC);
190 env->fpscr |= 0x11 << FPSCR_FPCC;
195 /* Update the floating-point invalid operation summary */
196 env->fpscr |= 1 << FPSCR_VX;
197 /* Update the floating-point exception summary */
200 /* Update the floating-point enabled exception summary */
201 env->fpscr |= 1 << FPSCR_FEX;
202 if (msr_fe0 != 0 || msr_fe1 != 0) {
203 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
204 POWERPC_EXCP_FP | op);
210 static inline void float_zero_divide_excp(CPUPPCState *env)
212 env->fpscr |= 1 << FPSCR_ZX;
213 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
214 /* Update the floating-point exception summary */
217 /* Update the floating-point enabled exception summary */
218 env->fpscr |= 1 << FPSCR_FEX;
219 if (msr_fe0 != 0 || msr_fe1 != 0) {
220 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
221 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
226 static inline void float_overflow_excp(CPUPPCState *env)
228 CPUState *cs = CPU(ppc_env_get_cpu(env));
230 env->fpscr |= 1 << FPSCR_OX;
231 /* Update the floating-point exception summary */
234 /* XXX: should adjust the result */
235 /* Update the floating-point enabled exception summary */
236 env->fpscr |= 1 << FPSCR_FEX;
237 /* We must update the target FPR before raising the exception */
238 cs->exception_index = POWERPC_EXCP_PROGRAM;
239 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
241 env->fpscr |= 1 << FPSCR_XX;
242 env->fpscr |= 1 << FPSCR_FI;
246 static inline void float_underflow_excp(CPUPPCState *env)
248 CPUState *cs = CPU(ppc_env_get_cpu(env));
250 env->fpscr |= 1 << FPSCR_UX;
251 /* Update the floating-point exception summary */
254 /* XXX: should adjust the result */
255 /* Update the floating-point enabled exception summary */
256 env->fpscr |= 1 << FPSCR_FEX;
257 /* We must update the target FPR before raising the exception */
258 cs->exception_index = POWERPC_EXCP_PROGRAM;
259 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
263 static inline void float_inexact_excp(CPUPPCState *env)
265 CPUState *cs = CPU(ppc_env_get_cpu(env));
267 env->fpscr |= 1 << FPSCR_XX;
268 /* Update the floating-point exception summary */
271 /* Update the floating-point enabled exception summary */
272 env->fpscr |= 1 << FPSCR_FEX;
273 /* We must update the target FPR before raising the exception */
274 cs->exception_index = POWERPC_EXCP_PROGRAM;
275 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
279 static inline void fpscr_set_rounding_mode(CPUPPCState *env)
283 /* Set rounding mode */
286 /* Best approximation (round to nearest) */
287 rnd_type = float_round_nearest_even;
290 /* Smaller magnitude (round toward zero) */
291 rnd_type = float_round_to_zero;
294 /* Round toward +infinite */
295 rnd_type = float_round_up;
299 /* Round toward -infinite */
300 rnd_type = float_round_down;
303 set_float_rounding_mode(rnd_type, &env->fp_status);
306 void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
310 prev = (env->fpscr >> bit) & 1;
311 env->fpscr &= ~(1 << bit);
316 fpscr_set_rounding_mode(env);
324 void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
326 CPUState *cs = CPU(ppc_env_get_cpu(env));
329 prev = (env->fpscr >> bit) & 1;
330 env->fpscr |= 1 << bit;
372 env->fpscr |= 1 << FPSCR_VX;
381 env->error_code = POWERPC_EXCP_FP;
383 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
386 env->error_code |= POWERPC_EXCP_FP_VXISI;
389 env->error_code |= POWERPC_EXCP_FP_VXIDI;
392 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
395 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
398 env->error_code |= POWERPC_EXCP_FP_VXVC;
401 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
404 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
407 env->error_code |= POWERPC_EXCP_FP_VXCVI;
415 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
422 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
429 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
436 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
442 fpscr_set_rounding_mode(env);
447 /* Update the floating-point enabled exception summary */
448 env->fpscr |= 1 << FPSCR_FEX;
449 /* We have to update Rc1 before raising the exception */
450 cs->exception_index = POWERPC_EXCP_PROGRAM;
456 void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
458 CPUState *cs = CPU(ppc_env_get_cpu(env));
459 target_ulong prev, new;
463 new = (target_ulong)arg;
464 new &= ~0x60000000LL;
465 new |= prev & 0x60000000LL;
466 for (i = 0; i < sizeof(target_ulong) * 2; i++) {
467 if (mask & (1 << i)) {
468 env->fpscr &= ~(0xFLL << (4 * i));
469 env->fpscr |= new & (0xFLL << (4 * i));
472 /* Update VX and FEX */
474 env->fpscr |= 1 << FPSCR_VX;
476 env->fpscr &= ~(1 << FPSCR_VX);
478 if ((fpscr_ex & fpscr_eex) != 0) {
479 env->fpscr |= 1 << FPSCR_FEX;
480 cs->exception_index = POWERPC_EXCP_PROGRAM;
481 /* XXX: we should compute it properly */
482 env->error_code = POWERPC_EXCP_FP;
484 env->fpscr &= ~(1 << FPSCR_FEX);
486 fpscr_set_rounding_mode(env);
489 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
491 helper_store_fpscr(env, arg, mask);
494 void helper_float_check_status(CPUPPCState *env)
496 CPUState *cs = CPU(ppc_env_get_cpu(env));
497 int status = get_float_exception_flags(&env->fp_status);
499 if (status & float_flag_divbyzero) {
500 float_zero_divide_excp(env);
501 } else if (status & float_flag_overflow) {
502 float_overflow_excp(env);
503 } else if (status & float_flag_underflow) {
504 float_underflow_excp(env);
505 } else if (status & float_flag_inexact) {
506 float_inexact_excp(env);
509 if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
510 (env->error_code & POWERPC_EXCP_FP)) {
511 /* Differred floating-point exception after target FPR update */
512 if (msr_fe0 != 0 || msr_fe1 != 0) {
513 helper_raise_exception_err(env, cs->exception_index,
519 void helper_reset_fpstatus(CPUPPCState *env)
521 set_float_exception_flags(0, &env->fp_status);
525 uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
527 CPU_DoubleU farg1, farg2;
532 if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
533 float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
534 /* Magnitude subtraction of infinities */
535 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
537 if (unlikely(float64_is_signaling_nan(farg1.d) ||
538 float64_is_signaling_nan(farg2.d))) {
540 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
542 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
549 uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
551 CPU_DoubleU farg1, farg2;
556 if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
557 float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
558 /* Magnitude subtraction of infinities */
559 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
561 if (unlikely(float64_is_signaling_nan(farg1.d) ||
562 float64_is_signaling_nan(farg2.d))) {
563 /* sNaN subtraction */
564 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
566 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
573 uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
575 CPU_DoubleU farg1, farg2;
580 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
581 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
582 /* Multiplication of zero by infinity */
583 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
585 if (unlikely(float64_is_signaling_nan(farg1.d) ||
586 float64_is_signaling_nan(farg2.d))) {
587 /* sNaN multiplication */
588 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
590 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
597 uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
599 CPU_DoubleU farg1, farg2;
604 if (unlikely(float64_is_infinity(farg1.d) &&
605 float64_is_infinity(farg2.d))) {
606 /* Division of infinity by infinity */
607 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1);
608 } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) {
609 /* Division of zero by zero */
610 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1);
612 if (unlikely(float64_is_signaling_nan(farg1.d) ||
613 float64_is_signaling_nan(farg2.d))) {
615 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
617 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
624 #define FPU_FCTI(op, cvt, nanval) \
625 uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
630 farg.ll = float64_to_##cvt(farg.d, &env->fp_status); \
632 if (unlikely(env->fp_status.float_exception_flags)) { \
633 if (float64_is_any_nan(arg)) { \
634 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
635 if (float64_is_signaling_nan(arg)) { \
636 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \
639 } else if (env->fp_status.float_exception_flags & \
640 float_flag_invalid) { \
641 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \
643 helper_float_check_status(env); \
648 FPU_FCTI(fctiw, int32, 0x80000000U)
649 FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
650 FPU_FCTI(fctiwu, uint32, 0x00000000U)
651 FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
652 FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
653 FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
654 FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
655 FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
657 #define FPU_FCFI(op, cvtr, is_single) \
658 uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
663 float32 tmp = cvtr(arg, &env->fp_status); \
664 farg.d = float32_to_float64(tmp, &env->fp_status); \
666 farg.d = cvtr(arg, &env->fp_status); \
668 helper_float_check_status(env); \
672 FPU_FCFI(fcfid, int64_to_float64, 0)
673 FPU_FCFI(fcfids, int64_to_float32, 1)
674 FPU_FCFI(fcfidu, uint64_to_float64, 0)
675 FPU_FCFI(fcfidus, uint64_to_float32, 1)
677 static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
684 if (unlikely(float64_is_signaling_nan(farg.d))) {
686 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
687 farg.ll = arg | 0x0008000000000000ULL;
689 int inexact = get_float_exception_flags(&env->fp_status) &
691 set_float_rounding_mode(rounding_mode, &env->fp_status);
692 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
693 /* Restore rounding mode from FPSCR */
694 fpscr_set_rounding_mode(env);
696 /* fri* does not set FPSCR[XX] */
698 env->fp_status.float_exception_flags &= ~float_flag_inexact;
701 helper_float_check_status(env);
705 uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
707 return do_fri(env, arg, float_round_ties_away);
710 uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
712 return do_fri(env, arg, float_round_to_zero);
715 uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
717 return do_fri(env, arg, float_round_up);
720 uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
722 return do_fri(env, arg, float_round_down);
726 uint64_t helper_fmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
729 CPU_DoubleU farg1, farg2, farg3;
735 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
736 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
737 /* Multiplication of zero by infinity */
738 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
740 if (unlikely(float64_is_signaling_nan(farg1.d) ||
741 float64_is_signaling_nan(farg2.d) ||
742 float64_is_signaling_nan(farg3.d))) {
744 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
746 /* This is the way the PowerPC specification defines it */
747 float128 ft0_128, ft1_128;
749 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
750 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
751 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
752 if (unlikely(float128_is_infinity(ft0_128) &&
753 float64_is_infinity(farg3.d) &&
754 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
755 /* Magnitude subtraction of infinities */
756 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
758 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
759 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
760 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
768 uint64_t helper_fmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
771 CPU_DoubleU farg1, farg2, farg3;
777 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
778 (float64_is_zero(farg1.d) &&
779 float64_is_infinity(farg2.d)))) {
780 /* Multiplication of zero by infinity */
781 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
783 if (unlikely(float64_is_signaling_nan(farg1.d) ||
784 float64_is_signaling_nan(farg2.d) ||
785 float64_is_signaling_nan(farg3.d))) {
787 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
789 /* This is the way the PowerPC specification defines it */
790 float128 ft0_128, ft1_128;
792 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
793 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
794 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
795 if (unlikely(float128_is_infinity(ft0_128) &&
796 float64_is_infinity(farg3.d) &&
797 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
798 /* Magnitude subtraction of infinities */
799 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
801 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
802 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
803 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
809 /* fnmadd - fnmadd. */
810 uint64_t helper_fnmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
813 CPU_DoubleU farg1, farg2, farg3;
819 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
820 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
821 /* Multiplication of zero by infinity */
822 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
824 if (unlikely(float64_is_signaling_nan(farg1.d) ||
825 float64_is_signaling_nan(farg2.d) ||
826 float64_is_signaling_nan(farg3.d))) {
828 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
830 /* This is the way the PowerPC specification defines it */
831 float128 ft0_128, ft1_128;
833 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
834 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
835 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
836 if (unlikely(float128_is_infinity(ft0_128) &&
837 float64_is_infinity(farg3.d) &&
838 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
839 /* Magnitude subtraction of infinities */
840 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
842 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
843 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
844 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
846 if (likely(!float64_is_any_nan(farg1.d))) {
847 farg1.d = float64_chs(farg1.d);
853 /* fnmsub - fnmsub. */
854 uint64_t helper_fnmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
857 CPU_DoubleU farg1, farg2, farg3;
863 if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
864 (float64_is_zero(farg1.d) &&
865 float64_is_infinity(farg2.d)))) {
866 /* Multiplication of zero by infinity */
867 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
869 if (unlikely(float64_is_signaling_nan(farg1.d) ||
870 float64_is_signaling_nan(farg2.d) ||
871 float64_is_signaling_nan(farg3.d))) {
873 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
875 /* This is the way the PowerPC specification defines it */
876 float128 ft0_128, ft1_128;
878 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
879 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
880 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
881 if (unlikely(float128_is_infinity(ft0_128) &&
882 float64_is_infinity(farg3.d) &&
883 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
884 /* Magnitude subtraction of infinities */
885 farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
887 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
888 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
889 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
891 if (likely(!float64_is_any_nan(farg1.d))) {
892 farg1.d = float64_chs(farg1.d);
899 uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
906 if (unlikely(float64_is_signaling_nan(farg.d))) {
907 /* sNaN square root */
908 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
910 f32 = float64_to_float32(farg.d, &env->fp_status);
911 farg.d = float32_to_float64(f32, &env->fp_status);
917 uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)
923 if (unlikely(float64_is_any_nan(farg.d))) {
924 if (unlikely(float64_is_signaling_nan(farg.d))) {
925 /* sNaN reciprocal square root */
926 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
927 farg.ll = float64_snan_to_qnan(farg.ll);
929 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
930 /* Square root of a negative nonzero number */
931 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
933 farg.d = float64_sqrt(farg.d, &env->fp_status);
939 uint64_t helper_fre(CPUPPCState *env, uint64_t arg)
945 if (unlikely(float64_is_signaling_nan(farg.d))) {
946 /* sNaN reciprocal */
947 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
949 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
954 uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
961 if (unlikely(float64_is_signaling_nan(farg.d))) {
962 /* sNaN reciprocal */
963 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
965 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
966 f32 = float64_to_float32(farg.d, &env->fp_status);
967 farg.d = float32_to_float64(f32, &env->fp_status);
972 /* frsqrte - frsqrte. */
973 uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg)
979 if (unlikely(float64_is_any_nan(farg.d))) {
980 if (unlikely(float64_is_signaling_nan(farg.d))) {
981 /* sNaN reciprocal square root */
982 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
983 farg.ll = float64_snan_to_qnan(farg.ll);
985 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
986 /* Reciprocal square root of a negative nonzero number */
987 farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
989 farg.d = float64_sqrt(farg.d, &env->fp_status);
990 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
997 uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1004 if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
1005 !float64_is_any_nan(farg1.d)) {
1012 uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
1017 if (unlikely(float64_is_infinity(fra) ||
1018 float64_is_infinity(frb) ||
1019 float64_is_zero(frb))) {
1023 int e_a = ppc_float64_get_unbiased_exp(fra);
1024 int e_b = ppc_float64_get_unbiased_exp(frb);
1026 if (unlikely(float64_is_any_nan(fra) ||
1027 float64_is_any_nan(frb))) {
1029 } else if ((e_b <= -1022) || (e_b >= 1021)) {
1031 } else if (!float64_is_zero(fra) &&
1032 (((e_a - e_b) >= 1023) ||
1033 ((e_a - e_b) <= -1021) ||
1038 if (unlikely(float64_is_zero_or_denormal(frb))) {
1039 /* XB is not zero because of the above check and */
1040 /* so must be denormalized. */
1045 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
1048 uint32_t helper_ftsqrt(uint64_t frb)
1053 if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
1057 int e_b = ppc_float64_get_unbiased_exp(frb);
1059 if (unlikely(float64_is_any_nan(frb))) {
1061 } else if (unlikely(float64_is_zero(frb))) {
1063 } else if (unlikely(float64_is_neg(frb))) {
1065 } else if (!float64_is_zero(frb) && (e_b <= (-1022+52))) {
1069 if (unlikely(float64_is_zero_or_denormal(frb))) {
1070 /* XB is not zero because of the above check and */
1071 /* therefore must be denormalized. */
1076 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
1079 void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1082 CPU_DoubleU farg1, farg2;
1088 if (unlikely(float64_is_any_nan(farg1.d) ||
1089 float64_is_any_nan(farg2.d))) {
1091 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1093 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1099 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1100 env->fpscr |= ret << FPSCR_FPRF;
1101 env->crf[crfD] = ret;
1102 if (unlikely(ret == 0x01UL
1103 && (float64_is_signaling_nan(farg1.d) ||
1104 float64_is_signaling_nan(farg2.d)))) {
1105 /* sNaN comparison */
1106 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
1110 void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1113 CPU_DoubleU farg1, farg2;
1119 if (unlikely(float64_is_any_nan(farg1.d) ||
1120 float64_is_any_nan(farg2.d))) {
1122 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1124 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1130 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1131 env->fpscr |= ret << FPSCR_FPRF;
1132 env->crf[crfD] = ret;
1133 if (unlikely(ret == 0x01UL)) {
1134 if (float64_is_signaling_nan(farg1.d) ||
1135 float64_is_signaling_nan(farg2.d)) {
1136 /* sNaN comparison */
1137 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
1138 POWERPC_EXCP_FP_VXVC, 1);
1140 /* qNaN comparison */
1141 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 1);
1146 /* Single-precision floating-point conversions */
1147 static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
1151 u.f = int32_to_float32(val, &env->vec_status);
1156 static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
1160 u.f = uint32_to_float32(val, &env->vec_status);
1165 static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
1170 /* NaN are not treated the same way IEEE 754 does */
1171 if (unlikely(float32_is_quiet_nan(u.f))) {
1175 return float32_to_int32(u.f, &env->vec_status);
1178 static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
1183 /* NaN are not treated the same way IEEE 754 does */
1184 if (unlikely(float32_is_quiet_nan(u.f))) {
1188 return float32_to_uint32(u.f, &env->vec_status);
1191 static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
1196 /* NaN are not treated the same way IEEE 754 does */
1197 if (unlikely(float32_is_quiet_nan(u.f))) {
1201 return float32_to_int32_round_to_zero(u.f, &env->vec_status);
1204 static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
1209 /* NaN are not treated the same way IEEE 754 does */
1210 if (unlikely(float32_is_quiet_nan(u.f))) {
1214 return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1217 static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
1222 u.f = int32_to_float32(val, &env->vec_status);
1223 tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1224 u.f = float32_div(u.f, tmp, &env->vec_status);
1229 static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
1234 u.f = uint32_to_float32(val, &env->vec_status);
1235 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1236 u.f = float32_div(u.f, tmp, &env->vec_status);
1241 static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
1247 /* NaN are not treated the same way IEEE 754 does */
1248 if (unlikely(float32_is_quiet_nan(u.f))) {
1251 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1252 u.f = float32_mul(u.f, tmp, &env->vec_status);
1254 return float32_to_int32(u.f, &env->vec_status);
1257 static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
1263 /* NaN are not treated the same way IEEE 754 does */
1264 if (unlikely(float32_is_quiet_nan(u.f))) {
1267 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1268 u.f = float32_mul(u.f, tmp, &env->vec_status);
1270 return float32_to_uint32(u.f, &env->vec_status);
1273 #define HELPER_SPE_SINGLE_CONV(name) \
1274 uint32_t helper_e##name(CPUPPCState *env, uint32_t val) \
1276 return e##name(env, val); \
1279 HELPER_SPE_SINGLE_CONV(fscfsi);
1281 HELPER_SPE_SINGLE_CONV(fscfui);
1283 HELPER_SPE_SINGLE_CONV(fscfuf);
1285 HELPER_SPE_SINGLE_CONV(fscfsf);
1287 HELPER_SPE_SINGLE_CONV(fsctsi);
1289 HELPER_SPE_SINGLE_CONV(fsctui);
1291 HELPER_SPE_SINGLE_CONV(fsctsiz);
1293 HELPER_SPE_SINGLE_CONV(fsctuiz);
1295 HELPER_SPE_SINGLE_CONV(fsctsf);
1297 HELPER_SPE_SINGLE_CONV(fsctuf);
1299 #define HELPER_SPE_VECTOR_CONV(name) \
1300 uint64_t helper_ev##name(CPUPPCState *env, uint64_t val) \
1302 return ((uint64_t)e##name(env, val >> 32) << 32) | \
1303 (uint64_t)e##name(env, val); \
1306 HELPER_SPE_VECTOR_CONV(fscfsi);
1308 HELPER_SPE_VECTOR_CONV(fscfui);
1310 HELPER_SPE_VECTOR_CONV(fscfuf);
1312 HELPER_SPE_VECTOR_CONV(fscfsf);
1314 HELPER_SPE_VECTOR_CONV(fsctsi);
1316 HELPER_SPE_VECTOR_CONV(fsctui);
1318 HELPER_SPE_VECTOR_CONV(fsctsiz);
1320 HELPER_SPE_VECTOR_CONV(fsctuiz);
1322 HELPER_SPE_VECTOR_CONV(fsctsf);
1324 HELPER_SPE_VECTOR_CONV(fsctuf);
1326 /* Single-precision floating-point arithmetic */
1327 static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
1333 u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1337 static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
1343 u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1347 static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
1353 u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1357 static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
1363 u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1367 #define HELPER_SPE_SINGLE_ARITH(name) \
1368 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1370 return e##name(env, op1, op2); \
1373 HELPER_SPE_SINGLE_ARITH(fsadd);
1375 HELPER_SPE_SINGLE_ARITH(fssub);
1377 HELPER_SPE_SINGLE_ARITH(fsmul);
1379 HELPER_SPE_SINGLE_ARITH(fsdiv);
1381 #define HELPER_SPE_VECTOR_ARITH(name) \
1382 uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1384 return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) | \
1385 (uint64_t)e##name(env, op1, op2); \
1388 HELPER_SPE_VECTOR_ARITH(fsadd);
1390 HELPER_SPE_VECTOR_ARITH(fssub);
1392 HELPER_SPE_VECTOR_ARITH(fsmul);
1394 HELPER_SPE_VECTOR_ARITH(fsdiv);
1396 /* Single-precision floating-point comparisons */
1397 static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1403 return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1406 static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1412 return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1415 static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1421 return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1424 static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1426 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1427 return efscmplt(env, op1, op2);
1430 static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1432 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1433 return efscmpgt(env, op1, op2);
1436 static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1438 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1439 return efscmpeq(env, op1, op2);
1442 #define HELPER_SINGLE_SPE_CMP(name) \
1443 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1445 return e##name(env, op1, op2) << 2; \
1448 HELPER_SINGLE_SPE_CMP(fststlt);
1450 HELPER_SINGLE_SPE_CMP(fststgt);
1452 HELPER_SINGLE_SPE_CMP(fststeq);
1454 HELPER_SINGLE_SPE_CMP(fscmplt);
1456 HELPER_SINGLE_SPE_CMP(fscmpgt);
1458 HELPER_SINGLE_SPE_CMP(fscmpeq);
1460 static inline uint32_t evcmp_merge(int t0, int t1)
1462 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1465 #define HELPER_VECTOR_SPE_CMP(name) \
1466 uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1468 return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32), \
1469 e##name(env, op1, op2)); \
1472 HELPER_VECTOR_SPE_CMP(fststlt);
1474 HELPER_VECTOR_SPE_CMP(fststgt);
1476 HELPER_VECTOR_SPE_CMP(fststeq);
1478 HELPER_VECTOR_SPE_CMP(fscmplt);
1480 HELPER_VECTOR_SPE_CMP(fscmpgt);
1482 HELPER_VECTOR_SPE_CMP(fscmpeq);
1484 /* Double-precision floating-point conversion */
1485 uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
1489 u.d = int32_to_float64(val, &env->vec_status);
1494 uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
1498 u.d = int64_to_float64(val, &env->vec_status);
1503 uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
1507 u.d = uint32_to_float64(val, &env->vec_status);
1512 uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
1516 u.d = uint64_to_float64(val, &env->vec_status);
1521 uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
1526 /* NaN are not treated the same way IEEE 754 does */
1527 if (unlikely(float64_is_any_nan(u.d))) {
1531 return float64_to_int32(u.d, &env->vec_status);
1534 uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
1539 /* NaN are not treated the same way IEEE 754 does */
1540 if (unlikely(float64_is_any_nan(u.d))) {
1544 return float64_to_uint32(u.d, &env->vec_status);
1547 uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
1552 /* NaN are not treated the same way IEEE 754 does */
1553 if (unlikely(float64_is_any_nan(u.d))) {
1557 return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1560 uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
1565 /* NaN are not treated the same way IEEE 754 does */
1566 if (unlikely(float64_is_any_nan(u.d))) {
1570 return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1573 uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
1578 /* NaN are not treated the same way IEEE 754 does */
1579 if (unlikely(float64_is_any_nan(u.d))) {
1583 return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1586 uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
1591 /* NaN are not treated the same way IEEE 754 does */
1592 if (unlikely(float64_is_any_nan(u.d))) {
1596 return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1599 uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
1604 u.d = int32_to_float64(val, &env->vec_status);
1605 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1606 u.d = float64_div(u.d, tmp, &env->vec_status);
1611 uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
1616 u.d = uint32_to_float64(val, &env->vec_status);
1617 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1618 u.d = float64_div(u.d, tmp, &env->vec_status);
1623 uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
1629 /* NaN are not treated the same way IEEE 754 does */
1630 if (unlikely(float64_is_any_nan(u.d))) {
1633 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1634 u.d = float64_mul(u.d, tmp, &env->vec_status);
1636 return float64_to_int32(u.d, &env->vec_status);
1639 uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
1645 /* NaN are not treated the same way IEEE 754 does */
1646 if (unlikely(float64_is_any_nan(u.d))) {
1649 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1650 u.d = float64_mul(u.d, tmp, &env->vec_status);
1652 return float64_to_uint32(u.d, &env->vec_status);
1655 uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
1661 u2.f = float64_to_float32(u1.d, &env->vec_status);
1666 uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
1672 u2.d = float32_to_float64(u1.f, &env->vec_status);
1677 /* Double precision fixed-point arithmetic */
1678 uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
1684 u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1688 uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
1694 u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1698 uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
1704 u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1708 uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
1714 u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1718 /* Double precision floating point helpers */
1719 uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1725 return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1728 uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1734 return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1737 uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1743 return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1746 uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1748 /* XXX: TODO: test special values (NaN, infinites, ...) */
1749 return helper_efdtstlt(env, op1, op2);
1752 uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1754 /* XXX: TODO: test special values (NaN, infinites, ...) */
1755 return helper_efdtstgt(env, op1, op2);
1758 uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1760 /* XXX: TODO: test special values (NaN, infinites, ...) */
1761 return helper_efdtsteq(env, op1, op2);
1764 #define DECODE_SPLIT(opcode, shift1, nb1, shift2, nb2) \
1765 (((((opcode) >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
1766 (((opcode) >> (shift2)) & ((1 << (nb2)) - 1)))
1768 #define xT(opcode) DECODE_SPLIT(opcode, 0, 1, 21, 5)
1769 #define xA(opcode) DECODE_SPLIT(opcode, 2, 1, 16, 5)
1770 #define xB(opcode) DECODE_SPLIT(opcode, 1, 1, 11, 5)
1771 #define xC(opcode) DECODE_SPLIT(opcode, 3, 1, 6, 5)
1772 #define BF(opcode) (((opcode) >> (31-8)) & 7)
1774 typedef union _ppc_vsr_t {
1781 #if defined(HOST_WORDS_BIGENDIAN)
1782 #define VsrW(i) u32[i]
1783 #define VsrD(i) u64[i]
1785 #define VsrW(i) u32[3-(i)]
1786 #define VsrD(i) u64[1-(i)]
1789 static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
1792 vsr->VsrD(0) = env->fpr[n];
1793 vsr->VsrD(1) = env->vsr[n];
1795 vsr->u64[0] = env->avr[n-32].u64[0];
1796 vsr->u64[1] = env->avr[n-32].u64[1];
1800 static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
1803 env->fpr[n] = vsr->VsrD(0);
1804 env->vsr[n] = vsr->VsrD(1);
1806 env->avr[n-32].u64[0] = vsr->u64[0];
1807 env->avr[n-32].u64[1] = vsr->u64[1];
1811 #define float64_to_float64(x, env) x
1814 /* VSX_ADD_SUB - VSX floating point add/subract
1815 * name - instruction mnemonic
1816 * op - operation (add or sub)
1817 * nels - number of elements (1, 2 or 4)
1818 * tp - type (float32 or float64)
1819 * fld - vsr_t field (VsrD(*) or VsrW(*))
1822 #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \
1823 void helper_##name(CPUPPCState *env, uint32_t opcode) \
1825 ppc_vsr_t xt, xa, xb; \
1828 getVSR(xA(opcode), &xa, env); \
1829 getVSR(xB(opcode), &xb, env); \
1830 getVSR(xT(opcode), &xt, env); \
1831 helper_reset_fpstatus(env); \
1833 for (i = 0; i < nels; i++) { \
1834 float_status tstat = env->fp_status; \
1835 set_float_exception_flags(0, &tstat); \
1836 xt.fld = tp##_##op(xa.fld, xb.fld, &tstat); \
1837 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1839 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1840 if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \
1841 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \
1842 } else if (tp##_is_signaling_nan(xa.fld) || \
1843 tp##_is_signaling_nan(xb.fld)) { \
1844 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
1849 xt.fld = helper_frsp(env, xt.fld); \
1853 helper_compute_fprf(env, xt.fld); \
1856 putVSR(xT(opcode), &xt, env); \
1857 helper_float_check_status(env); \
1860 VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0)
1861 VSX_ADD_SUB(xsaddsp, add, 1, float64, VsrD(0), 1, 1)
1862 VSX_ADD_SUB(xvadddp, add, 2, float64, VsrD(i), 0, 0)
1863 VSX_ADD_SUB(xvaddsp, add, 4, float32, VsrW(i), 0, 0)
1864 VSX_ADD_SUB(xssubdp, sub, 1, float64, VsrD(0), 1, 0)
1865 VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1)
1866 VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0)
1867 VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0)
1869 /* VSX_MUL - VSX floating point multiply
1870 * op - instruction mnemonic
1871 * nels - number of elements (1, 2 or 4)
1872 * tp - type (float32 or float64)
1873 * fld - vsr_t field (VsrD(*) or VsrW(*))
1876 #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) \
1877 void helper_##op(CPUPPCState *env, uint32_t opcode) \
1879 ppc_vsr_t xt, xa, xb; \
1882 getVSR(xA(opcode), &xa, env); \
1883 getVSR(xB(opcode), &xb, env); \
1884 getVSR(xT(opcode), &xt, env); \
1885 helper_reset_fpstatus(env); \
1887 for (i = 0; i < nels; i++) { \
1888 float_status tstat = env->fp_status; \
1889 set_float_exception_flags(0, &tstat); \
1890 xt.fld = tp##_mul(xa.fld, xb.fld, &tstat); \
1891 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1893 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1894 if ((tp##_is_infinity(xa.fld) && tp##_is_zero(xb.fld)) || \
1895 (tp##_is_infinity(xb.fld) && tp##_is_zero(xa.fld))) { \
1896 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, sfprf); \
1897 } else if (tp##_is_signaling_nan(xa.fld) || \
1898 tp##_is_signaling_nan(xb.fld)) { \
1899 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
1904 xt.fld = helper_frsp(env, xt.fld); \
1908 helper_compute_fprf(env, xt.fld); \
1912 putVSR(xT(opcode), &xt, env); \
1913 helper_float_check_status(env); \
1916 VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0)
1917 VSX_MUL(xsmulsp, 1, float64, VsrD(0), 1, 1)
1918 VSX_MUL(xvmuldp, 2, float64, VsrD(i), 0, 0)
1919 VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0)
1921 /* VSX_DIV - VSX floating point divide
1922 * op - instruction mnemonic
1923 * nels - number of elements (1, 2 or 4)
1924 * tp - type (float32 or float64)
1925 * fld - vsr_t field (VsrD(*) or VsrW(*))
1928 #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \
1929 void helper_##op(CPUPPCState *env, uint32_t opcode) \
1931 ppc_vsr_t xt, xa, xb; \
1934 getVSR(xA(opcode), &xa, env); \
1935 getVSR(xB(opcode), &xb, env); \
1936 getVSR(xT(opcode), &xt, env); \
1937 helper_reset_fpstatus(env); \
1939 for (i = 0; i < nels; i++) { \
1940 float_status tstat = env->fp_status; \
1941 set_float_exception_flags(0, &tstat); \
1942 xt.fld = tp##_div(xa.fld, xb.fld, &tstat); \
1943 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1945 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1946 if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { \
1947 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, sfprf); \
1948 } else if (tp##_is_zero(xa.fld) && \
1949 tp##_is_zero(xb.fld)) { \
1950 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf); \
1951 } else if (tp##_is_signaling_nan(xa.fld) || \
1952 tp##_is_signaling_nan(xb.fld)) { \
1953 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
1958 xt.fld = helper_frsp(env, xt.fld); \
1962 helper_compute_fprf(env, xt.fld); \
1966 putVSR(xT(opcode), &xt, env); \
1967 helper_float_check_status(env); \
1970 VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0)
1971 VSX_DIV(xsdivsp, 1, float64, VsrD(0), 1, 1)
1972 VSX_DIV(xvdivdp, 2, float64, VsrD(i), 0, 0)
1973 VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0)
1975 /* VSX_RE - VSX floating point reciprocal estimate
1976 * op - instruction mnemonic
1977 * nels - number of elements (1, 2 or 4)
1978 * tp - type (float32 or float64)
1979 * fld - vsr_t field (VsrD(*) or VsrW(*))
1982 #define VSX_RE(op, nels, tp, fld, sfprf, r2sp) \
1983 void helper_##op(CPUPPCState *env, uint32_t opcode) \
1988 getVSR(xB(opcode), &xb, env); \
1989 getVSR(xT(opcode), &xt, env); \
1990 helper_reset_fpstatus(env); \
1992 for (i = 0; i < nels; i++) { \
1993 if (unlikely(tp##_is_signaling_nan(xb.fld))) { \
1994 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
1996 xt.fld = tp##_div(tp##_one, xb.fld, &env->fp_status); \
1999 xt.fld = helper_frsp(env, xt.fld); \
2003 helper_compute_fprf(env, xt.fld); \
2007 putVSR(xT(opcode), &xt, env); \
2008 helper_float_check_status(env); \
2011 VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0)
2012 VSX_RE(xsresp, 1, float64, VsrD(0), 1, 1)
2013 VSX_RE(xvredp, 2, float64, VsrD(i), 0, 0)
2014 VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0)
2016 /* VSX_SQRT - VSX floating point square root
2017 * op - instruction mnemonic
2018 * nels - number of elements (1, 2 or 4)
2019 * tp - type (float32 or float64)
2020 * fld - vsr_t field (VsrD(*) or VsrW(*))
2023 #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \
2024 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2029 getVSR(xB(opcode), &xb, env); \
2030 getVSR(xT(opcode), &xt, env); \
2031 helper_reset_fpstatus(env); \
2033 for (i = 0; i < nels; i++) { \
2034 float_status tstat = env->fp_status; \
2035 set_float_exception_flags(0, &tstat); \
2036 xt.fld = tp##_sqrt(xb.fld, &tstat); \
2037 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2039 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2040 if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \
2041 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \
2042 } else if (tp##_is_signaling_nan(xb.fld)) { \
2043 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
2048 xt.fld = helper_frsp(env, xt.fld); \
2052 helper_compute_fprf(env, xt.fld); \
2056 putVSR(xT(opcode), &xt, env); \
2057 helper_float_check_status(env); \
2060 VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0)
2061 VSX_SQRT(xssqrtsp, 1, float64, VsrD(0), 1, 1)
2062 VSX_SQRT(xvsqrtdp, 2, float64, VsrD(i), 0, 0)
2063 VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0)
2065 /* VSX_RSQRTE - VSX floating point reciprocal square root estimate
2066 * op - instruction mnemonic
2067 * nels - number of elements (1, 2 or 4)
2068 * tp - type (float32 or float64)
2069 * fld - vsr_t field (VsrD(*) or VsrW(*))
2072 #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) \
2073 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2078 getVSR(xB(opcode), &xb, env); \
2079 getVSR(xT(opcode), &xt, env); \
2080 helper_reset_fpstatus(env); \
2082 for (i = 0; i < nels; i++) { \
2083 float_status tstat = env->fp_status; \
2084 set_float_exception_flags(0, &tstat); \
2085 xt.fld = tp##_sqrt(xb.fld, &tstat); \
2086 xt.fld = tp##_div(tp##_one, xt.fld, &tstat); \
2087 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2089 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2090 if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { \
2091 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf); \
2092 } else if (tp##_is_signaling_nan(xb.fld)) { \
2093 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
2098 xt.fld = helper_frsp(env, xt.fld); \
2102 helper_compute_fprf(env, xt.fld); \
2106 putVSR(xT(opcode), &xt, env); \
2107 helper_float_check_status(env); \
2110 VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0)
2111 VSX_RSQRTE(xsrsqrtesp, 1, float64, VsrD(0), 1, 1)
2112 VSX_RSQRTE(xvrsqrtedp, 2, float64, VsrD(i), 0, 0)
2113 VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0)
2115 /* VSX_TDIV - VSX floating point test for divide
2116 * op - instruction mnemonic
2117 * nels - number of elements (1, 2 or 4)
2118 * tp - type (float32 or float64)
2119 * fld - vsr_t field (VsrD(*) or VsrW(*))
2120 * emin - minimum unbiased exponent
2121 * emax - maximum unbiased exponent
2122 * nbits - number of fraction bits
2124 #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
2125 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2132 getVSR(xA(opcode), &xa, env); \
2133 getVSR(xB(opcode), &xb, env); \
2135 for (i = 0; i < nels; i++) { \
2136 if (unlikely(tp##_is_infinity(xa.fld) || \
2137 tp##_is_infinity(xb.fld) || \
2138 tp##_is_zero(xb.fld))) { \
2142 int e_a = ppc_##tp##_get_unbiased_exp(xa.fld); \
2143 int e_b = ppc_##tp##_get_unbiased_exp(xb.fld); \
2145 if (unlikely(tp##_is_any_nan(xa.fld) || \
2146 tp##_is_any_nan(xb.fld))) { \
2148 } else if ((e_b <= emin) || (e_b >= (emax-2))) { \
2150 } else if (!tp##_is_zero(xa.fld) && \
2151 (((e_a - e_b) >= emax) || \
2152 ((e_a - e_b) <= (emin+1)) || \
2153 (e_a <= (emin+nbits)))) { \
2157 if (unlikely(tp##_is_zero_or_denormal(xb.fld))) { \
2158 /* XB is not zero because of the above check and */ \
2159 /* so must be denormalized. */ \
2165 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2168 VSX_TDIV(xstdivdp, 1, float64, VsrD(0), -1022, 1023, 52)
2169 VSX_TDIV(xvtdivdp, 2, float64, VsrD(i), -1022, 1023, 52)
2170 VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23)
2172 /* VSX_TSQRT - VSX floating point test for square root
2173 * op - instruction mnemonic
2174 * nels - number of elements (1, 2 or 4)
2175 * tp - type (float32 or float64)
2176 * fld - vsr_t field (VsrD(*) or VsrW(*))
2177 * emin - minimum unbiased exponent
2178 * emax - maximum unbiased exponent
2179 * nbits - number of fraction bits
2181 #define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
2182 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2189 getVSR(xA(opcode), &xa, env); \
2190 getVSR(xB(opcode), &xb, env); \
2192 for (i = 0; i < nels; i++) { \
2193 if (unlikely(tp##_is_infinity(xb.fld) || \
2194 tp##_is_zero(xb.fld))) { \
2198 int e_b = ppc_##tp##_get_unbiased_exp(xb.fld); \
2200 if (unlikely(tp##_is_any_nan(xb.fld))) { \
2202 } else if (unlikely(tp##_is_zero(xb.fld))) { \
2204 } else if (unlikely(tp##_is_neg(xb.fld))) { \
2206 } else if (!tp##_is_zero(xb.fld) && \
2207 (e_b <= (emin+nbits))) { \
2211 if (unlikely(tp##_is_zero_or_denormal(xb.fld))) { \
2212 /* XB is not zero because of the above check and */ \
2213 /* therefore must be denormalized. */ \
2219 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2222 VSX_TSQRT(xstsqrtdp, 1, float64, VsrD(0), -1022, 52)
2223 VSX_TSQRT(xvtsqrtdp, 2, float64, VsrD(i), -1022, 52)
2224 VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
2226 /* VSX_MADD - VSX floating point muliply/add variations
2227 * op - instruction mnemonic
2228 * nels - number of elements (1, 2 or 4)
2229 * tp - type (float32 or float64)
2230 * fld - vsr_t field (VsrD(*) or VsrW(*))
2231 * maddflgs - flags for the float*muladd routine that control the
2232 * various forms (madd, msub, nmadd, nmsub)
2233 * afrm - A form (1=A, 0=M)
2236 #define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp) \
2237 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2239 ppc_vsr_t xt_in, xa, xb, xt_out; \
2243 if (afrm) { /* AxB + T */ \
2246 } else { /* AxT + B */ \
2251 getVSR(xA(opcode), &xa, env); \
2252 getVSR(xB(opcode), &xb, env); \
2253 getVSR(xT(opcode), &xt_in, env); \
2257 helper_reset_fpstatus(env); \
2259 for (i = 0; i < nels; i++) { \
2260 float_status tstat = env->fp_status; \
2261 set_float_exception_flags(0, &tstat); \
2262 if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
2263 /* Avoid double rounding errors by rounding the intermediate */ \
2264 /* result to odd. */ \
2265 set_float_rounding_mode(float_round_to_zero, &tstat); \
2266 xt_out.fld = tp##_muladd(xa.fld, b->fld, c->fld, \
2267 maddflgs, &tstat); \
2268 xt_out.fld |= (get_float_exception_flags(&tstat) & \
2269 float_flag_inexact) != 0; \
2271 xt_out.fld = tp##_muladd(xa.fld, b->fld, c->fld, \
2272 maddflgs, &tstat); \
2274 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2276 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2277 if (tp##_is_signaling_nan(xa.fld) || \
2278 tp##_is_signaling_nan(b->fld) || \
2279 tp##_is_signaling_nan(c->fld)) { \
2280 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \
2281 tstat.float_exception_flags &= ~float_flag_invalid; \
2283 if ((tp##_is_infinity(xa.fld) && tp##_is_zero(b->fld)) || \
2284 (tp##_is_zero(xa.fld) && tp##_is_infinity(b->fld))) { \
2285 xt_out.fld = float64_to_##tp(fload_invalid_op_excp(env, \
2286 POWERPC_EXCP_FP_VXIMZ, sfprf), &env->fp_status); \
2287 tstat.float_exception_flags &= ~float_flag_invalid; \
2289 if ((tstat.float_exception_flags & float_flag_invalid) && \
2290 ((tp##_is_infinity(xa.fld) || \
2291 tp##_is_infinity(b->fld)) && \
2292 tp##_is_infinity(c->fld))) { \
2293 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); \
2298 xt_out.fld = helper_frsp(env, xt_out.fld); \
2302 helper_compute_fprf(env, xt_out.fld); \
2305 putVSR(xT(opcode), &xt_out, env); \
2306 helper_float_check_status(env); \
2310 #define MSUB_FLGS float_muladd_negate_c
2311 #define NMADD_FLGS float_muladd_negate_result
2312 #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
2314 VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0)
2315 VSX_MADD(xsmaddmdp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 0)
2316 VSX_MADD(xsmsubadp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 0)
2317 VSX_MADD(xsmsubmdp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 0)
2318 VSX_MADD(xsnmaddadp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 0)
2319 VSX_MADD(xsnmaddmdp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 0)
2320 VSX_MADD(xsnmsubadp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 0)
2321 VSX_MADD(xsnmsubmdp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 0)
2323 VSX_MADD(xsmaddasp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 1)
2324 VSX_MADD(xsmaddmsp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 1)
2325 VSX_MADD(xsmsubasp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 1)
2326 VSX_MADD(xsmsubmsp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 1)
2327 VSX_MADD(xsnmaddasp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 1)
2328 VSX_MADD(xsnmaddmsp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 1)
2329 VSX_MADD(xsnmsubasp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 1)
2330 VSX_MADD(xsnmsubmsp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 1)
2332 VSX_MADD(xvmaddadp, 2, float64, VsrD(i), MADD_FLGS, 1, 0, 0)
2333 VSX_MADD(xvmaddmdp, 2, float64, VsrD(i), MADD_FLGS, 0, 0, 0)
2334 VSX_MADD(xvmsubadp, 2, float64, VsrD(i), MSUB_FLGS, 1, 0, 0)
2335 VSX_MADD(xvmsubmdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0, 0)
2336 VSX_MADD(xvnmaddadp, 2, float64, VsrD(i), NMADD_FLGS, 1, 0, 0)
2337 VSX_MADD(xvnmaddmdp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0, 0)
2338 VSX_MADD(xvnmsubadp, 2, float64, VsrD(i), NMSUB_FLGS, 1, 0, 0)
2339 VSX_MADD(xvnmsubmdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0, 0)
2341 VSX_MADD(xvmaddasp, 4, float32, VsrW(i), MADD_FLGS, 1, 0, 0)
2342 VSX_MADD(xvmaddmsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0, 0)
2343 VSX_MADD(xvmsubasp, 4, float32, VsrW(i), MSUB_FLGS, 1, 0, 0)
2344 VSX_MADD(xvmsubmsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0, 0)
2345 VSX_MADD(xvnmaddasp, 4, float32, VsrW(i), NMADD_FLGS, 1, 0, 0)
2346 VSX_MADD(xvnmaddmsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0, 0)
2347 VSX_MADD(xvnmsubasp, 4, float32, VsrW(i), NMSUB_FLGS, 1, 0, 0)
2348 VSX_MADD(xvnmsubmsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0, 0)
2350 #define VSX_SCALAR_CMP(op, ordered) \
2351 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2356 getVSR(xA(opcode), &xa, env); \
2357 getVSR(xB(opcode), &xb, env); \
2359 if (unlikely(float64_is_any_nan(xa.VsrD(0)) || \
2360 float64_is_any_nan(xb.VsrD(0)))) { \
2361 if (float64_is_signaling_nan(xa.VsrD(0)) || \
2362 float64_is_signaling_nan(xb.VsrD(0))) { \
2363 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2366 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
2370 if (float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) { \
2372 } else if (!float64_le(xa.VsrD(0), xb.VsrD(0), \
2373 &env->fp_status)) { \
2380 env->fpscr &= ~(0x0F << FPSCR_FPRF); \
2381 env->fpscr |= cc << FPSCR_FPRF; \
2382 env->crf[BF(opcode)] = cc; \
2384 helper_float_check_status(env); \
2387 VSX_SCALAR_CMP(xscmpodp, 1)
2388 VSX_SCALAR_CMP(xscmpudp, 0)
2390 /* VSX_MAX_MIN - VSX floating point maximum/minimum
2391 * name - instruction mnemonic
2392 * op - operation (max or min)
2393 * nels - number of elements (1, 2 or 4)
2394 * tp - type (float32 or float64)
2395 * fld - vsr_t field (VsrD(*) or VsrW(*))
2397 #define VSX_MAX_MIN(name, op, nels, tp, fld) \
2398 void helper_##name(CPUPPCState *env, uint32_t opcode) \
2400 ppc_vsr_t xt, xa, xb; \
2403 getVSR(xA(opcode), &xa, env); \
2404 getVSR(xB(opcode), &xb, env); \
2405 getVSR(xT(opcode), &xt, env); \
2407 for (i = 0; i < nels; i++) { \
2408 xt.fld = tp##_##op(xa.fld, xb.fld, &env->fp_status); \
2409 if (unlikely(tp##_is_signaling_nan(xa.fld) || \
2410 tp##_is_signaling_nan(xb.fld))) { \
2411 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2415 putVSR(xT(opcode), &xt, env); \
2416 helper_float_check_status(env); \
2419 VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, VsrD(0))
2420 VSX_MAX_MIN(xvmaxdp, maxnum, 2, float64, VsrD(i))
2421 VSX_MAX_MIN(xvmaxsp, maxnum, 4, float32, VsrW(i))
2422 VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
2423 VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
2424 VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
2426 /* VSX_CMP - VSX floating point compare
2427 * op - instruction mnemonic
2428 * nels - number of elements (1, 2 or 4)
2429 * tp - type (float32 or float64)
2430 * fld - vsr_t field (VsrD(*) or VsrW(*))
2431 * cmp - comparison operation
2432 * svxvc - set VXVC bit
2434 #define VSX_CMP(op, nels, tp, fld, cmp, svxvc) \
2435 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2437 ppc_vsr_t xt, xa, xb; \
2440 int all_false = 1; \
2442 getVSR(xA(opcode), &xa, env); \
2443 getVSR(xB(opcode), &xb, env); \
2444 getVSR(xT(opcode), &xt, env); \
2446 for (i = 0; i < nels; i++) { \
2447 if (unlikely(tp##_is_any_nan(xa.fld) || \
2448 tp##_is_any_nan(xb.fld))) { \
2449 if (tp##_is_signaling_nan(xa.fld) || \
2450 tp##_is_signaling_nan(xb.fld)) { \
2451 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2454 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
2459 if (tp##_##cmp(xb.fld, xa.fld, &env->fp_status) == 1) { \
2469 putVSR(xT(opcode), &xt, env); \
2470 if ((opcode >> (31-21)) & 1) { \
2471 env->crf[6] = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
2473 helper_float_check_status(env); \
2476 VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0)
2477 VSX_CMP(xvcmpgedp, 2, float64, VsrD(i), le, 1)
2478 VSX_CMP(xvcmpgtdp, 2, float64, VsrD(i), lt, 1)
2479 VSX_CMP(xvcmpeqsp, 4, float32, VsrW(i), eq, 0)
2480 VSX_CMP(xvcmpgesp, 4, float32, VsrW(i), le, 1)
2481 VSX_CMP(xvcmpgtsp, 4, float32, VsrW(i), lt, 1)
2483 /* VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
2484 * op - instruction mnemonic
2485 * nels - number of elements (1, 2 or 4)
2486 * stp - source type (float32 or float64)
2487 * ttp - target type (float32 or float64)
2488 * sfld - source vsr_t field
2489 * tfld - target vsr_t field (f32 or f64)
2492 #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2493 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2498 getVSR(xB(opcode), &xb, env); \
2499 getVSR(xT(opcode), &xt, env); \
2501 for (i = 0; i < nels; i++) { \
2502 xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
2503 if (unlikely(stp##_is_signaling_nan(xb.sfld))) { \
2504 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2505 xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
2508 helper_compute_fprf(env, ttp##_to_float64(xt.tfld, \
2509 &env->fp_status)); \
2513 putVSR(xT(opcode), &xt, env); \
2514 helper_float_check_status(env); \
2517 VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
2518 VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
2519 VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2*i), 0)
2520 VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2*i), VsrD(i), 0)
2522 uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
2524 float_status tstat = env->fp_status;
2525 set_float_exception_flags(0, &tstat);
2527 return (uint64_t)float64_to_float32(xb, &tstat) << 32;
2530 uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
2532 float_status tstat = env->fp_status;
2533 set_float_exception_flags(0, &tstat);
2535 return float32_to_float64(xb >> 32, &tstat);
2538 /* VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
2539 * op - instruction mnemonic
2540 * nels - number of elements (1, 2 or 4)
2541 * stp - source type (float32 or float64)
2542 * ttp - target type (int32, uint32, int64 or uint64)
2543 * sfld - source vsr_t field
2544 * tfld - target vsr_t field
2545 * rnan - resulting NaN
2547 #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan) \
2548 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2553 getVSR(xB(opcode), &xb, env); \
2554 getVSR(xT(opcode), &xt, env); \
2556 for (i = 0; i < nels; i++) { \
2557 if (unlikely(stp##_is_any_nan(xb.sfld))) { \
2558 if (stp##_is_signaling_nan(xb.sfld)) { \
2559 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2561 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \
2564 xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld, \
2566 if (env->fp_status.float_exception_flags & float_flag_invalid) { \
2567 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); \
2572 putVSR(xT(opcode), &xt, env); \
2573 helper_float_check_status(env); \
2576 VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \
2577 0x8000000000000000ULL)
2578 VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \
2580 VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL)
2581 VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U)
2582 VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \
2583 0x8000000000000000ULL)
2584 VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2*i), \
2586 VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL)
2587 VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2*i), 0U)
2588 VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2*i), VsrD(i), \
2589 0x8000000000000000ULL)
2590 VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
2591 VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2*i), VsrD(i), 0ULL)
2592 VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
2594 /* VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
2595 * op - instruction mnemonic
2596 * nels - number of elements (1, 2 or 4)
2597 * stp - source type (int32, uint32, int64 or uint64)
2598 * ttp - target type (float32 or float64)
2599 * sfld - source vsr_t field
2600 * tfld - target vsr_t field
2601 * jdef - definition of the j index (i or 2*i)
2604 #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \
2605 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2610 getVSR(xB(opcode), &xb, env); \
2611 getVSR(xT(opcode), &xt, env); \
2613 for (i = 0; i < nels; i++) { \
2614 xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
2616 xt.tfld = helper_frsp(env, xt.tfld); \
2619 helper_compute_fprf(env, xt.tfld); \
2623 putVSR(xT(opcode), &xt, env); \
2624 helper_float_check_status(env); \
2627 VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
2628 VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0)
2629 VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1)
2630 VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1)
2631 VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
2632 VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
2633 VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2*i), VsrD(i), 0, 0)
2634 VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2*i), VsrD(i), 0, 0)
2635 VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2*i), 0, 0)
2636 VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2*i), 0, 0)
2637 VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
2638 VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
2640 /* For "use current rounding mode", define a value that will not be one of
2641 * the existing rounding model enums.
2643 #define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
2644 float_round_up + float_round_to_zero)
2646 /* VSX_ROUND - VSX floating point round
2647 * op - instruction mnemonic
2648 * nels - number of elements (1, 2 or 4)
2649 * tp - type (float32 or float64)
2650 * fld - vsr_t field (VsrD(*) or VsrW(*))
2651 * rmode - rounding mode
2654 #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \
2655 void helper_##op(CPUPPCState *env, uint32_t opcode) \
2659 getVSR(xB(opcode), &xb, env); \
2660 getVSR(xT(opcode), &xt, env); \
2662 if (rmode != FLOAT_ROUND_CURRENT) { \
2663 set_float_rounding_mode(rmode, &env->fp_status); \
2666 for (i = 0; i < nels; i++) { \
2667 if (unlikely(tp##_is_signaling_nan(xb.fld))) { \
2668 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2669 xt.fld = tp##_snan_to_qnan(xb.fld); \
2671 xt.fld = tp##_round_to_int(xb.fld, &env->fp_status); \
2674 helper_compute_fprf(env, xt.fld); \
2678 /* If this is not a "use current rounding mode" instruction, \
2679 * then inhibit setting of the XX bit and restore rounding \
2680 * mode from FPSCR */ \
2681 if (rmode != FLOAT_ROUND_CURRENT) { \
2682 fpscr_set_rounding_mode(env); \
2683 env->fp_status.float_exception_flags &= ~float_flag_inexact; \
2686 putVSR(xT(opcode), &xt, env); \
2687 helper_float_check_status(env); \
2690 VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_nearest_even, 1)
2691 VSX_ROUND(xsrdpic, 1, float64, VsrD(0), FLOAT_ROUND_CURRENT, 1)
2692 VSX_ROUND(xsrdpim, 1, float64, VsrD(0), float_round_down, 1)
2693 VSX_ROUND(xsrdpip, 1, float64, VsrD(0), float_round_up, 1)
2694 VSX_ROUND(xsrdpiz, 1, float64, VsrD(0), float_round_to_zero, 1)
2696 VSX_ROUND(xvrdpi, 2, float64, VsrD(i), float_round_nearest_even, 0)
2697 VSX_ROUND(xvrdpic, 2, float64, VsrD(i), FLOAT_ROUND_CURRENT, 0)
2698 VSX_ROUND(xvrdpim, 2, float64, VsrD(i), float_round_down, 0)
2699 VSX_ROUND(xvrdpip, 2, float64, VsrD(i), float_round_up, 0)
2700 VSX_ROUND(xvrdpiz, 2, float64, VsrD(i), float_round_to_zero, 0)
2702 VSX_ROUND(xvrspi, 4, float32, VsrW(i), float_round_nearest_even, 0)
2703 VSX_ROUND(xvrspic, 4, float32, VsrW(i), FLOAT_ROUND_CURRENT, 0)
2704 VSX_ROUND(xvrspim, 4, float32, VsrW(i), float_round_down, 0)
2705 VSX_ROUND(xvrspip, 4, float32, VsrW(i), float_round_up, 0)
2706 VSX_ROUND(xvrspiz, 4, float32, VsrW(i), float_round_to_zero, 0)
2708 uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
2710 helper_reset_fpstatus(env);
2712 uint64_t xt = helper_frsp(env, xb);
2714 helper_compute_fprf(env, xt);
2715 helper_float_check_status(env);