2 * Microblaze helper routines.
4 * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "exec/helper-proto.h"
24 #include "qemu/host-utils.h"
25 #include "exec/cpu_ldst.h"
29 #if !defined(CONFIG_USER_ONLY)
31 /* Try to fill the TLB and return an exception if error. If retaddr is
32 * NULL, it means that the function was called in C code (i.e. not
33 * from generated code or from helper.c)
35 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
40 ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
43 /* now we have a real cpu fault */
44 cpu_restore_state(cs, retaddr);
51 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
53 int test = ctrl & STREAM_TEST;
54 int atomic = ctrl & STREAM_ATOMIC;
55 int control = ctrl & STREAM_CONTROL;
56 int nonblock = ctrl & STREAM_NONBLOCK;
57 int exception = ctrl & STREAM_EXCEPTION;
59 qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
68 uint32_t helper_get(uint32_t id, uint32_t ctrl)
70 int test = ctrl & STREAM_TEST;
71 int atomic = ctrl & STREAM_ATOMIC;
72 int control = ctrl & STREAM_CONTROL;
73 int nonblock = ctrl & STREAM_NONBLOCK;
74 int exception = ctrl & STREAM_EXCEPTION;
76 qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
83 return 0xdead0000 | id;
86 void helper_raise_exception(CPUMBState *env, uint32_t index)
88 CPUState *cs = CPU(mb_env_get_cpu(env));
90 cs->exception_index = index;
94 void helper_debug(CPUMBState *env)
98 qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
99 qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
100 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
101 env->debug, env->imm, env->iflags);
102 qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
103 env->btaken, env->btarget,
104 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
105 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
106 (env->sregs[SR_MSR] & MSR_EIP),
107 (env->sregs[SR_MSR] & MSR_IE));
108 for (i = 0; i < 32; i++) {
109 qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
110 if ((i + 1) % 4 == 0)
116 static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
120 if ((b == ~0) && cin)
122 else if ((~0 - a) < (b + cin))
127 uint32_t helper_cmp(uint32_t a, uint32_t b)
132 if ((b & 0x80000000) ^ (a & 0x80000000))
133 t = (t & 0x7fffffff) | (b & 0x80000000);
137 uint32_t helper_cmpu(uint32_t a, uint32_t b)
142 if ((b & 0x80000000) ^ (a & 0x80000000))
143 t = (t & 0x7fffffff) | (a & 0x80000000);
147 uint32_t helper_clz(uint32_t t0)
152 uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
154 return compute_carry(a, b, cf);
157 static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
160 env->sregs[SR_MSR] |= MSR_DZ;
162 if ((env->sregs[SR_MSR] & MSR_EE)
163 && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
164 env->sregs[SR_ESR] = ESR_EC_DIVZERO;
165 helper_raise_exception(env, EXCP_HW_EXCP);
169 env->sregs[SR_MSR] &= ~MSR_DZ;
173 uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
175 if (!div_prepare(env, a, b)) {
178 return (int32_t)a / (int32_t)b;
181 uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
183 if (!div_prepare(env, a, b)) {
189 /* raise FPU exception. */
190 static void raise_fpu_exception(CPUMBState *env)
192 env->sregs[SR_ESR] = ESR_EC_FPU;
193 helper_raise_exception(env, EXCP_HW_EXCP);
196 static void update_fpu_flags(CPUMBState *env, int flags)
200 if (flags & float_flag_invalid) {
201 env->sregs[SR_FSR] |= FSR_IO;
204 if (flags & float_flag_divbyzero) {
205 env->sregs[SR_FSR] |= FSR_DZ;
208 if (flags & float_flag_overflow) {
209 env->sregs[SR_FSR] |= FSR_OF;
212 if (flags & float_flag_underflow) {
213 env->sregs[SR_FSR] |= FSR_UF;
217 && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
218 && (env->sregs[SR_MSR] & MSR_EE)) {
219 raise_fpu_exception(env);
223 uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
225 CPU_FloatU fd, fa, fb;
228 set_float_exception_flags(0, &env->fp_status);
231 fd.f = float32_add(fa.f, fb.f, &env->fp_status);
233 flags = get_float_exception_flags(&env->fp_status);
234 update_fpu_flags(env, flags);
238 uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
240 CPU_FloatU fd, fa, fb;
243 set_float_exception_flags(0, &env->fp_status);
246 fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
247 flags = get_float_exception_flags(&env->fp_status);
248 update_fpu_flags(env, flags);
252 uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
254 CPU_FloatU fd, fa, fb;
257 set_float_exception_flags(0, &env->fp_status);
260 fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
261 flags = get_float_exception_flags(&env->fp_status);
262 update_fpu_flags(env, flags);
267 uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
269 CPU_FloatU fd, fa, fb;
272 set_float_exception_flags(0, &env->fp_status);
275 fd.f = float32_div(fb.f, fa.f, &env->fp_status);
276 flags = get_float_exception_flags(&env->fp_status);
277 update_fpu_flags(env, flags);
282 uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
290 if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
291 update_fpu_flags(env, float_flag_invalid);
295 if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
302 uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
308 set_float_exception_flags(0, &env->fp_status);
311 r = float32_lt(fb.f, fa.f, &env->fp_status);
312 flags = get_float_exception_flags(&env->fp_status);
313 update_fpu_flags(env, flags & float_flag_invalid);
318 uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
324 set_float_exception_flags(0, &env->fp_status);
327 r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
328 flags = get_float_exception_flags(&env->fp_status);
329 update_fpu_flags(env, flags & float_flag_invalid);
334 uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
342 set_float_exception_flags(0, &env->fp_status);
343 r = float32_le(fa.f, fb.f, &env->fp_status);
344 flags = get_float_exception_flags(&env->fp_status);
345 update_fpu_flags(env, flags & float_flag_invalid);
351 uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
358 set_float_exception_flags(0, &env->fp_status);
359 r = float32_lt(fa.f, fb.f, &env->fp_status);
360 flags = get_float_exception_flags(&env->fp_status);
361 update_fpu_flags(env, flags & float_flag_invalid);
365 uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
372 set_float_exception_flags(0, &env->fp_status);
373 r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
374 flags = get_float_exception_flags(&env->fp_status);
375 update_fpu_flags(env, flags & float_flag_invalid);
380 uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
387 set_float_exception_flags(0, &env->fp_status);
388 r = !float32_lt(fa.f, fb.f, &env->fp_status);
389 flags = get_float_exception_flags(&env->fp_status);
390 update_fpu_flags(env, flags & float_flag_invalid);
395 uint32_t helper_flt(CPUMBState *env, uint32_t a)
400 fd.f = int32_to_float32(fa.l, &env->fp_status);
404 uint32_t helper_fint(CPUMBState *env, uint32_t a)
410 set_float_exception_flags(0, &env->fp_status);
412 r = float32_to_int32(fa.f, &env->fp_status);
413 flags = get_float_exception_flags(&env->fp_status);
414 update_fpu_flags(env, flags);
419 uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
424 set_float_exception_flags(0, &env->fp_status);
426 fd.l = float32_sqrt(fa.f, &env->fp_status);
427 flags = get_float_exception_flags(&env->fp_status);
428 update_fpu_flags(env, flags);
433 uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
436 uint32_t mask = 0xff000000;
438 for (i = 0; i < 4; i++) {
439 if ((a & mask) == (b & mask))
446 void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
450 qemu_log_mask(CPU_LOG_INT,
451 "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
453 env->sregs[SR_EAR] = addr;
454 env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
457 env->sregs[SR_ESR] |= 1 << 11;
459 if (!(env->sregs[SR_MSR] & MSR_EE)) {
462 helper_raise_exception(env, EXCP_HW_EXCP);
466 void helper_stackprot(CPUMBState *env, uint32_t addr)
468 if (addr < env->slr || addr > env->shr) {
469 qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n",
470 addr, env->slr, env->shr);
471 env->sregs[SR_EAR] = addr;
472 env->sregs[SR_ESR] = ESR_EC_STACKPROT;
473 helper_raise_exception(env, EXCP_HW_EXCP);
477 #if !defined(CONFIG_USER_ONLY)
478 /* Writes/reads to the MMU's special regs end up here. */
479 uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
481 return mmu_read(env, rn);
484 void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
486 mmu_write(env, rn, v);
489 void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
490 bool is_write, bool is_exec, int is_asi,
496 qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
497 addr, is_write ? 1 : 0, is_exec ? 1 : 0);
501 cpu = MICROBLAZE_CPU(cs);
503 if (!(env->sregs[SR_MSR] & MSR_EE)) {
507 env->sregs[SR_EAR] = addr;
509 if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
510 env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
511 helper_raise_exception(env, EXCP_HW_EXCP);
514 if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
515 env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
516 helper_raise_exception(env, EXCP_HW_EXCP);