4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm_int.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "hw/i386/apic_internal.h"
34 #include "hw/i386/apic-msidef.h"
35 #include "exec/ioport.h"
36 #include <asm/hyperv.h>
37 #include "hw/pci/pci.h"
38 #include "migration/migration.h"
39 #include "exec/memattrs.h"
44 #define DPRINTF(fmt, ...) \
45 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
47 #define DPRINTF(fmt, ...) \
51 #define MSR_KVM_WALL_CLOCK 0x11
52 #define MSR_KVM_SYSTEM_TIME 0x12
55 #define BUS_MCEERR_AR 4
58 #define BUS_MCEERR_AO 5
61 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
62 KVM_CAP_INFO(SET_TSS_ADDR),
63 KVM_CAP_INFO(EXT_CPUID),
64 KVM_CAP_INFO(MP_STATE),
68 static bool has_msr_star;
69 static bool has_msr_hsave_pa;
70 static bool has_msr_tsc_adjust;
71 static bool has_msr_tsc_deadline;
72 static bool has_msr_feature_control;
73 static bool has_msr_async_pf_en;
74 static bool has_msr_pv_eoi_en;
75 static bool has_msr_misc_enable;
76 static bool has_msr_smbase;
77 static bool has_msr_bndcfgs;
78 static bool has_msr_kvm_steal_time;
79 static int lm_capable_kernel;
80 static bool has_msr_hv_hypercall;
81 static bool has_msr_hv_vapic;
82 static bool has_msr_hv_tsc;
83 static bool has_msr_mtrr;
84 static bool has_msr_xss;
86 static bool has_msr_architectural_pmu;
87 static uint32_t num_architectural_pmu_counters;
89 bool kvm_has_smm(void)
91 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
94 bool kvm_allows_irq0_override(void)
96 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
99 static int kvm_get_tsc(CPUState *cs)
101 X86CPU *cpu = X86_CPU(cs);
102 CPUX86State *env = &cpu->env;
104 struct kvm_msrs info;
105 struct kvm_msr_entry entries[1];
109 if (env->tsc_valid) {
113 msr_data.info.nmsrs = 1;
114 msr_data.entries[0].index = MSR_IA32_TSC;
115 env->tsc_valid = !runstate_is_running();
117 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
122 env->tsc = msr_data.entries[0].data;
126 static inline void do_kvm_synchronize_tsc(void *arg)
133 void kvm_synchronize_all_tsc(void)
139 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
144 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
146 struct kvm_cpuid2 *cpuid;
149 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
150 cpuid = g_malloc0(size);
152 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
153 if (r == 0 && cpuid->nent >= max) {
161 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
169 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
172 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
174 struct kvm_cpuid2 *cpuid;
176 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
182 static const struct kvm_para_features {
185 } para_features[] = {
186 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
187 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
188 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
189 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
192 static int get_para_features(KVMState *s)
196 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
197 if (kvm_check_extension(s, para_features[i].cap)) {
198 features |= (1 << para_features[i].feature);
206 /* Returns the value for a specific register on the cpuid entry
208 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
228 /* Find matching entry for function/index on kvm_cpuid2 struct
230 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
235 for (i = 0; i < cpuid->nent; ++i) {
236 if (cpuid->entries[i].function == function &&
237 cpuid->entries[i].index == index) {
238 return &cpuid->entries[i];
245 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
246 uint32_t index, int reg)
248 struct kvm_cpuid2 *cpuid;
250 uint32_t cpuid_1_edx;
253 cpuid = get_supported_cpuid(s);
255 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
258 ret = cpuid_entry_get_reg(entry, reg);
261 /* Fixups for the data returned by KVM, below */
263 if (function == 1 && reg == R_EDX) {
264 /* KVM before 2.6.30 misreports the following features */
265 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
266 } else if (function == 1 && reg == R_ECX) {
267 /* We can set the hypervisor flag, even if KVM does not return it on
268 * GET_SUPPORTED_CPUID
270 ret |= CPUID_EXT_HYPERVISOR;
271 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
272 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
273 * and the irqchip is in the kernel.
275 if (kvm_irqchip_in_kernel() &&
276 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
277 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
280 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
281 * without the in-kernel irqchip
283 if (!kvm_irqchip_in_kernel()) {
284 ret &= ~CPUID_EXT_X2APIC;
286 } else if (function == 6 && reg == R_EAX) {
287 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
288 } else if (function == 0x80000001 && reg == R_EDX) {
289 /* On Intel, kvm returns cpuid according to the Intel spec,
290 * so add missing bits according to the AMD spec:
292 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
293 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
298 /* fallback for older kernels */
299 if ((function == KVM_CPUID_FEATURES) && !found) {
300 ret = get_para_features(s);
306 typedef struct HWPoisonPage {
308 QLIST_ENTRY(HWPoisonPage) list;
311 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
312 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
314 static void kvm_unpoison_all(void *param)
316 HWPoisonPage *page, *next_page;
318 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
319 QLIST_REMOVE(page, list);
320 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
325 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
329 QLIST_FOREACH(page, &hwpoison_page_list, list) {
330 if (page->ram_addr == ram_addr) {
334 page = g_new(HWPoisonPage, 1);
335 page->ram_addr = ram_addr;
336 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
339 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
344 r = kvm_check_extension(s, KVM_CAP_MCE);
347 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
352 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
354 CPUX86State *env = &cpu->env;
355 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
356 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
357 uint64_t mcg_status = MCG_STATUS_MCIP;
359 if (code == BUS_MCEERR_AR) {
360 status |= MCI_STATUS_AR | 0x134;
361 mcg_status |= MCG_STATUS_EIPV;
364 mcg_status |= MCG_STATUS_RIPV;
366 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
367 (MCM_ADDR_PHYS << 6) | 0xc,
368 cpu_x86_support_mca_broadcast(env) ?
369 MCE_INJECT_BROADCAST : 0);
372 static void hardware_memory_error(void)
374 fprintf(stderr, "Hardware memory error!\n");
378 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
380 X86CPU *cpu = X86_CPU(c);
381 CPUX86State *env = &cpu->env;
385 if ((env->mcg_cap & MCG_SER_P) && addr
386 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
387 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
388 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
389 fprintf(stderr, "Hardware memory error for memory used by "
390 "QEMU itself instead of guest system!\n");
391 /* Hope we are lucky for AO MCE */
392 if (code == BUS_MCEERR_AO) {
395 hardware_memory_error();
398 kvm_hwpoison_page_add(ram_addr);
399 kvm_mce_inject(cpu, paddr, code);
401 if (code == BUS_MCEERR_AO) {
403 } else if (code == BUS_MCEERR_AR) {
404 hardware_memory_error();
412 int kvm_arch_on_sigbus(int code, void *addr)
414 X86CPU *cpu = X86_CPU(first_cpu);
416 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
420 /* Hope we are lucky for AO MCE */
421 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
422 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
424 fprintf(stderr, "Hardware memory error for memory used by "
425 "QEMU itself instead of guest system!: %p\n", addr);
428 kvm_hwpoison_page_add(ram_addr);
429 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
431 if (code == BUS_MCEERR_AO) {
433 } else if (code == BUS_MCEERR_AR) {
434 hardware_memory_error();
442 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
444 CPUX86State *env = &cpu->env;
446 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
447 unsigned int bank, bank_num = env->mcg_cap & 0xff;
448 struct kvm_x86_mce mce;
450 env->exception_injected = -1;
453 * There must be at least one bank in use if an MCE is pending.
454 * Find it and use its values for the event injection.
456 for (bank = 0; bank < bank_num; bank++) {
457 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
461 assert(bank < bank_num);
464 mce.status = env->mce_banks[bank * 4 + 1];
465 mce.mcg_status = env->mcg_status;
466 mce.addr = env->mce_banks[bank * 4 + 2];
467 mce.misc = env->mce_banks[bank * 4 + 3];
469 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
474 static void cpu_update_state(void *opaque, int running, RunState state)
476 CPUX86State *env = opaque;
479 env->tsc_valid = false;
483 unsigned long kvm_arch_vcpu_id(CPUState *cs)
485 X86CPU *cpu = X86_CPU(cs);
489 #ifndef KVM_CPUID_SIGNATURE_NEXT
490 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
493 static bool hyperv_hypercall_available(X86CPU *cpu)
495 return cpu->hyperv_vapic ||
496 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
499 static bool hyperv_enabled(X86CPU *cpu)
501 CPUState *cs = CPU(cpu);
502 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
503 (hyperv_hypercall_available(cpu) ||
505 cpu->hyperv_relaxed_timing);
508 static Error *invtsc_mig_blocker;
510 #define KVM_MAX_CPUID_ENTRIES 100
512 int kvm_arch_init_vcpu(CPUState *cs)
515 struct kvm_cpuid2 cpuid;
516 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
517 } QEMU_PACKED cpuid_data;
518 X86CPU *cpu = X86_CPU(cs);
519 CPUX86State *env = &cpu->env;
520 uint32_t limit, i, j, cpuid_i;
522 struct kvm_cpuid_entry2 *c;
523 uint32_t signature[3];
524 int kvm_base = KVM_CPUID_SIGNATURE;
527 memset(&cpuid_data, 0, sizeof(cpuid_data));
531 /* Paravirtualization CPUIDs */
532 if (hyperv_enabled(cpu)) {
533 c = &cpuid_data.entries[cpuid_i++];
534 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
535 memcpy(signature, "Microsoft Hv", 12);
536 c->eax = HYPERV_CPUID_MIN;
537 c->ebx = signature[0];
538 c->ecx = signature[1];
539 c->edx = signature[2];
541 c = &cpuid_data.entries[cpuid_i++];
542 c->function = HYPERV_CPUID_INTERFACE;
543 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
544 c->eax = signature[0];
549 c = &cpuid_data.entries[cpuid_i++];
550 c->function = HYPERV_CPUID_VERSION;
554 c = &cpuid_data.entries[cpuid_i++];
555 c->function = HYPERV_CPUID_FEATURES;
556 if (cpu->hyperv_relaxed_timing) {
557 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
559 if (cpu->hyperv_vapic) {
560 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
561 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
562 has_msr_hv_vapic = true;
564 if (cpu->hyperv_time &&
565 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
566 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
567 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
569 has_msr_hv_tsc = true;
571 c = &cpuid_data.entries[cpuid_i++];
572 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
573 if (cpu->hyperv_relaxed_timing) {
574 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
576 if (has_msr_hv_vapic) {
577 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
579 c->ebx = cpu->hyperv_spinlock_attempts;
581 c = &cpuid_data.entries[cpuid_i++];
582 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
586 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
587 has_msr_hv_hypercall = true;
590 if (cpu->expose_kvm) {
591 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
592 c = &cpuid_data.entries[cpuid_i++];
593 c->function = KVM_CPUID_SIGNATURE | kvm_base;
594 c->eax = KVM_CPUID_FEATURES | kvm_base;
595 c->ebx = signature[0];
596 c->ecx = signature[1];
597 c->edx = signature[2];
599 c = &cpuid_data.entries[cpuid_i++];
600 c->function = KVM_CPUID_FEATURES | kvm_base;
601 c->eax = env->features[FEAT_KVM];
603 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
605 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
607 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
610 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
612 for (i = 0; i <= limit; i++) {
613 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
614 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
617 c = &cpuid_data.entries[cpuid_i++];
621 /* Keep reading function 2 till all the input is received */
625 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
626 KVM_CPUID_FLAG_STATE_READ_NEXT;
627 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
628 times = c->eax & 0xff;
630 for (j = 1; j < times; ++j) {
631 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
632 fprintf(stderr, "cpuid_data is full, no space for "
633 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
636 c = &cpuid_data.entries[cpuid_i++];
638 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
639 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
647 if (i == 0xd && j == 64) {
651 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
653 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
655 if (i == 4 && c->eax == 0) {
658 if (i == 0xb && !(c->ecx & 0xff00)) {
661 if (i == 0xd && c->eax == 0) {
664 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
665 fprintf(stderr, "cpuid_data is full, no space for "
666 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
669 c = &cpuid_data.entries[cpuid_i++];
675 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
683 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
684 if ((ver & 0xff) > 0) {
685 has_msr_architectural_pmu = true;
686 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
688 /* Shouldn't be more than 32, since that's the number of bits
689 * available in EBX to tell us _which_ counters are available.
692 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
693 num_architectural_pmu_counters = MAX_GP_COUNTERS;
698 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
700 for (i = 0x80000000; i <= limit; i++) {
701 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
702 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
705 c = &cpuid_data.entries[cpuid_i++];
709 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
712 /* Call Centaur's CPUID instructions they are supported. */
713 if (env->cpuid_xlevel2 > 0) {
714 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
716 for (i = 0xC0000000; i <= limit; i++) {
717 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
718 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
721 c = &cpuid_data.entries[cpuid_i++];
725 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
729 cpuid_data.cpuid.nent = cpuid_i;
731 if (((env->cpuid_version >> 8)&0xF) >= 6
732 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
733 (CPUID_MCE | CPUID_MCA)
734 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
739 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
741 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
745 if (banks > MCE_BANKS_DEF) {
746 banks = MCE_BANKS_DEF;
748 mcg_cap &= MCE_CAP_DEF;
750 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
752 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
756 env->mcg_cap = mcg_cap;
759 qemu_add_vm_change_state_handler(cpu_update_state, env);
761 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
763 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
764 !!(c->ecx & CPUID_EXT_SMX);
767 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
768 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
770 error_setg(&invtsc_mig_blocker,
771 "State blocked by non-migratable CPU device"
773 migrate_add_blocker(invtsc_mig_blocker);
775 vmstate_x86_cpu.unmigratable = 1;
778 cpuid_data.cpuid.padding = 0;
779 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
784 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
785 if (r && env->tsc_khz) {
786 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
788 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
793 if (kvm_has_xsave()) {
794 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
797 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
804 void kvm_arch_reset_vcpu(X86CPU *cpu)
806 CPUX86State *env = &cpu->env;
808 env->exception_injected = -1;
809 env->interrupt_injected = -1;
811 if (kvm_irqchip_in_kernel()) {
812 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
813 KVM_MP_STATE_UNINITIALIZED;
815 env->mp_state = KVM_MP_STATE_RUNNABLE;
819 void kvm_arch_do_init_vcpu(X86CPU *cpu)
821 CPUX86State *env = &cpu->env;
823 /* APs get directly into wait-for-SIPI state. */
824 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
825 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
829 static int kvm_get_supported_msrs(KVMState *s)
831 static int kvm_supported_msrs;
835 if (kvm_supported_msrs == 0) {
836 struct kvm_msr_list msr_list, *kvm_msr_list;
838 kvm_supported_msrs = -1;
840 /* Obtain MSR list from KVM. These are the MSRs that we must
843 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
844 if (ret < 0 && ret != -E2BIG) {
847 /* Old kernel modules had a bug and could write beyond the provided
848 memory. Allocate at least a safe amount of 1K. */
849 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
851 sizeof(msr_list.indices[0])));
853 kvm_msr_list->nmsrs = msr_list.nmsrs;
854 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
858 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
859 if (kvm_msr_list->indices[i] == MSR_STAR) {
863 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
864 has_msr_hsave_pa = true;
867 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
868 has_msr_tsc_adjust = true;
871 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
872 has_msr_tsc_deadline = true;
875 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
876 has_msr_smbase = true;
879 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
880 has_msr_misc_enable = true;
883 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
884 has_msr_bndcfgs = true;
887 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
894 g_free(kvm_msr_list);
900 static Notifier smram_machine_done;
901 static KVMMemoryListener smram_listener;
902 static AddressSpace smram_address_space;
903 static MemoryRegion smram_as_root;
904 static MemoryRegion smram_as_mem;
906 static void register_smram_listener(Notifier *n, void *unused)
908 MemoryRegion *smram =
909 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
911 /* Outer container... */
912 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
913 memory_region_set_enabled(&smram_as_root, true);
915 /* ... with two regions inside: normal system memory with low
918 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
919 get_system_memory(), 0, ~0ull);
920 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
921 memory_region_set_enabled(&smram_as_mem, true);
924 /* ... SMRAM with higher priority */
925 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
926 memory_region_set_enabled(smram, true);
929 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
930 kvm_memory_listener_register(kvm_state, &smram_listener,
931 &smram_address_space, 1);
934 int kvm_arch_init(MachineState *ms, KVMState *s)
936 uint64_t identity_base = 0xfffbc000;
939 struct utsname utsname;
941 ret = kvm_get_supported_msrs(s);
947 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
950 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
951 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
952 * Since these must be part of guest physical memory, we need to allocate
953 * them, both by setting their start addresses in the kernel and by
954 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
956 * Older KVM versions may not support setting the identity map base. In
957 * that case we need to stick with the default, i.e. a 256K maximum BIOS
960 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
961 /* Allows up to 16M BIOSes. */
962 identity_base = 0xfeffc000;
964 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
970 /* Set TSS base one page after EPT identity map. */
971 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
976 /* Tell fw_cfg to notify the BIOS to reserve the range. */
977 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
979 fprintf(stderr, "e820_add_entry() table is full\n");
982 qemu_register_reset(kvm_unpoison_all, NULL);
984 shadow_mem = machine_kvm_shadow_mem(ms);
985 if (shadow_mem != -1) {
987 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
993 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
994 smram_machine_done.notify = register_smram_listener;
995 qemu_add_machine_init_done_notifier(&smram_machine_done);
1000 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1002 lhs->selector = rhs->selector;
1003 lhs->base = rhs->base;
1004 lhs->limit = rhs->limit;
1016 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1018 unsigned flags = rhs->flags;
1019 lhs->selector = rhs->selector;
1020 lhs->base = rhs->base;
1021 lhs->limit = rhs->limit;
1022 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1023 lhs->present = (flags & DESC_P_MASK) != 0;
1024 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1025 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1026 lhs->s = (flags & DESC_S_MASK) != 0;
1027 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1028 lhs->g = (flags & DESC_G_MASK) != 0;
1029 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1034 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1036 lhs->selector = rhs->selector;
1037 lhs->base = rhs->base;
1038 lhs->limit = rhs->limit;
1039 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1040 (rhs->present * DESC_P_MASK) |
1041 (rhs->dpl << DESC_DPL_SHIFT) |
1042 (rhs->db << DESC_B_SHIFT) |
1043 (rhs->s * DESC_S_MASK) |
1044 (rhs->l << DESC_L_SHIFT) |
1045 (rhs->g * DESC_G_MASK) |
1046 (rhs->avl * DESC_AVL_MASK);
1049 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1052 *kvm_reg = *qemu_reg;
1054 *qemu_reg = *kvm_reg;
1058 static int kvm_getput_regs(X86CPU *cpu, int set)
1060 CPUX86State *env = &cpu->env;
1061 struct kvm_regs regs;
1065 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s);
1071 kvm_getput_reg(®s.rax, &env->regs[R_EAX], set);
1072 kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set);
1073 kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set);
1074 kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set);
1075 kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set);
1076 kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set);
1077 kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set);
1078 kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set);
1079 #ifdef TARGET_X86_64
1080 kvm_getput_reg(®s.r8, &env->regs[8], set);
1081 kvm_getput_reg(®s.r9, &env->regs[9], set);
1082 kvm_getput_reg(®s.r10, &env->regs[10], set);
1083 kvm_getput_reg(®s.r11, &env->regs[11], set);
1084 kvm_getput_reg(®s.r12, &env->regs[12], set);
1085 kvm_getput_reg(®s.r13, &env->regs[13], set);
1086 kvm_getput_reg(®s.r14, &env->regs[14], set);
1087 kvm_getput_reg(®s.r15, &env->regs[15], set);
1090 kvm_getput_reg(®s.rflags, &env->eflags, set);
1091 kvm_getput_reg(®s.rip, &env->eip, set);
1094 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s);
1100 static int kvm_put_fpu(X86CPU *cpu)
1102 CPUX86State *env = &cpu->env;
1106 memset(&fpu, 0, sizeof fpu);
1107 fpu.fsw = env->fpus & ~(7 << 11);
1108 fpu.fsw |= (env->fpstt & 7) << 11;
1109 fpu.fcw = env->fpuc;
1110 fpu.last_opcode = env->fpop;
1111 fpu.last_ip = env->fpip;
1112 fpu.last_dp = env->fpdp;
1113 for (i = 0; i < 8; ++i) {
1114 fpu.ftwx |= (!env->fptags[i]) << i;
1116 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1117 for (i = 0; i < CPU_NB_REGS; i++) {
1118 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0));
1119 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1));
1121 fpu.mxcsr = env->mxcsr;
1123 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1126 #define XSAVE_FCW_FSW 0
1127 #define XSAVE_FTW_FOP 1
1128 #define XSAVE_CWD_RIP 2
1129 #define XSAVE_CWD_RDP 4
1130 #define XSAVE_MXCSR 6
1131 #define XSAVE_ST_SPACE 8
1132 #define XSAVE_XMM_SPACE 40
1133 #define XSAVE_XSTATE_BV 128
1134 #define XSAVE_YMMH_SPACE 144
1135 #define XSAVE_BNDREGS 240
1136 #define XSAVE_BNDCSR 256
1137 #define XSAVE_OPMASK 272
1138 #define XSAVE_ZMM_Hi256 288
1139 #define XSAVE_Hi16_ZMM 416
1141 static int kvm_put_xsave(X86CPU *cpu)
1143 CPUX86State *env = &cpu->env;
1144 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1145 uint16_t cwd, swd, twd;
1146 uint8_t *xmm, *ymmh, *zmmh;
1149 if (!kvm_has_xsave()) {
1150 return kvm_put_fpu(cpu);
1153 memset(xsave, 0, sizeof(struct kvm_xsave));
1155 swd = env->fpus & ~(7 << 11);
1156 swd |= (env->fpstt & 7) << 11;
1158 for (i = 0; i < 8; ++i) {
1159 twd |= (!env->fptags[i]) << i;
1161 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1162 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1163 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1164 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1165 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1166 sizeof env->fpregs);
1167 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1168 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1169 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1170 sizeof env->bnd_regs);
1171 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1172 sizeof(env->bndcs_regs));
1173 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1174 sizeof env->opmask_regs);
1176 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1177 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1178 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1179 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1180 stq_p(xmm, env->xmm_regs[i].XMM_Q(0));
1181 stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1));
1182 stq_p(ymmh, env->xmm_regs[i].XMM_Q(2));
1183 stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3));
1184 stq_p(zmmh, env->xmm_regs[i].XMM_Q(4));
1185 stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5));
1186 stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6));
1187 stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7));
1190 #ifdef TARGET_X86_64
1191 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1192 16 * sizeof env->xmm_regs[16]);
1194 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1198 static int kvm_put_xcrs(X86CPU *cpu)
1200 CPUX86State *env = &cpu->env;
1201 struct kvm_xcrs xcrs = {};
1203 if (!kvm_has_xcrs()) {
1209 xcrs.xcrs[0].xcr = 0;
1210 xcrs.xcrs[0].value = env->xcr0;
1211 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1214 static int kvm_put_sregs(X86CPU *cpu)
1216 CPUX86State *env = &cpu->env;
1217 struct kvm_sregs sregs;
1219 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1220 if (env->interrupt_injected >= 0) {
1221 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1222 (uint64_t)1 << (env->interrupt_injected % 64);
1225 if ((env->eflags & VM_MASK)) {
1226 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1227 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1228 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1229 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1230 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1231 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1233 set_seg(&sregs.cs, &env->segs[R_CS]);
1234 set_seg(&sregs.ds, &env->segs[R_DS]);
1235 set_seg(&sregs.es, &env->segs[R_ES]);
1236 set_seg(&sregs.fs, &env->segs[R_FS]);
1237 set_seg(&sregs.gs, &env->segs[R_GS]);
1238 set_seg(&sregs.ss, &env->segs[R_SS]);
1241 set_seg(&sregs.tr, &env->tr);
1242 set_seg(&sregs.ldt, &env->ldt);
1244 sregs.idt.limit = env->idt.limit;
1245 sregs.idt.base = env->idt.base;
1246 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1247 sregs.gdt.limit = env->gdt.limit;
1248 sregs.gdt.base = env->gdt.base;
1249 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1251 sregs.cr0 = env->cr[0];
1252 sregs.cr2 = env->cr[2];
1253 sregs.cr3 = env->cr[3];
1254 sregs.cr4 = env->cr[4];
1256 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1257 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1259 sregs.efer = env->efer;
1261 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1264 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1265 uint32_t index, uint64_t value)
1267 entry->index = index;
1268 entry->reserved = 0;
1269 entry->data = value;
1272 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1274 CPUX86State *env = &cpu->env;
1276 struct kvm_msrs info;
1277 struct kvm_msr_entry entries[1];
1279 struct kvm_msr_entry *msrs = msr_data.entries;
1281 if (!has_msr_tsc_deadline) {
1285 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1287 msr_data.info = (struct kvm_msrs) {
1291 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1295 * Provide a separate write service for the feature control MSR in order to
1296 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1297 * before writing any other state because forcibly leaving nested mode
1298 * invalidates the VCPU state.
1300 static int kvm_put_msr_feature_control(X86CPU *cpu)
1303 struct kvm_msrs info;
1304 struct kvm_msr_entry entry;
1307 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1308 cpu->env.msr_ia32_feature_control);
1310 msr_data.info = (struct kvm_msrs) {
1314 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1317 static int kvm_put_msrs(X86CPU *cpu, int level)
1319 CPUX86State *env = &cpu->env;
1321 struct kvm_msrs info;
1322 struct kvm_msr_entry entries[150];
1324 struct kvm_msr_entry *msrs = msr_data.entries;
1327 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1328 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1329 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1330 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1332 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1334 if (has_msr_hsave_pa) {
1335 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1337 if (has_msr_tsc_adjust) {
1338 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1340 if (has_msr_misc_enable) {
1341 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1342 env->msr_ia32_misc_enable);
1344 if (has_msr_smbase) {
1345 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1347 if (has_msr_bndcfgs) {
1348 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1351 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1353 #ifdef TARGET_X86_64
1354 if (lm_capable_kernel) {
1355 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1356 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1357 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1358 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1362 * The following MSRs have side effects on the guest or are too heavy
1363 * for normal writeback. Limit them to reset or full state updates.
1365 if (level >= KVM_PUT_RESET_STATE) {
1366 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1367 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1368 env->system_time_msr);
1369 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1370 if (has_msr_async_pf_en) {
1371 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1372 env->async_pf_en_msr);
1374 if (has_msr_pv_eoi_en) {
1375 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1376 env->pv_eoi_en_msr);
1378 if (has_msr_kvm_steal_time) {
1379 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1380 env->steal_time_msr);
1382 if (has_msr_architectural_pmu) {
1383 /* Stop the counter. */
1384 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1385 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1387 /* Set the counter values. */
1388 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1389 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1390 env->msr_fixed_counters[i]);
1392 for (i = 0; i < num_architectural_pmu_counters; i++) {
1393 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1394 env->msr_gp_counters[i]);
1395 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1396 env->msr_gp_evtsel[i]);
1398 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1399 env->msr_global_status);
1400 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1401 env->msr_global_ovf_ctrl);
1403 /* Now start the PMU. */
1404 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1405 env->msr_fixed_ctr_ctrl);
1406 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1407 env->msr_global_ctrl);
1409 if (has_msr_hv_hypercall) {
1410 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1411 env->msr_hv_guest_os_id);
1412 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1413 env->msr_hv_hypercall);
1415 if (has_msr_hv_vapic) {
1416 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1419 if (has_msr_hv_tsc) {
1420 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1424 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1425 kvm_msr_entry_set(&msrs[n++],
1426 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1427 kvm_msr_entry_set(&msrs[n++],
1428 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1429 kvm_msr_entry_set(&msrs[n++],
1430 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1431 kvm_msr_entry_set(&msrs[n++],
1432 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1433 kvm_msr_entry_set(&msrs[n++],
1434 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1435 kvm_msr_entry_set(&msrs[n++],
1436 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1437 kvm_msr_entry_set(&msrs[n++],
1438 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1439 kvm_msr_entry_set(&msrs[n++],
1440 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1441 kvm_msr_entry_set(&msrs[n++],
1442 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1443 kvm_msr_entry_set(&msrs[n++],
1444 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1445 kvm_msr_entry_set(&msrs[n++],
1446 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1447 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1448 kvm_msr_entry_set(&msrs[n++],
1449 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1450 kvm_msr_entry_set(&msrs[n++],
1451 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1455 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1456 * kvm_put_msr_feature_control. */
1461 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1462 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1463 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1464 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1468 msr_data.info = (struct kvm_msrs) {
1472 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1477 static int kvm_get_fpu(X86CPU *cpu)
1479 CPUX86State *env = &cpu->env;
1483 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1488 env->fpstt = (fpu.fsw >> 11) & 7;
1489 env->fpus = fpu.fsw;
1490 env->fpuc = fpu.fcw;
1491 env->fpop = fpu.last_opcode;
1492 env->fpip = fpu.last_ip;
1493 env->fpdp = fpu.last_dp;
1494 for (i = 0; i < 8; ++i) {
1495 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1497 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1498 for (i = 0; i < CPU_NB_REGS; i++) {
1499 env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1500 env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1502 env->mxcsr = fpu.mxcsr;
1507 static int kvm_get_xsave(X86CPU *cpu)
1509 CPUX86State *env = &cpu->env;
1510 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1512 const uint8_t *xmm, *ymmh, *zmmh;
1513 uint16_t cwd, swd, twd;
1515 if (!kvm_has_xsave()) {
1516 return kvm_get_fpu(cpu);
1519 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1524 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1525 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1526 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1527 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1528 env->fpstt = (swd >> 11) & 7;
1531 for (i = 0; i < 8; ++i) {
1532 env->fptags[i] = !((twd >> i) & 1);
1534 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1535 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1536 env->mxcsr = xsave->region[XSAVE_MXCSR];
1537 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1538 sizeof env->fpregs);
1539 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1540 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1541 sizeof env->bnd_regs);
1542 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1543 sizeof(env->bndcs_regs));
1544 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1545 sizeof env->opmask_regs);
1547 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1548 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1549 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1550 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1551 env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm);
1552 env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8);
1553 env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh);
1554 env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8);
1555 env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh);
1556 env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8);
1557 env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16);
1558 env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24);
1561 #ifdef TARGET_X86_64
1562 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1563 16 * sizeof env->xmm_regs[16]);
1568 static int kvm_get_xcrs(X86CPU *cpu)
1570 CPUX86State *env = &cpu->env;
1572 struct kvm_xcrs xcrs;
1574 if (!kvm_has_xcrs()) {
1578 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1583 for (i = 0; i < xcrs.nr_xcrs; i++) {
1584 /* Only support xcr0 now */
1585 if (xcrs.xcrs[i].xcr == 0) {
1586 env->xcr0 = xcrs.xcrs[i].value;
1593 static int kvm_get_sregs(X86CPU *cpu)
1595 CPUX86State *env = &cpu->env;
1596 struct kvm_sregs sregs;
1600 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1605 /* There can only be one pending IRQ set in the bitmap at a time, so try
1606 to find it and save its number instead (-1 for none). */
1607 env->interrupt_injected = -1;
1608 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1609 if (sregs.interrupt_bitmap[i]) {
1610 bit = ctz64(sregs.interrupt_bitmap[i]);
1611 env->interrupt_injected = i * 64 + bit;
1616 get_seg(&env->segs[R_CS], &sregs.cs);
1617 get_seg(&env->segs[R_DS], &sregs.ds);
1618 get_seg(&env->segs[R_ES], &sregs.es);
1619 get_seg(&env->segs[R_FS], &sregs.fs);
1620 get_seg(&env->segs[R_GS], &sregs.gs);
1621 get_seg(&env->segs[R_SS], &sregs.ss);
1623 get_seg(&env->tr, &sregs.tr);
1624 get_seg(&env->ldt, &sregs.ldt);
1626 env->idt.limit = sregs.idt.limit;
1627 env->idt.base = sregs.idt.base;
1628 env->gdt.limit = sregs.gdt.limit;
1629 env->gdt.base = sregs.gdt.base;
1631 env->cr[0] = sregs.cr0;
1632 env->cr[2] = sregs.cr2;
1633 env->cr[3] = sregs.cr3;
1634 env->cr[4] = sregs.cr4;
1636 env->efer = sregs.efer;
1638 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1640 #define HFLAG_COPY_MASK \
1641 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1642 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1643 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1644 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1646 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1647 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1648 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1649 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1650 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1651 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1652 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1654 if (env->efer & MSR_EFER_LMA) {
1655 hflags |= HF_LMA_MASK;
1658 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1659 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1661 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1662 (DESC_B_SHIFT - HF_CS32_SHIFT);
1663 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1664 (DESC_B_SHIFT - HF_SS32_SHIFT);
1665 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1666 !(hflags & HF_CS32_MASK)) {
1667 hflags |= HF_ADDSEG_MASK;
1669 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1670 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1673 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1678 static int kvm_get_msrs(X86CPU *cpu)
1680 CPUX86State *env = &cpu->env;
1682 struct kvm_msrs info;
1683 struct kvm_msr_entry entries[150];
1685 struct kvm_msr_entry *msrs = msr_data.entries;
1689 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1690 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1691 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1692 msrs[n++].index = MSR_PAT;
1694 msrs[n++].index = MSR_STAR;
1696 if (has_msr_hsave_pa) {
1697 msrs[n++].index = MSR_VM_HSAVE_PA;
1699 if (has_msr_tsc_adjust) {
1700 msrs[n++].index = MSR_TSC_ADJUST;
1702 if (has_msr_tsc_deadline) {
1703 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1705 if (has_msr_misc_enable) {
1706 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1708 if (has_msr_smbase) {
1709 msrs[n++].index = MSR_IA32_SMBASE;
1711 if (has_msr_feature_control) {
1712 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1714 if (has_msr_bndcfgs) {
1715 msrs[n++].index = MSR_IA32_BNDCFGS;
1718 msrs[n++].index = MSR_IA32_XSS;
1722 if (!env->tsc_valid) {
1723 msrs[n++].index = MSR_IA32_TSC;
1724 env->tsc_valid = !runstate_is_running();
1727 #ifdef TARGET_X86_64
1728 if (lm_capable_kernel) {
1729 msrs[n++].index = MSR_CSTAR;
1730 msrs[n++].index = MSR_KERNELGSBASE;
1731 msrs[n++].index = MSR_FMASK;
1732 msrs[n++].index = MSR_LSTAR;
1735 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1736 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1737 if (has_msr_async_pf_en) {
1738 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1740 if (has_msr_pv_eoi_en) {
1741 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1743 if (has_msr_kvm_steal_time) {
1744 msrs[n++].index = MSR_KVM_STEAL_TIME;
1746 if (has_msr_architectural_pmu) {
1747 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1748 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1749 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1750 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1751 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1752 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1754 for (i = 0; i < num_architectural_pmu_counters; i++) {
1755 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1756 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1761 msrs[n++].index = MSR_MCG_STATUS;
1762 msrs[n++].index = MSR_MCG_CTL;
1763 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1764 msrs[n++].index = MSR_MC0_CTL + i;
1768 if (has_msr_hv_hypercall) {
1769 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1770 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1772 if (has_msr_hv_vapic) {
1773 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1775 if (has_msr_hv_tsc) {
1776 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1779 msrs[n++].index = MSR_MTRRdefType;
1780 msrs[n++].index = MSR_MTRRfix64K_00000;
1781 msrs[n++].index = MSR_MTRRfix16K_80000;
1782 msrs[n++].index = MSR_MTRRfix16K_A0000;
1783 msrs[n++].index = MSR_MTRRfix4K_C0000;
1784 msrs[n++].index = MSR_MTRRfix4K_C8000;
1785 msrs[n++].index = MSR_MTRRfix4K_D0000;
1786 msrs[n++].index = MSR_MTRRfix4K_D8000;
1787 msrs[n++].index = MSR_MTRRfix4K_E0000;
1788 msrs[n++].index = MSR_MTRRfix4K_E8000;
1789 msrs[n++].index = MSR_MTRRfix4K_F0000;
1790 msrs[n++].index = MSR_MTRRfix4K_F8000;
1791 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1792 msrs[n++].index = MSR_MTRRphysBase(i);
1793 msrs[n++].index = MSR_MTRRphysMask(i);
1797 msr_data.info = (struct kvm_msrs) {
1801 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1806 for (i = 0; i < ret; i++) {
1807 uint32_t index = msrs[i].index;
1809 case MSR_IA32_SYSENTER_CS:
1810 env->sysenter_cs = msrs[i].data;
1812 case MSR_IA32_SYSENTER_ESP:
1813 env->sysenter_esp = msrs[i].data;
1815 case MSR_IA32_SYSENTER_EIP:
1816 env->sysenter_eip = msrs[i].data;
1819 env->pat = msrs[i].data;
1822 env->star = msrs[i].data;
1824 #ifdef TARGET_X86_64
1826 env->cstar = msrs[i].data;
1828 case MSR_KERNELGSBASE:
1829 env->kernelgsbase = msrs[i].data;
1832 env->fmask = msrs[i].data;
1835 env->lstar = msrs[i].data;
1839 env->tsc = msrs[i].data;
1841 case MSR_TSC_ADJUST:
1842 env->tsc_adjust = msrs[i].data;
1844 case MSR_IA32_TSCDEADLINE:
1845 env->tsc_deadline = msrs[i].data;
1847 case MSR_VM_HSAVE_PA:
1848 env->vm_hsave = msrs[i].data;
1850 case MSR_KVM_SYSTEM_TIME:
1851 env->system_time_msr = msrs[i].data;
1853 case MSR_KVM_WALL_CLOCK:
1854 env->wall_clock_msr = msrs[i].data;
1856 case MSR_MCG_STATUS:
1857 env->mcg_status = msrs[i].data;
1860 env->mcg_ctl = msrs[i].data;
1862 case MSR_IA32_MISC_ENABLE:
1863 env->msr_ia32_misc_enable = msrs[i].data;
1865 case MSR_IA32_SMBASE:
1866 env->smbase = msrs[i].data;
1868 case MSR_IA32_FEATURE_CONTROL:
1869 env->msr_ia32_feature_control = msrs[i].data;
1871 case MSR_IA32_BNDCFGS:
1872 env->msr_bndcfgs = msrs[i].data;
1875 env->xss = msrs[i].data;
1878 if (msrs[i].index >= MSR_MC0_CTL &&
1879 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1880 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1883 case MSR_KVM_ASYNC_PF_EN:
1884 env->async_pf_en_msr = msrs[i].data;
1886 case MSR_KVM_PV_EOI_EN:
1887 env->pv_eoi_en_msr = msrs[i].data;
1889 case MSR_KVM_STEAL_TIME:
1890 env->steal_time_msr = msrs[i].data;
1892 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1893 env->msr_fixed_ctr_ctrl = msrs[i].data;
1895 case MSR_CORE_PERF_GLOBAL_CTRL:
1896 env->msr_global_ctrl = msrs[i].data;
1898 case MSR_CORE_PERF_GLOBAL_STATUS:
1899 env->msr_global_status = msrs[i].data;
1901 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1902 env->msr_global_ovf_ctrl = msrs[i].data;
1904 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1905 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1907 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1908 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1910 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1911 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1913 case HV_X64_MSR_HYPERCALL:
1914 env->msr_hv_hypercall = msrs[i].data;
1916 case HV_X64_MSR_GUEST_OS_ID:
1917 env->msr_hv_guest_os_id = msrs[i].data;
1919 case HV_X64_MSR_APIC_ASSIST_PAGE:
1920 env->msr_hv_vapic = msrs[i].data;
1922 case HV_X64_MSR_REFERENCE_TSC:
1923 env->msr_hv_tsc = msrs[i].data;
1925 case MSR_MTRRdefType:
1926 env->mtrr_deftype = msrs[i].data;
1928 case MSR_MTRRfix64K_00000:
1929 env->mtrr_fixed[0] = msrs[i].data;
1931 case MSR_MTRRfix16K_80000:
1932 env->mtrr_fixed[1] = msrs[i].data;
1934 case MSR_MTRRfix16K_A0000:
1935 env->mtrr_fixed[2] = msrs[i].data;
1937 case MSR_MTRRfix4K_C0000:
1938 env->mtrr_fixed[3] = msrs[i].data;
1940 case MSR_MTRRfix4K_C8000:
1941 env->mtrr_fixed[4] = msrs[i].data;
1943 case MSR_MTRRfix4K_D0000:
1944 env->mtrr_fixed[5] = msrs[i].data;
1946 case MSR_MTRRfix4K_D8000:
1947 env->mtrr_fixed[6] = msrs[i].data;
1949 case MSR_MTRRfix4K_E0000:
1950 env->mtrr_fixed[7] = msrs[i].data;
1952 case MSR_MTRRfix4K_E8000:
1953 env->mtrr_fixed[8] = msrs[i].data;
1955 case MSR_MTRRfix4K_F0000:
1956 env->mtrr_fixed[9] = msrs[i].data;
1958 case MSR_MTRRfix4K_F8000:
1959 env->mtrr_fixed[10] = msrs[i].data;
1961 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
1963 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
1965 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
1974 static int kvm_put_mp_state(X86CPU *cpu)
1976 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1978 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1981 static int kvm_get_mp_state(X86CPU *cpu)
1983 CPUState *cs = CPU(cpu);
1984 CPUX86State *env = &cpu->env;
1985 struct kvm_mp_state mp_state;
1988 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1992 env->mp_state = mp_state.mp_state;
1993 if (kvm_irqchip_in_kernel()) {
1994 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1999 static int kvm_get_apic(X86CPU *cpu)
2001 DeviceState *apic = cpu->apic_state;
2002 struct kvm_lapic_state kapic;
2005 if (apic && kvm_irqchip_in_kernel()) {
2006 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2011 kvm_get_apic_state(apic, &kapic);
2016 static int kvm_put_apic(X86CPU *cpu)
2018 DeviceState *apic = cpu->apic_state;
2019 struct kvm_lapic_state kapic;
2021 if (apic && kvm_irqchip_in_kernel()) {
2022 kvm_put_apic_state(apic, &kapic);
2024 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
2029 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2031 CPUState *cs = CPU(cpu);
2032 CPUX86State *env = &cpu->env;
2033 struct kvm_vcpu_events events = {};
2035 if (!kvm_has_vcpu_events()) {
2039 events.exception.injected = (env->exception_injected >= 0);
2040 events.exception.nr = env->exception_injected;
2041 events.exception.has_error_code = env->has_error_code;
2042 events.exception.error_code = env->error_code;
2043 events.exception.pad = 0;
2045 events.interrupt.injected = (env->interrupt_injected >= 0);
2046 events.interrupt.nr = env->interrupt_injected;
2047 events.interrupt.soft = env->soft_interrupt;
2049 events.nmi.injected = env->nmi_injected;
2050 events.nmi.pending = env->nmi_pending;
2051 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2054 events.sipi_vector = env->sipi_vector;
2056 if (has_msr_smbase) {
2057 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2058 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2059 if (kvm_irqchip_in_kernel()) {
2060 /* As soon as these are moved to the kernel, remove them
2061 * from cs->interrupt_request.
2063 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2064 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2065 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2067 /* Keep these in cs->interrupt_request. */
2068 events.smi.pending = 0;
2069 events.smi.latched_init = 0;
2071 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2075 if (level >= KVM_PUT_RESET_STATE) {
2077 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2080 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2083 static int kvm_get_vcpu_events(X86CPU *cpu)
2085 CPUX86State *env = &cpu->env;
2086 struct kvm_vcpu_events events;
2089 if (!kvm_has_vcpu_events()) {
2093 memset(&events, 0, sizeof(events));
2094 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2098 env->exception_injected =
2099 events.exception.injected ? events.exception.nr : -1;
2100 env->has_error_code = events.exception.has_error_code;
2101 env->error_code = events.exception.error_code;
2103 env->interrupt_injected =
2104 events.interrupt.injected ? events.interrupt.nr : -1;
2105 env->soft_interrupt = events.interrupt.soft;
2107 env->nmi_injected = events.nmi.injected;
2108 env->nmi_pending = events.nmi.pending;
2109 if (events.nmi.masked) {
2110 env->hflags2 |= HF2_NMI_MASK;
2112 env->hflags2 &= ~HF2_NMI_MASK;
2115 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2116 if (events.smi.smm) {
2117 env->hflags |= HF_SMM_MASK;
2119 env->hflags &= ~HF_SMM_MASK;
2121 if (events.smi.pending) {
2122 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2124 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2126 if (events.smi.smm_inside_nmi) {
2127 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2129 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2131 if (events.smi.latched_init) {
2132 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2134 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2138 env->sipi_vector = events.sipi_vector;
2143 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2145 CPUState *cs = CPU(cpu);
2146 CPUX86State *env = &cpu->env;
2148 unsigned long reinject_trap = 0;
2150 if (!kvm_has_vcpu_events()) {
2151 if (env->exception_injected == 1) {
2152 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2153 } else if (env->exception_injected == 3) {
2154 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2156 env->exception_injected = -1;
2160 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2161 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2162 * by updating the debug state once again if single-stepping is on.
2163 * Another reason to call kvm_update_guest_debug here is a pending debug
2164 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2165 * reinject them via SET_GUEST_DEBUG.
2167 if (reinject_trap ||
2168 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2169 ret = kvm_update_guest_debug(cs, reinject_trap);
2174 static int kvm_put_debugregs(X86CPU *cpu)
2176 CPUX86State *env = &cpu->env;
2177 struct kvm_debugregs dbgregs;
2180 if (!kvm_has_debugregs()) {
2184 for (i = 0; i < 4; i++) {
2185 dbgregs.db[i] = env->dr[i];
2187 dbgregs.dr6 = env->dr[6];
2188 dbgregs.dr7 = env->dr[7];
2191 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2194 static int kvm_get_debugregs(X86CPU *cpu)
2196 CPUX86State *env = &cpu->env;
2197 struct kvm_debugregs dbgregs;
2200 if (!kvm_has_debugregs()) {
2204 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2208 for (i = 0; i < 4; i++) {
2209 env->dr[i] = dbgregs.db[i];
2211 env->dr[4] = env->dr[6] = dbgregs.dr6;
2212 env->dr[5] = env->dr[7] = dbgregs.dr7;
2217 int kvm_arch_put_registers(CPUState *cpu, int level)
2219 X86CPU *x86_cpu = X86_CPU(cpu);
2222 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2224 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2225 ret = kvm_put_msr_feature_control(x86_cpu);
2231 ret = kvm_getput_regs(x86_cpu, 1);
2235 ret = kvm_put_xsave(x86_cpu);
2239 ret = kvm_put_xcrs(x86_cpu);
2243 ret = kvm_put_sregs(x86_cpu);
2247 /* must be before kvm_put_msrs */
2248 ret = kvm_inject_mce_oldstyle(x86_cpu);
2252 ret = kvm_put_msrs(x86_cpu, level);
2256 if (level >= KVM_PUT_RESET_STATE) {
2257 ret = kvm_put_mp_state(x86_cpu);
2261 ret = kvm_put_apic(x86_cpu);
2267 ret = kvm_put_tscdeadline_msr(x86_cpu);
2272 ret = kvm_put_vcpu_events(x86_cpu, level);
2276 ret = kvm_put_debugregs(x86_cpu);
2281 ret = kvm_guest_debug_workarounds(x86_cpu);
2288 int kvm_arch_get_registers(CPUState *cs)
2290 X86CPU *cpu = X86_CPU(cs);
2293 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2295 ret = kvm_getput_regs(cpu, 0);
2299 ret = kvm_get_xsave(cpu);
2303 ret = kvm_get_xcrs(cpu);
2307 ret = kvm_get_sregs(cpu);
2311 ret = kvm_get_msrs(cpu);
2315 ret = kvm_get_mp_state(cpu);
2319 ret = kvm_get_apic(cpu);
2323 ret = kvm_get_vcpu_events(cpu);
2327 ret = kvm_get_debugregs(cpu);
2334 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2336 X86CPU *x86_cpu = X86_CPU(cpu);
2337 CPUX86State *env = &x86_cpu->env;
2341 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2342 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2343 qemu_mutex_lock_iothread();
2344 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2345 qemu_mutex_unlock_iothread();
2346 DPRINTF("injected NMI\n");
2347 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2349 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2353 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2354 qemu_mutex_lock_iothread();
2355 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2356 qemu_mutex_unlock_iothread();
2357 DPRINTF("injected SMI\n");
2358 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2360 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2366 if (!kvm_irqchip_in_kernel()) {
2367 qemu_mutex_lock_iothread();
2370 /* Force the VCPU out of its inner loop to process any INIT requests
2371 * or (for userspace APIC, but it is cheap to combine the checks here)
2372 * pending TPR access reports.
2374 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2375 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2376 !(env->hflags & HF_SMM_MASK)) {
2377 cpu->exit_request = 1;
2379 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2380 cpu->exit_request = 1;
2384 if (!kvm_irqchip_in_kernel()) {
2385 /* Try to inject an interrupt if the guest can accept it */
2386 if (run->ready_for_interrupt_injection &&
2387 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2388 (env->eflags & IF_MASK)) {
2391 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2392 irq = cpu_get_pic_interrupt(env);
2394 struct kvm_interrupt intr;
2397 DPRINTF("injected interrupt %d\n", irq);
2398 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2401 "KVM: injection failed, interrupt lost (%s)\n",
2407 /* If we have an interrupt but the guest is not ready to receive an
2408 * interrupt, request an interrupt window exit. This will
2409 * cause a return to userspace as soon as the guest is ready to
2410 * receive interrupts. */
2411 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2412 run->request_interrupt_window = 1;
2414 run->request_interrupt_window = 0;
2417 DPRINTF("setting tpr\n");
2418 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2420 qemu_mutex_unlock_iothread();
2424 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2426 X86CPU *x86_cpu = X86_CPU(cpu);
2427 CPUX86State *env = &x86_cpu->env;
2429 if (run->flags & KVM_RUN_X86_SMM) {
2430 env->hflags |= HF_SMM_MASK;
2432 env->hflags &= HF_SMM_MASK;
2435 env->eflags |= IF_MASK;
2437 env->eflags &= ~IF_MASK;
2440 /* We need to protect the apic state against concurrent accesses from
2441 * different threads in case the userspace irqchip is used. */
2442 if (!kvm_irqchip_in_kernel()) {
2443 qemu_mutex_lock_iothread();
2445 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2446 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2447 if (!kvm_irqchip_in_kernel()) {
2448 qemu_mutex_unlock_iothread();
2450 return cpu_get_mem_attrs(env);
2453 int kvm_arch_process_async_events(CPUState *cs)
2455 X86CPU *cpu = X86_CPU(cs);
2456 CPUX86State *env = &cpu->env;
2458 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2459 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2460 assert(env->mcg_cap);
2462 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2464 kvm_cpu_synchronize_state(cs);
2466 if (env->exception_injected == EXCP08_DBLE) {
2467 /* this means triple fault */
2468 qemu_system_reset_request();
2469 cs->exit_request = 1;
2472 env->exception_injected = EXCP12_MCHK;
2473 env->has_error_code = 0;
2476 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2477 env->mp_state = KVM_MP_STATE_RUNNABLE;
2481 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2482 !(env->hflags & HF_SMM_MASK)) {
2483 kvm_cpu_synchronize_state(cs);
2487 if (kvm_irqchip_in_kernel()) {
2491 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2492 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2493 apic_poll_irq(cpu->apic_state);
2495 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2496 (env->eflags & IF_MASK)) ||
2497 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2500 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2501 kvm_cpu_synchronize_state(cs);
2504 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2505 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2506 kvm_cpu_synchronize_state(cs);
2507 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2508 env->tpr_access_type);
2514 static int kvm_handle_halt(X86CPU *cpu)
2516 CPUState *cs = CPU(cpu);
2517 CPUX86State *env = &cpu->env;
2519 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2520 (env->eflags & IF_MASK)) &&
2521 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2529 static int kvm_handle_tpr_access(X86CPU *cpu)
2531 CPUState *cs = CPU(cpu);
2532 struct kvm_run *run = cs->kvm_run;
2534 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2535 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2540 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2542 static const uint8_t int3 = 0xcc;
2544 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2545 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2551 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2555 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2556 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2568 static int nb_hw_breakpoint;
2570 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2574 for (n = 0; n < nb_hw_breakpoint; n++) {
2575 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2576 (hw_breakpoint[n].len == len || len == -1)) {
2583 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2584 target_ulong len, int type)
2587 case GDB_BREAKPOINT_HW:
2590 case GDB_WATCHPOINT_WRITE:
2591 case GDB_WATCHPOINT_ACCESS:
2598 if (addr & (len - 1)) {
2610 if (nb_hw_breakpoint == 4) {
2613 if (find_hw_breakpoint(addr, len, type) >= 0) {
2616 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2617 hw_breakpoint[nb_hw_breakpoint].len = len;
2618 hw_breakpoint[nb_hw_breakpoint].type = type;
2624 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2625 target_ulong len, int type)
2629 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2634 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2639 void kvm_arch_remove_all_hw_breakpoints(void)
2641 nb_hw_breakpoint = 0;
2644 static CPUWatchpoint hw_watchpoint;
2646 static int kvm_handle_debug(X86CPU *cpu,
2647 struct kvm_debug_exit_arch *arch_info)
2649 CPUState *cs = CPU(cpu);
2650 CPUX86State *env = &cpu->env;
2654 if (arch_info->exception == 1) {
2655 if (arch_info->dr6 & (1 << 14)) {
2656 if (cs->singlestep_enabled) {
2660 for (n = 0; n < 4; n++) {
2661 if (arch_info->dr6 & (1 << n)) {
2662 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2668 cs->watchpoint_hit = &hw_watchpoint;
2669 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2670 hw_watchpoint.flags = BP_MEM_WRITE;
2674 cs->watchpoint_hit = &hw_watchpoint;
2675 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2676 hw_watchpoint.flags = BP_MEM_ACCESS;
2682 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2686 cpu_synchronize_state(cs);
2687 assert(env->exception_injected == -1);
2690 env->exception_injected = arch_info->exception;
2691 env->has_error_code = 0;
2697 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2699 const uint8_t type_code[] = {
2700 [GDB_BREAKPOINT_HW] = 0x0,
2701 [GDB_WATCHPOINT_WRITE] = 0x1,
2702 [GDB_WATCHPOINT_ACCESS] = 0x3
2704 const uint8_t len_code[] = {
2705 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2709 if (kvm_sw_breakpoints_active(cpu)) {
2710 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2712 if (nb_hw_breakpoint > 0) {
2713 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2714 dbg->arch.debugreg[7] = 0x0600;
2715 for (n = 0; n < nb_hw_breakpoint; n++) {
2716 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2717 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2718 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2719 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2724 static bool host_supports_vmx(void)
2726 uint32_t ecx, unused;
2728 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2729 return ecx & CPUID_EXT_VMX;
2732 #define VMX_INVALID_GUEST_STATE 0x80000021
2734 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2736 X86CPU *cpu = X86_CPU(cs);
2740 switch (run->exit_reason) {
2742 DPRINTF("handle_hlt\n");
2743 qemu_mutex_lock_iothread();
2744 ret = kvm_handle_halt(cpu);
2745 qemu_mutex_unlock_iothread();
2747 case KVM_EXIT_SET_TPR:
2750 case KVM_EXIT_TPR_ACCESS:
2751 qemu_mutex_lock_iothread();
2752 ret = kvm_handle_tpr_access(cpu);
2753 qemu_mutex_unlock_iothread();
2755 case KVM_EXIT_FAIL_ENTRY:
2756 code = run->fail_entry.hardware_entry_failure_reason;
2757 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2759 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2761 "\nIf you're running a guest on an Intel machine without "
2762 "unrestricted mode\n"
2763 "support, the failure can be most likely due to the guest "
2764 "entering an invalid\n"
2765 "state for Intel VT. For example, the guest maybe running "
2766 "in big real mode\n"
2767 "which is not supported on less recent Intel processors."
2772 case KVM_EXIT_EXCEPTION:
2773 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2774 run->ex.exception, run->ex.error_code);
2777 case KVM_EXIT_DEBUG:
2778 DPRINTF("kvm_exit_debug\n");
2779 qemu_mutex_lock_iothread();
2780 ret = kvm_handle_debug(cpu, &run->debug.arch);
2781 qemu_mutex_unlock_iothread();
2784 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2792 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2794 X86CPU *cpu = X86_CPU(cs);
2795 CPUX86State *env = &cpu->env;
2797 kvm_cpu_synchronize_state(cs);
2798 return !(env->cr[0] & CR0_PE_MASK) ||
2799 ((env->segs[R_CS].selector & 3) != 3);
2802 void kvm_arch_init_irq_routing(KVMState *s)
2804 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2805 /* If kernel can't do irq routing, interrupt source
2806 * override 0->2 cannot be set up as required by HPET.
2807 * So we have to disable it.
2811 /* We know at this point that we're using the in-kernel
2812 * irqchip, so we can use irqfds, and on x86 we know
2813 * we can use msi via irqfd and GSI routing.
2815 kvm_msi_via_irqfd_allowed = true;
2816 kvm_gsi_routing_allowed = true;
2819 /* Classic KVM device assignment interface. Will remain x86 only. */
2820 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2821 uint32_t flags, uint32_t *dev_id)
2823 struct kvm_assigned_pci_dev dev_data = {
2824 .segnr = dev_addr->domain,
2825 .busnr = dev_addr->bus,
2826 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2831 dev_data.assigned_dev_id =
2832 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2834 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2839 *dev_id = dev_data.assigned_dev_id;
2844 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2846 struct kvm_assigned_pci_dev dev_data = {
2847 .assigned_dev_id = dev_id,
2850 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2853 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2854 uint32_t irq_type, uint32_t guest_irq)
2856 struct kvm_assigned_irq assigned_irq = {
2857 .assigned_dev_id = dev_id,
2858 .guest_irq = guest_irq,
2862 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2863 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2865 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2869 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2872 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2873 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2875 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2878 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2880 struct kvm_assigned_pci_dev dev_data = {
2881 .assigned_dev_id = dev_id,
2882 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2885 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2888 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2891 struct kvm_assigned_irq assigned_irq = {
2892 .assigned_dev_id = dev_id,
2896 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2899 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2901 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2902 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2905 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2907 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2908 KVM_DEV_IRQ_GUEST_MSI, virq);
2911 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2913 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2914 KVM_DEV_IRQ_HOST_MSI);
2917 bool kvm_device_msix_supported(KVMState *s)
2919 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2920 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2921 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2924 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2925 uint32_t nr_vectors)
2927 struct kvm_assigned_msix_nr msix_nr = {
2928 .assigned_dev_id = dev_id,
2929 .entry_nr = nr_vectors,
2932 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2935 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2938 struct kvm_assigned_msix_entry msix_entry = {
2939 .assigned_dev_id = dev_id,
2944 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2947 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2949 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2950 KVM_DEV_IRQ_GUEST_MSIX, 0);
2953 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2955 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2956 KVM_DEV_IRQ_HOST_MSIX);
2959 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
2960 uint64_t address, uint32_t data)
2965 int kvm_arch_msi_data_to_gsi(uint32_t data)