2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 * The condition code translation is in need of attention.
27 #include "disas/disas.h"
29 #include "exec/helper-proto.h"
31 #include "exec/cpu_ldst.h"
32 #include "crisv32-decode.h"
34 #include "exec/helper-gen.h"
36 #include "trace-tcg.h"
41 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 # define LOG_DIS(...) do { } while (0)
47 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
48 #define BUG_ON(x) ({if (x) BUG();})
52 /* Used by the decoder. */
53 #define EXTRACT_FIELD(src, start, end) \
54 (((src) >> start) & ((1 << (end - start + 1)) - 1))
56 #define CC_MASK_NZ 0xc
57 #define CC_MASK_NZV 0xe
58 #define CC_MASK_NZVC 0xf
59 #define CC_MASK_RNZV 0x10e
61 static TCGv_ptr cpu_env;
62 static TCGv cpu_R[16];
63 static TCGv cpu_PR[16];
67 static TCGv cc_result;
72 static TCGv env_btaken;
73 static TCGv env_btarget;
76 #include "exec/gen-icount.h"
78 /* This is the state at translation time. */
79 typedef struct DisasContext {
84 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
89 unsigned int zsize, zzsize;
103 int cc_size_uptodate; /* -1 invalid or last written value. */
105 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
106 int flags_uptodate; /* Wether or not $ccs is uptodate. */
107 int flagx_known; /* Wether or not flags_x has the x flag known at
111 int clear_x; /* Clear x after this insn? */
112 int clear_prefix; /* Clear prefix after this insn? */
113 int clear_locked_irq; /* Clear the irq lockout. */
114 int cpustate_changed;
115 unsigned int tb_flags; /* tb dependent flags. */
120 #define JMP_DIRECT_CC 2
121 #define JMP_INDIRECT 3
122 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
127 struct TranslationBlock *tb;
128 int singlestep_enabled;
131 static void gen_BUG(DisasContext *dc, const char *file, int line)
133 printf("BUG: pc=%x %s %d\n", dc->pc, file, line);
134 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
135 cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line);
138 static const char *regnames[] =
140 "$r0", "$r1", "$r2", "$r3",
141 "$r4", "$r5", "$r6", "$r7",
142 "$r8", "$r9", "$r10", "$r11",
143 "$r12", "$r13", "$sp", "$acr",
145 static const char *pregnames[] =
147 "$bz", "$vr", "$pid", "$srs",
148 "$wz", "$exs", "$eda", "$mof",
149 "$dz", "$ebp", "$erp", "$srp",
150 "$nrp", "$ccs", "$usp", "$spc",
153 /* We need this table to handle preg-moves with implicit width. */
154 static int preg_sizes[] = {
165 #define t_gen_mov_TN_env(tn, member) \
166 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
167 #define t_gen_mov_env_TN(member, tn) \
168 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
170 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
172 assert(r >= 0 && r <= 15);
173 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
174 tcg_gen_mov_tl(tn, tcg_const_tl(0));
175 } else if (r == PR_VR) {
176 tcg_gen_mov_tl(tn, tcg_const_tl(32));
178 tcg_gen_mov_tl(tn, cpu_PR[r]);
181 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
183 assert(r >= 0 && r <= 15);
184 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
186 } else if (r == PR_SRS) {
187 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
190 gen_helper_tlb_flush_pid(cpu_env, tn);
192 if (dc->tb_flags & S_FLAG && r == PR_SPC) {
193 gen_helper_spc_write(cpu_env, tn);
194 } else if (r == PR_CCS) {
195 dc->cpustate_changed = 1;
197 tcg_gen_mov_tl(cpu_PR[r], tn);
201 /* Sign extend at translation time. */
202 static int sign_extend(unsigned int val, unsigned int width)
214 static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
215 unsigned int size, unsigned int sign)
222 r = cpu_ldl_code(env, addr);
228 r = cpu_ldsw_code(env, addr);
230 r = cpu_lduw_code(env, addr);
237 r = cpu_ldsb_code(env, addr);
239 r = cpu_ldub_code(env, addr);
244 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
250 static void cris_lock_irq(DisasContext *dc)
252 dc->clear_locked_irq = 0;
253 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
256 static inline void t_gen_raise_exception(uint32_t index)
258 TCGv_i32 tmp = tcg_const_i32(index);
259 gen_helper_raise_exception(cpu_env, tmp);
260 tcg_temp_free_i32(tmp);
263 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
268 t_31 = tcg_const_tl(31);
269 tcg_gen_shl_tl(d, a, b);
271 tcg_gen_sub_tl(t0, t_31, b);
272 tcg_gen_sar_tl(t0, t0, t_31);
273 tcg_gen_and_tl(t0, t0, d);
274 tcg_gen_xor_tl(d, d, t0);
279 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
284 t_31 = tcg_temp_new();
285 tcg_gen_shr_tl(d, a, b);
287 tcg_gen_movi_tl(t_31, 31);
288 tcg_gen_sub_tl(t0, t_31, b);
289 tcg_gen_sar_tl(t0, t0, t_31);
290 tcg_gen_and_tl(t0, t0, d);
291 tcg_gen_xor_tl(d, d, t0);
296 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
301 t_31 = tcg_temp_new();
302 tcg_gen_sar_tl(d, a, b);
304 tcg_gen_movi_tl(t_31, 31);
305 tcg_gen_sub_tl(t0, t_31, b);
306 tcg_gen_sar_tl(t0, t0, t_31);
307 tcg_gen_or_tl(d, d, t0);
312 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
314 TCGLabel *l1 = gen_new_label();
321 tcg_gen_shli_tl(d, a, 1);
322 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
323 tcg_gen_sub_tl(d, d, b);
327 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
337 tcg_gen_shli_tl(d, a, 1);
338 tcg_gen_shli_tl(t, ccs, 31 - 3);
339 tcg_gen_sari_tl(t, t, 31);
340 tcg_gen_and_tl(t, t, b);
341 tcg_gen_add_tl(d, d, t);
345 /* Extended arithmetics on CRIS. */
346 static inline void t_gen_add_flag(TCGv d, int flag)
351 t_gen_mov_TN_preg(c, PR_CCS);
352 /* Propagate carry into d. */
353 tcg_gen_andi_tl(c, c, 1 << flag);
355 tcg_gen_shri_tl(c, c, flag);
357 tcg_gen_add_tl(d, d, c);
361 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
363 if (dc->flagx_known) {
368 t_gen_mov_TN_preg(c, PR_CCS);
369 /* C flag is already at bit 0. */
370 tcg_gen_andi_tl(c, c, C_FLAG);
371 tcg_gen_add_tl(d, d, c);
379 t_gen_mov_TN_preg(x, PR_CCS);
380 tcg_gen_mov_tl(c, x);
382 /* Propagate carry into d if X is set. Branch free. */
383 tcg_gen_andi_tl(c, c, C_FLAG);
384 tcg_gen_andi_tl(x, x, X_FLAG);
385 tcg_gen_shri_tl(x, x, 4);
387 tcg_gen_and_tl(x, x, c);
388 tcg_gen_add_tl(d, d, x);
394 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
396 if (dc->flagx_known) {
401 t_gen_mov_TN_preg(c, PR_CCS);
402 /* C flag is already at bit 0. */
403 tcg_gen_andi_tl(c, c, C_FLAG);
404 tcg_gen_sub_tl(d, d, c);
412 t_gen_mov_TN_preg(x, PR_CCS);
413 tcg_gen_mov_tl(c, x);
415 /* Propagate carry into d if X is set. Branch free. */
416 tcg_gen_andi_tl(c, c, C_FLAG);
417 tcg_gen_andi_tl(x, x, X_FLAG);
418 tcg_gen_shri_tl(x, x, 4);
420 tcg_gen_and_tl(x, x, c);
421 tcg_gen_sub_tl(d, d, x);
427 /* Swap the two bytes within each half word of the s operand.
428 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
429 static inline void t_gen_swapb(TCGv d, TCGv s)
434 org_s = tcg_temp_new();
436 /* d and s may refer to the same object. */
437 tcg_gen_mov_tl(org_s, s);
438 tcg_gen_shli_tl(t, org_s, 8);
439 tcg_gen_andi_tl(d, t, 0xff00ff00);
440 tcg_gen_shri_tl(t, org_s, 8);
441 tcg_gen_andi_tl(t, t, 0x00ff00ff);
442 tcg_gen_or_tl(d, d, t);
444 tcg_temp_free(org_s);
447 /* Swap the halfwords of the s operand. */
448 static inline void t_gen_swapw(TCGv d, TCGv s)
451 /* d and s refer the same object. */
453 tcg_gen_mov_tl(t, s);
454 tcg_gen_shli_tl(d, t, 16);
455 tcg_gen_shri_tl(t, t, 16);
456 tcg_gen_or_tl(d, d, t);
460 /* Reverse the within each byte.
461 T0 = (((T0 << 7) & 0x80808080) |
462 ((T0 << 5) & 0x40404040) |
463 ((T0 << 3) & 0x20202020) |
464 ((T0 << 1) & 0x10101010) |
465 ((T0 >> 1) & 0x08080808) |
466 ((T0 >> 3) & 0x04040404) |
467 ((T0 >> 5) & 0x02020202) |
468 ((T0 >> 7) & 0x01010101));
470 static inline void t_gen_swapr(TCGv d, TCGv s)
473 int shift; /* LSL when positive, LSR when negative. */
488 /* d and s refer the same object. */
490 org_s = tcg_temp_new();
491 tcg_gen_mov_tl(org_s, s);
493 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
494 tcg_gen_andi_tl(d, t, bitrev[0].mask);
495 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
496 if (bitrev[i].shift >= 0) {
497 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
499 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
501 tcg_gen_andi_tl(t, t, bitrev[i].mask);
502 tcg_gen_or_tl(d, d, t);
505 tcg_temp_free(org_s);
508 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
510 TCGLabel *l1 = gen_new_label();
512 /* Conditional jmp. */
513 tcg_gen_mov_tl(env_pc, pc_false);
514 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
515 tcg_gen_mov_tl(env_pc, pc_true);
519 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
521 TranslationBlock *tb;
523 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
525 tcg_gen_movi_tl(env_pc, dest);
526 tcg_gen_exit_tb((uintptr_t)tb + n);
528 tcg_gen_movi_tl(env_pc, dest);
533 static inline void cris_clear_x_flag(DisasContext *dc)
535 if (dc->flagx_known && dc->flags_x) {
536 dc->flags_uptodate = 0;
543 static void cris_flush_cc_state(DisasContext *dc)
545 if (dc->cc_size_uptodate != dc->cc_size) {
546 tcg_gen_movi_tl(cc_size, dc->cc_size);
547 dc->cc_size_uptodate = dc->cc_size;
549 tcg_gen_movi_tl(cc_op, dc->cc_op);
550 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
553 static void cris_evaluate_flags(DisasContext *dc)
555 if (dc->flags_uptodate) {
559 cris_flush_cc_state(dc);
563 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
564 cpu_PR[PR_CCS], cc_src,
568 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
569 cpu_PR[PR_CCS], cc_result,
573 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
574 cpu_PR[PR_CCS], cc_result,
584 switch (dc->cc_size) {
586 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
587 cpu_env, cpu_PR[PR_CCS], cc_result);
590 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
591 cpu_env, cpu_PR[PR_CCS], cc_result);
594 gen_helper_evaluate_flags(cpu_env);
603 if (dc->cc_size == 4) {
604 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
605 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
607 gen_helper_evaluate_flags(cpu_env);
612 switch (dc->cc_size) {
614 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
615 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
618 gen_helper_evaluate_flags(cpu_env);
624 if (dc->flagx_known) {
626 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);
627 } else if (dc->cc_op == CC_OP_FLAGS) {
628 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
631 dc->flags_uptodate = 1;
634 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
643 /* Check if we need to evaluate the condition codes due to
645 ovl = (dc->cc_mask ^ mask) & ~mask;
647 /* TODO: optimize this case. It trigs all the time. */
648 cris_evaluate_flags(dc);
654 static void cris_update_cc_op(DisasContext *dc, int op, int size)
658 dc->flags_uptodate = 0;
661 static inline void cris_update_cc_x(DisasContext *dc)
663 /* Save the x flag state at the time of the cc snapshot. */
664 if (dc->flagx_known) {
665 if (dc->cc_x_uptodate == (2 | dc->flags_x)) {
668 tcg_gen_movi_tl(cc_x, dc->flags_x);
669 dc->cc_x_uptodate = 2 | dc->flags_x;
671 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
672 dc->cc_x_uptodate = 1;
676 /* Update cc prior to executing ALU op. Needs source operands untouched. */
677 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
678 TCGv dst, TCGv src, int size)
681 cris_update_cc_op(dc, op, size);
682 tcg_gen_mov_tl(cc_src, src);
690 && op != CC_OP_LSL) {
691 tcg_gen_mov_tl(cc_dest, dst);
694 cris_update_cc_x(dc);
698 /* Update cc after executing ALU op. needs the result. */
699 static inline void cris_update_result(DisasContext *dc, TCGv res)
702 tcg_gen_mov_tl(cc_result, res);
706 /* Returns one if the write back stage should execute. */
707 static void cris_alu_op_exec(DisasContext *dc, int op,
708 TCGv dst, TCGv a, TCGv b, int size)
710 /* Emit the ALU insns. */
713 tcg_gen_add_tl(dst, a, b);
714 /* Extended arithmetics. */
715 t_gen_addx_carry(dc, dst);
718 tcg_gen_add_tl(dst, a, b);
719 t_gen_add_flag(dst, 0); /* C_FLAG. */
722 tcg_gen_add_tl(dst, a, b);
723 t_gen_add_flag(dst, 8); /* R_FLAG. */
726 tcg_gen_sub_tl(dst, a, b);
727 /* Extended arithmetics. */
728 t_gen_subx_carry(dc, dst);
731 tcg_gen_mov_tl(dst, b);
734 tcg_gen_or_tl(dst, a, b);
737 tcg_gen_and_tl(dst, a, b);
740 tcg_gen_xor_tl(dst, a, b);
743 t_gen_lsl(dst, a, b);
746 t_gen_lsr(dst, a, b);
749 t_gen_asr(dst, a, b);
752 tcg_gen_neg_tl(dst, b);
753 /* Extended arithmetics. */
754 t_gen_subx_carry(dc, dst);
757 gen_helper_lz(dst, b);
760 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
763 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
766 t_gen_cris_dstep(dst, a, b);
769 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
773 TCGLabel *l1 = gen_new_label();
774 tcg_gen_mov_tl(dst, a);
775 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
776 tcg_gen_mov_tl(dst, b);
781 tcg_gen_sub_tl(dst, a, b);
782 /* Extended arithmetics. */
783 t_gen_subx_carry(dc, dst);
786 qemu_log("illegal ALU op.\n");
792 tcg_gen_andi_tl(dst, dst, 0xff);
793 } else if (size == 2) {
794 tcg_gen_andi_tl(dst, dst, 0xffff);
798 static void cris_alu(DisasContext *dc, int op,
799 TCGv d, TCGv op_a, TCGv op_b, int size)
806 if (op == CC_OP_CMP) {
807 tmp = tcg_temp_new();
809 } else if (size == 4) {
813 tmp = tcg_temp_new();
817 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
818 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
819 cris_update_result(dc, tmp);
824 tcg_gen_andi_tl(d, d, ~0xff);
826 tcg_gen_andi_tl(d, d, ~0xffff);
828 tcg_gen_or_tl(d, d, tmp);
830 if (!TCGV_EQUAL(tmp, d)) {
835 static int arith_cc(DisasContext *dc)
839 case CC_OP_ADDC: return 1;
840 case CC_OP_ADD: return 1;
841 case CC_OP_SUB: return 1;
842 case CC_OP_DSTEP: return 1;
843 case CC_OP_LSL: return 1;
844 case CC_OP_LSR: return 1;
845 case CC_OP_ASR: return 1;
846 case CC_OP_CMP: return 1;
847 case CC_OP_NEG: return 1;
848 case CC_OP_OR: return 1;
849 case CC_OP_AND: return 1;
850 case CC_OP_XOR: return 1;
851 case CC_OP_MULU: return 1;
852 case CC_OP_MULS: return 1;
860 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
862 int arith_opt, move_opt;
864 /* TODO: optimize more condition codes. */
867 * If the flags are live, we've gotta look into the bits of CCS.
868 * Otherwise, if we just did an arithmetic operation we try to
869 * evaluate the condition code faster.
871 * When this function is done, T0 should be non-zero if the condition
874 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
875 move_opt = (dc->cc_op == CC_OP_MOVE);
878 if ((arith_opt || move_opt)
879 && dc->cc_x_uptodate != (2 | X_FLAG)) {
880 tcg_gen_setcond_tl(TCG_COND_EQ, cc,
881 cc_result, tcg_const_tl(0));
883 cris_evaluate_flags(dc);
885 cpu_PR[PR_CCS], Z_FLAG);
889 if ((arith_opt || move_opt)
890 && dc->cc_x_uptodate != (2 | X_FLAG)) {
891 tcg_gen_mov_tl(cc, cc_result);
893 cris_evaluate_flags(dc);
894 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
896 tcg_gen_andi_tl(cc, cc, Z_FLAG);
900 cris_evaluate_flags(dc);
901 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
904 cris_evaluate_flags(dc);
905 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
906 tcg_gen_andi_tl(cc, cc, C_FLAG);
909 cris_evaluate_flags(dc);
910 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
913 cris_evaluate_flags(dc);
914 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
916 tcg_gen_andi_tl(cc, cc, V_FLAG);
919 if (arith_opt || move_opt) {
922 if (dc->cc_size == 1) {
924 } else if (dc->cc_size == 2) {
928 tcg_gen_shri_tl(cc, cc_result, bits);
929 tcg_gen_xori_tl(cc, cc, 1);
931 cris_evaluate_flags(dc);
932 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
934 tcg_gen_andi_tl(cc, cc, N_FLAG);
938 if (arith_opt || move_opt) {
941 if (dc->cc_size == 1) {
943 } else if (dc->cc_size == 2) {
947 tcg_gen_shri_tl(cc, cc_result, bits);
948 tcg_gen_andi_tl(cc, cc, 1);
950 cris_evaluate_flags(dc);
951 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
956 cris_evaluate_flags(dc);
957 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
961 cris_evaluate_flags(dc);
965 tmp = tcg_temp_new();
966 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
968 /* Overlay the C flag on top of the Z. */
969 tcg_gen_shli_tl(cc, tmp, 2);
970 tcg_gen_and_tl(cc, tmp, cc);
971 tcg_gen_andi_tl(cc, cc, Z_FLAG);
977 cris_evaluate_flags(dc);
978 /* Overlay the V flag on top of the N. */
979 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
982 tcg_gen_andi_tl(cc, cc, N_FLAG);
983 tcg_gen_xori_tl(cc, cc, N_FLAG);
986 cris_evaluate_flags(dc);
987 /* Overlay the V flag on top of the N. */
988 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
991 tcg_gen_andi_tl(cc, cc, N_FLAG);
994 cris_evaluate_flags(dc);
1001 /* To avoid a shift we overlay everything on
1003 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1004 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1006 tcg_gen_xori_tl(z, z, 2);
1008 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1009 tcg_gen_xori_tl(n, n, 2);
1010 tcg_gen_and_tl(cc, z, n);
1011 tcg_gen_andi_tl(cc, cc, 2);
1018 cris_evaluate_flags(dc);
1025 /* To avoid a shift we overlay everything on
1027 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1028 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1030 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1031 tcg_gen_or_tl(cc, z, n);
1032 tcg_gen_andi_tl(cc, cc, 2);
1039 cris_evaluate_flags(dc);
1040 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1043 tcg_gen_movi_tl(cc, 1);
1051 static void cris_store_direct_jmp(DisasContext *dc)
1053 /* Store the direct jmp state into the cpu-state. */
1054 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1055 if (dc->jmp == JMP_DIRECT) {
1056 tcg_gen_movi_tl(env_btaken, 1);
1058 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1059 dc->jmp = JMP_INDIRECT;
1063 static void cris_prepare_cc_branch (DisasContext *dc,
1064 int offset, int cond)
1066 /* This helps us re-schedule the micro-code to insns in delay-slots
1067 before the actual jump. */
1068 dc->delayed_branch = 2;
1069 dc->jmp = JMP_DIRECT_CC;
1070 dc->jmp_pc = dc->pc + offset;
1072 gen_tst_cc(dc, env_btaken, cond);
1073 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1077 /* jumps, when the dest is in a live reg for example. Direct should be set
1078 when the dest addr is constant to allow tb chaining. */
1079 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1081 /* This helps us re-schedule the micro-code to insns in delay-slots
1082 before the actual jump. */
1083 dc->delayed_branch = 2;
1085 if (type == JMP_INDIRECT) {
1086 tcg_gen_movi_tl(env_btaken, 1);
1090 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1092 int mem_index = cpu_mmu_index(&dc->cpu->env);
1094 /* If we get a fault on a delayslot we must keep the jmp state in
1095 the cpu-state to be able to re-execute the jmp. */
1096 if (dc->delayed_branch == 1) {
1097 cris_store_direct_jmp(dc);
1100 tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ);
1103 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1104 unsigned int size, int sign)
1106 int mem_index = cpu_mmu_index(&dc->cpu->env);
1108 /* If we get a fault on a delayslot we must keep the jmp state in
1109 the cpu-state to be able to re-execute the jmp. */
1110 if (dc->delayed_branch == 1) {
1111 cris_store_direct_jmp(dc);
1114 tcg_gen_qemu_ld_tl(dst, addr, mem_index,
1115 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
1118 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1121 int mem_index = cpu_mmu_index(&dc->cpu->env);
1123 /* If we get a fault on a delayslot we must keep the jmp state in
1124 the cpu-state to be able to re-execute the jmp. */
1125 if (dc->delayed_branch == 1) {
1126 cris_store_direct_jmp(dc);
1130 /* Conditional writes. We only support the kind were X and P are known
1131 at translation time. */
1132 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1134 cris_evaluate_flags(dc);
1135 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1139 tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
1141 if (dc->flagx_known && dc->flags_x) {
1142 cris_evaluate_flags(dc);
1143 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1147 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1150 tcg_gen_ext8s_i32(d, s);
1151 } else if (size == 2) {
1152 tcg_gen_ext16s_i32(d, s);
1153 } else if (!TCGV_EQUAL(d, s)) {
1154 tcg_gen_mov_tl(d, s);
1158 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1161 tcg_gen_ext8u_i32(d, s);
1162 } else if (size == 2) {
1163 tcg_gen_ext16u_i32(d, s);
1164 } else if (!TCGV_EQUAL(d, s)) {
1165 tcg_gen_mov_tl(d, s);
1170 static char memsize_char(int size)
1173 case 1: return 'b'; break;
1174 case 2: return 'w'; break;
1175 case 4: return 'd'; break;
1183 static inline unsigned int memsize_z(DisasContext *dc)
1185 return dc->zsize + 1;
1188 static inline unsigned int memsize_zz(DisasContext *dc)
1190 switch (dc->zzsize) {
1198 static inline void do_postinc (DisasContext *dc, int size)
1201 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1205 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1206 int size, int s_ext, TCGv dst)
1209 t_gen_sext(dst, cpu_R[rs], size);
1211 t_gen_zext(dst, cpu_R[rs], size);
1215 /* Prepare T0 and T1 for a register alu operation.
1216 s_ext decides if the operand1 should be sign-extended or zero-extended when
1218 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1219 int size, int s_ext, TCGv dst, TCGv src)
1221 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1224 t_gen_sext(dst, cpu_R[rd], size);
1226 t_gen_zext(dst, cpu_R[rd], size);
1230 static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
1231 int s_ext, int memsize, TCGv dst)
1239 is_imm = rs == 15 && dc->postinc;
1241 /* Load [$rs] onto T1. */
1243 insn_len = 2 + memsize;
1248 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
1249 tcg_gen_movi_tl(dst, imm);
1252 cris_flush_cc_state(dc);
1253 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1255 t_gen_sext(dst, dst, memsize);
1257 t_gen_zext(dst, dst, memsize);
1263 /* Prepare T0 and T1 for a memory + alu operation.
1264 s_ext decides if the operand1 should be sign-extended or zero-extended when
1266 static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
1267 int s_ext, int memsize, TCGv dst, TCGv src)
1271 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
1272 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1277 static const char *cc_name(int cc)
1279 static const char *cc_names[16] = {
1280 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1281 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1284 return cc_names[cc];
1288 /* Start of insn decoders. */
1290 static int dec_bccq(CPUCRISState *env, DisasContext *dc)
1294 uint32_t cond = dc->op2;
1296 offset = EXTRACT_FIELD(dc->ir, 1, 7);
1297 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1300 offset |= sign << 8;
1301 offset = sign_extend(offset, 8);
1303 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1305 /* op2 holds the condition-code. */
1306 cris_cc_mask(dc, 0);
1307 cris_prepare_cc_branch(dc, offset, cond);
1310 static int dec_addoq(CPUCRISState *env, DisasContext *dc)
1314 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1315 imm = sign_extend(dc->op1, 7);
1317 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1318 cris_cc_mask(dc, 0);
1319 /* Fetch register operand, */
1320 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1324 static int dec_addq(CPUCRISState *env, DisasContext *dc)
1326 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1328 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1330 cris_cc_mask(dc, CC_MASK_NZVC);
1332 cris_alu(dc, CC_OP_ADD,
1333 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1336 static int dec_moveq(CPUCRISState *env, DisasContext *dc)
1340 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1341 imm = sign_extend(dc->op1, 5);
1342 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1344 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1347 static int dec_subq(CPUCRISState *env, DisasContext *dc)
1349 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1351 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1353 cris_cc_mask(dc, CC_MASK_NZVC);
1354 cris_alu(dc, CC_OP_SUB,
1355 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1358 static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
1361 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1362 imm = sign_extend(dc->op1, 5);
1364 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1365 cris_cc_mask(dc, CC_MASK_NZVC);
1367 cris_alu(dc, CC_OP_CMP,
1368 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1371 static int dec_andq(CPUCRISState *env, DisasContext *dc)
1374 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1375 imm = sign_extend(dc->op1, 5);
1377 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1378 cris_cc_mask(dc, CC_MASK_NZ);
1380 cris_alu(dc, CC_OP_AND,
1381 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1384 static int dec_orq(CPUCRISState *env, DisasContext *dc)
1387 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1388 imm = sign_extend(dc->op1, 5);
1389 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1390 cris_cc_mask(dc, CC_MASK_NZ);
1392 cris_alu(dc, CC_OP_OR,
1393 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1396 static int dec_btstq(CPUCRISState *env, DisasContext *dc)
1398 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1399 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1401 cris_cc_mask(dc, CC_MASK_NZ);
1402 cris_evaluate_flags(dc);
1403 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1404 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1405 cris_alu(dc, CC_OP_MOVE,
1406 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1407 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1408 dc->flags_uptodate = 1;
1411 static int dec_asrq(CPUCRISState *env, DisasContext *dc)
1413 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1414 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1415 cris_cc_mask(dc, CC_MASK_NZ);
1417 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1418 cris_alu(dc, CC_OP_MOVE,
1420 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1423 static int dec_lslq(CPUCRISState *env, DisasContext *dc)
1425 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1426 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1428 cris_cc_mask(dc, CC_MASK_NZ);
1430 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1432 cris_alu(dc, CC_OP_MOVE,
1434 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1437 static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
1439 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1440 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1442 cris_cc_mask(dc, CC_MASK_NZ);
1444 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1445 cris_alu(dc, CC_OP_MOVE,
1447 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1451 static int dec_move_r(CPUCRISState *env, DisasContext *dc)
1453 int size = memsize_zz(dc);
1455 LOG_DIS("move.%c $r%u, $r%u\n",
1456 memsize_char(size), dc->op1, dc->op2);
1458 cris_cc_mask(dc, CC_MASK_NZ);
1460 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1461 cris_cc_mask(dc, CC_MASK_NZ);
1462 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1463 cris_update_cc_x(dc);
1464 cris_update_result(dc, cpu_R[dc->op2]);
1468 t0 = tcg_temp_new();
1469 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1470 cris_alu(dc, CC_OP_MOVE,
1472 cpu_R[dc->op2], t0, size);
1478 static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
1482 LOG_DIS("s%s $r%u\n",
1483 cc_name(cond), dc->op1);
1486 TCGLabel *l1 = gen_new_label();
1487 gen_tst_cc(dc, cpu_R[dc->op1], cond);
1488 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1489 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1492 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1495 cris_cc_mask(dc, 0);
1499 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1502 t[0] = cpu_R[dc->op2];
1503 t[1] = cpu_R[dc->op1];
1505 t[0] = tcg_temp_new();
1506 t[1] = tcg_temp_new();
1510 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1513 tcg_temp_free(t[0]);
1514 tcg_temp_free(t[1]);
1518 static int dec_and_r(CPUCRISState *env, DisasContext *dc)
1521 int size = memsize_zz(dc);
1523 LOG_DIS("and.%c $r%u, $r%u\n",
1524 memsize_char(size), dc->op1, dc->op2);
1526 cris_cc_mask(dc, CC_MASK_NZ);
1528 cris_alu_alloc_temps(dc, size, t);
1529 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1530 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1531 cris_alu_free_temps(dc, size, t);
1535 static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
1538 LOG_DIS("lz $r%u, $r%u\n",
1540 cris_cc_mask(dc, CC_MASK_NZ);
1541 t0 = tcg_temp_new();
1542 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1543 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1548 static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
1551 int size = memsize_zz(dc);
1553 LOG_DIS("lsl.%c $r%u, $r%u\n",
1554 memsize_char(size), dc->op1, dc->op2);
1556 cris_cc_mask(dc, CC_MASK_NZ);
1557 cris_alu_alloc_temps(dc, size, t);
1558 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1559 tcg_gen_andi_tl(t[1], t[1], 63);
1560 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1561 cris_alu_alloc_temps(dc, size, t);
1565 static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
1568 int size = memsize_zz(dc);
1570 LOG_DIS("lsr.%c $r%u, $r%u\n",
1571 memsize_char(size), dc->op1, dc->op2);
1573 cris_cc_mask(dc, CC_MASK_NZ);
1574 cris_alu_alloc_temps(dc, size, t);
1575 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1576 tcg_gen_andi_tl(t[1], t[1], 63);
1577 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1578 cris_alu_free_temps(dc, size, t);
1582 static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
1585 int size = memsize_zz(dc);
1587 LOG_DIS("asr.%c $r%u, $r%u\n",
1588 memsize_char(size), dc->op1, dc->op2);
1590 cris_cc_mask(dc, CC_MASK_NZ);
1591 cris_alu_alloc_temps(dc, size, t);
1592 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1593 tcg_gen_andi_tl(t[1], t[1], 63);
1594 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1595 cris_alu_free_temps(dc, size, t);
1599 static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
1602 int size = memsize_zz(dc);
1604 LOG_DIS("muls.%c $r%u, $r%u\n",
1605 memsize_char(size), dc->op1, dc->op2);
1606 cris_cc_mask(dc, CC_MASK_NZV);
1607 cris_alu_alloc_temps(dc, size, t);
1608 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1610 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1611 cris_alu_free_temps(dc, size, t);
1615 static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
1618 int size = memsize_zz(dc);
1620 LOG_DIS("mulu.%c $r%u, $r%u\n",
1621 memsize_char(size), dc->op1, dc->op2);
1622 cris_cc_mask(dc, CC_MASK_NZV);
1623 cris_alu_alloc_temps(dc, size, t);
1624 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1626 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1627 cris_alu_alloc_temps(dc, size, t);
1632 static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
1634 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1635 cris_cc_mask(dc, CC_MASK_NZ);
1636 cris_alu(dc, CC_OP_DSTEP,
1637 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1641 static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
1644 int size = memsize_zz(dc);
1645 LOG_DIS("xor.%c $r%u, $r%u\n",
1646 memsize_char(size), dc->op1, dc->op2);
1647 BUG_ON(size != 4); /* xor is dword. */
1648 cris_cc_mask(dc, CC_MASK_NZ);
1649 cris_alu_alloc_temps(dc, size, t);
1650 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1652 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1653 cris_alu_free_temps(dc, size, t);
1657 static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
1660 int size = memsize_zz(dc);
1661 LOG_DIS("bound.%c $r%u, $r%u\n",
1662 memsize_char(size), dc->op1, dc->op2);
1663 cris_cc_mask(dc, CC_MASK_NZ);
1664 l0 = tcg_temp_local_new();
1665 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1666 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1671 static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
1674 int size = memsize_zz(dc);
1675 LOG_DIS("cmp.%c $r%u, $r%u\n",
1676 memsize_char(size), dc->op1, dc->op2);
1677 cris_cc_mask(dc, CC_MASK_NZVC);
1678 cris_alu_alloc_temps(dc, size, t);
1679 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1681 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1682 cris_alu_free_temps(dc, size, t);
1686 static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
1690 LOG_DIS("abs $r%u, $r%u\n",
1692 cris_cc_mask(dc, CC_MASK_NZ);
1694 t0 = tcg_temp_new();
1695 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1696 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1697 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1700 cris_alu(dc, CC_OP_MOVE,
1701 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1705 static int dec_add_r(CPUCRISState *env, DisasContext *dc)
1708 int size = memsize_zz(dc);
1709 LOG_DIS("add.%c $r%u, $r%u\n",
1710 memsize_char(size), dc->op1, dc->op2);
1711 cris_cc_mask(dc, CC_MASK_NZVC);
1712 cris_alu_alloc_temps(dc, size, t);
1713 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1715 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1716 cris_alu_free_temps(dc, size, t);
1720 static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
1722 LOG_DIS("addc $r%u, $r%u\n",
1724 cris_evaluate_flags(dc);
1725 /* Set for this insn. */
1726 dc->flagx_known = 1;
1727 dc->flags_x = X_FLAG;
1729 cris_cc_mask(dc, CC_MASK_NZVC);
1730 cris_alu(dc, CC_OP_ADDC,
1731 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1735 static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
1737 LOG_DIS("mcp $p%u, $r%u\n",
1739 cris_evaluate_flags(dc);
1740 cris_cc_mask(dc, CC_MASK_RNZV);
1741 cris_alu(dc, CC_OP_MCP,
1742 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1747 static char * swapmode_name(int mode, char *modename) {
1750 modename[i++] = 'n';
1753 modename[i++] = 'w';
1756 modename[i++] = 'b';
1759 modename[i++] = 'r';
1766 static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
1772 LOG_DIS("swap%s $r%u\n",
1773 swapmode_name(dc->op2, modename), dc->op1);
1775 cris_cc_mask(dc, CC_MASK_NZ);
1776 t0 = tcg_temp_new();
1777 tcg_gen_mov_tl(t0, cpu_R[dc->op1]);
1779 tcg_gen_not_tl(t0, t0);
1782 t_gen_swapw(t0, t0);
1785 t_gen_swapb(t0, t0);
1788 t_gen_swapr(t0, t0);
1790 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1795 static int dec_or_r(CPUCRISState *env, DisasContext *dc)
1798 int size = memsize_zz(dc);
1799 LOG_DIS("or.%c $r%u, $r%u\n",
1800 memsize_char(size), dc->op1, dc->op2);
1801 cris_cc_mask(dc, CC_MASK_NZ);
1802 cris_alu_alloc_temps(dc, size, t);
1803 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1804 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1805 cris_alu_free_temps(dc, size, t);
1809 static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
1812 LOG_DIS("addi.%c $r%u, $r%u\n",
1813 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1814 cris_cc_mask(dc, 0);
1815 t0 = tcg_temp_new();
1816 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1817 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1822 static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
1825 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1826 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1827 cris_cc_mask(dc, 0);
1828 t0 = tcg_temp_new();
1829 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1830 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1835 static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
1838 int size = memsize_zz(dc);
1839 LOG_DIS("neg.%c $r%u, $r%u\n",
1840 memsize_char(size), dc->op1, dc->op2);
1841 cris_cc_mask(dc, CC_MASK_NZVC);
1842 cris_alu_alloc_temps(dc, size, t);
1843 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1845 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1846 cris_alu_free_temps(dc, size, t);
1850 static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
1852 LOG_DIS("btst $r%u, $r%u\n",
1854 cris_cc_mask(dc, CC_MASK_NZ);
1855 cris_evaluate_flags(dc);
1856 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1857 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1858 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1859 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1860 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1861 dc->flags_uptodate = 1;
1865 static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
1868 int size = memsize_zz(dc);
1869 LOG_DIS("sub.%c $r%u, $r%u\n",
1870 memsize_char(size), dc->op1, dc->op2);
1871 cris_cc_mask(dc, CC_MASK_NZVC);
1872 cris_alu_alloc_temps(dc, size, t);
1873 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1874 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1875 cris_alu_free_temps(dc, size, t);
1879 /* Zero extension. From size to dword. */
1880 static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
1883 int size = memsize_z(dc);
1884 LOG_DIS("movu.%c $r%u, $r%u\n",
1888 cris_cc_mask(dc, CC_MASK_NZ);
1889 t0 = tcg_temp_new();
1890 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1891 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1896 /* Sign extension. From size to dword. */
1897 static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
1900 int size = memsize_z(dc);
1901 LOG_DIS("movs.%c $r%u, $r%u\n",
1905 cris_cc_mask(dc, CC_MASK_NZ);
1906 t0 = tcg_temp_new();
1907 /* Size can only be qi or hi. */
1908 t_gen_sext(t0, cpu_R[dc->op1], size);
1909 cris_alu(dc, CC_OP_MOVE,
1910 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1915 /* zero extension. From size to dword. */
1916 static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
1919 int size = memsize_z(dc);
1920 LOG_DIS("addu.%c $r%u, $r%u\n",
1924 cris_cc_mask(dc, CC_MASK_NZVC);
1925 t0 = tcg_temp_new();
1926 /* Size can only be qi or hi. */
1927 t_gen_zext(t0, cpu_R[dc->op1], size);
1928 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1933 /* Sign extension. From size to dword. */
1934 static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
1937 int size = memsize_z(dc);
1938 LOG_DIS("adds.%c $r%u, $r%u\n",
1942 cris_cc_mask(dc, CC_MASK_NZVC);
1943 t0 = tcg_temp_new();
1944 /* Size can only be qi or hi. */
1945 t_gen_sext(t0, cpu_R[dc->op1], size);
1946 cris_alu(dc, CC_OP_ADD,
1947 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1952 /* Zero extension. From size to dword. */
1953 static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
1956 int size = memsize_z(dc);
1957 LOG_DIS("subu.%c $r%u, $r%u\n",
1961 cris_cc_mask(dc, CC_MASK_NZVC);
1962 t0 = tcg_temp_new();
1963 /* Size can only be qi or hi. */
1964 t_gen_zext(t0, cpu_R[dc->op1], size);
1965 cris_alu(dc, CC_OP_SUB,
1966 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1971 /* Sign extension. From size to dword. */
1972 static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
1975 int size = memsize_z(dc);
1976 LOG_DIS("subs.%c $r%u, $r%u\n",
1980 cris_cc_mask(dc, CC_MASK_NZVC);
1981 t0 = tcg_temp_new();
1982 /* Size can only be qi or hi. */
1983 t_gen_sext(t0, cpu_R[dc->op1], size);
1984 cris_alu(dc, CC_OP_SUB,
1985 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1990 static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
1993 int set = (~dc->opcode >> 2) & 1;
1996 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1997 | EXTRACT_FIELD(dc->ir, 0, 3);
1998 if (set && flags == 0) {
2001 } else if (!set && (flags & 0x20)) {
2004 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags);
2007 /* User space is not allowed to touch these. Silently ignore. */
2008 if (dc->tb_flags & U_FLAG) {
2009 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2012 if (flags & X_FLAG) {
2013 dc->flagx_known = 1;
2015 dc->flags_x = X_FLAG;
2021 /* Break the TB if any of the SPI flag changes. */
2022 if (flags & (P_FLAG | S_FLAG)) {
2023 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2024 dc->is_jmp = DISAS_UPDATE;
2025 dc->cpustate_changed = 1;
2028 /* For the I flag, only act on posedge. */
2029 if ((flags & I_FLAG)) {
2030 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2031 dc->is_jmp = DISAS_UPDATE;
2032 dc->cpustate_changed = 1;
2036 /* Simply decode the flags. */
2037 cris_evaluate_flags(dc);
2038 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2039 cris_update_cc_x(dc);
2040 tcg_gen_movi_tl(cc_op, dc->cc_op);
2043 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2044 /* Enter user mode. */
2045 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2046 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2047 dc->cpustate_changed = 1;
2049 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2051 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2054 dc->flags_uptodate = 1;
2059 static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
2061 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2062 cris_cc_mask(dc, 0);
2063 gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
2064 tcg_const_tl(dc->op1));
2067 static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
2069 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2070 cris_cc_mask(dc, 0);
2071 gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
2072 tcg_const_tl(dc->op2));
2076 static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
2079 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2080 cris_cc_mask(dc, 0);
2082 t[0] = tcg_temp_new();
2083 if (dc->op2 == PR_CCS) {
2084 cris_evaluate_flags(dc);
2085 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2086 if (dc->tb_flags & U_FLAG) {
2087 t[1] = tcg_temp_new();
2088 /* User space is not allowed to touch all flags. */
2089 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2090 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2091 tcg_gen_or_tl(t[0], t[1], t[0]);
2092 tcg_temp_free(t[1]);
2095 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2098 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2099 if (dc->op2 == PR_CCS) {
2100 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2101 dc->flags_uptodate = 1;
2103 tcg_temp_free(t[0]);
2106 static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
2109 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2110 cris_cc_mask(dc, 0);
2112 if (dc->op2 == PR_CCS) {
2113 cris_evaluate_flags(dc);
2116 if (dc->op2 == PR_DZ) {
2117 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2119 t0 = tcg_temp_new();
2120 t_gen_mov_TN_preg(t0, dc->op2);
2121 cris_alu(dc, CC_OP_MOVE,
2122 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2123 preg_sizes[dc->op2]);
2129 static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
2131 int memsize = memsize_zz(dc);
2133 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2134 memsize_char(memsize),
2135 dc->op1, dc->postinc ? "+]" : "]",
2139 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
2140 cris_cc_mask(dc, CC_MASK_NZ);
2141 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2142 cris_update_cc_x(dc);
2143 cris_update_result(dc, cpu_R[dc->op2]);
2147 t0 = tcg_temp_new();
2148 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
2149 cris_cc_mask(dc, CC_MASK_NZ);
2150 cris_alu(dc, CC_OP_MOVE,
2151 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2154 do_postinc(dc, memsize);
2158 static inline void cris_alu_m_alloc_temps(TCGv *t)
2160 t[0] = tcg_temp_new();
2161 t[1] = tcg_temp_new();
2164 static inline void cris_alu_m_free_temps(TCGv *t)
2166 tcg_temp_free(t[0]);
2167 tcg_temp_free(t[1]);
2170 static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
2173 int memsize = memsize_z(dc);
2175 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2176 memsize_char(memsize),
2177 dc->op1, dc->postinc ? "+]" : "]",
2180 cris_alu_m_alloc_temps(t);
2182 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2183 cris_cc_mask(dc, CC_MASK_NZ);
2184 cris_alu(dc, CC_OP_MOVE,
2185 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2186 do_postinc(dc, memsize);
2187 cris_alu_m_free_temps(t);
2191 static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
2194 int memsize = memsize_z(dc);
2196 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2197 memsize_char(memsize),
2198 dc->op1, dc->postinc ? "+]" : "]",
2201 cris_alu_m_alloc_temps(t);
2203 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2204 cris_cc_mask(dc, CC_MASK_NZVC);
2205 cris_alu(dc, CC_OP_ADD,
2206 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2207 do_postinc(dc, memsize);
2208 cris_alu_m_free_temps(t);
2212 static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
2215 int memsize = memsize_z(dc);
2217 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2218 memsize_char(memsize),
2219 dc->op1, dc->postinc ? "+]" : "]",
2222 cris_alu_m_alloc_temps(t);
2224 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2225 cris_cc_mask(dc, CC_MASK_NZVC);
2226 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2227 do_postinc(dc, memsize);
2228 cris_alu_m_free_temps(t);
2232 static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
2235 int memsize = memsize_z(dc);
2237 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2238 memsize_char(memsize),
2239 dc->op1, dc->postinc ? "+]" : "]",
2242 cris_alu_m_alloc_temps(t);
2244 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2245 cris_cc_mask(dc, CC_MASK_NZVC);
2246 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2247 do_postinc(dc, memsize);
2248 cris_alu_m_free_temps(t);
2252 static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
2255 int memsize = memsize_z(dc);
2257 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2258 memsize_char(memsize),
2259 dc->op1, dc->postinc ? "+]" : "]",
2262 cris_alu_m_alloc_temps(t);
2264 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2265 cris_cc_mask(dc, CC_MASK_NZVC);
2266 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2267 do_postinc(dc, memsize);
2268 cris_alu_m_free_temps(t);
2272 static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
2275 int memsize = memsize_z(dc);
2278 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2279 memsize_char(memsize),
2280 dc->op1, dc->postinc ? "+]" : "]",
2283 cris_alu_m_alloc_temps(t);
2284 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2285 cris_cc_mask(dc, CC_MASK_NZ);
2286 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2287 do_postinc(dc, memsize);
2288 cris_alu_m_free_temps(t);
2292 static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
2295 int memsize = memsize_z(dc);
2297 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2298 memsize_char(memsize),
2299 dc->op1, dc->postinc ? "+]" : "]",
2302 cris_alu_m_alloc_temps(t);
2303 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2304 cris_cc_mask(dc, CC_MASK_NZVC);
2305 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2306 do_postinc(dc, memsize);
2307 cris_alu_m_free_temps(t);
2311 static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
2314 int memsize = memsize_z(dc);
2316 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2317 memsize_char(memsize),
2318 dc->op1, dc->postinc ? "+]" : "]",
2321 cris_alu_m_alloc_temps(t);
2322 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2323 cris_cc_mask(dc, CC_MASK_NZVC);
2324 cris_alu(dc, CC_OP_CMP,
2325 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2327 do_postinc(dc, memsize);
2328 cris_alu_m_free_temps(t);
2332 static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
2335 int memsize = memsize_zz(dc);
2337 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2338 memsize_char(memsize),
2339 dc->op1, dc->postinc ? "+]" : "]",
2342 cris_alu_m_alloc_temps(t);
2343 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2344 cris_cc_mask(dc, CC_MASK_NZVC);
2345 cris_alu(dc, CC_OP_CMP,
2346 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2348 do_postinc(dc, memsize);
2349 cris_alu_m_free_temps(t);
2353 static int dec_test_m(CPUCRISState *env, DisasContext *dc)
2356 int memsize = memsize_zz(dc);
2358 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2359 memsize_char(memsize),
2360 dc->op1, dc->postinc ? "+]" : "]",
2363 cris_evaluate_flags(dc);
2365 cris_alu_m_alloc_temps(t);
2366 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2367 cris_cc_mask(dc, CC_MASK_NZ);
2368 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2370 cris_alu(dc, CC_OP_CMP,
2371 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2372 do_postinc(dc, memsize);
2373 cris_alu_m_free_temps(t);
2377 static int dec_and_m(CPUCRISState *env, DisasContext *dc)
2380 int memsize = memsize_zz(dc);
2382 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2383 memsize_char(memsize),
2384 dc->op1, dc->postinc ? "+]" : "]",
2387 cris_alu_m_alloc_temps(t);
2388 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2389 cris_cc_mask(dc, CC_MASK_NZ);
2390 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2391 do_postinc(dc, memsize);
2392 cris_alu_m_free_temps(t);
2396 static int dec_add_m(CPUCRISState *env, DisasContext *dc)
2399 int memsize = memsize_zz(dc);
2401 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2402 memsize_char(memsize),
2403 dc->op1, dc->postinc ? "+]" : "]",
2406 cris_alu_m_alloc_temps(t);
2407 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2408 cris_cc_mask(dc, CC_MASK_NZVC);
2409 cris_alu(dc, CC_OP_ADD,
2410 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2411 do_postinc(dc, memsize);
2412 cris_alu_m_free_temps(t);
2416 static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
2419 int memsize = memsize_zz(dc);
2421 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2422 memsize_char(memsize),
2423 dc->op1, dc->postinc ? "+]" : "]",
2426 cris_alu_m_alloc_temps(t);
2427 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2428 cris_cc_mask(dc, 0);
2429 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2430 do_postinc(dc, memsize);
2431 cris_alu_m_free_temps(t);
2435 static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
2438 int memsize = memsize_zz(dc);
2440 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2441 memsize_char(memsize),
2442 dc->op1, dc->postinc ? "+]" : "]",
2445 l[0] = tcg_temp_local_new();
2446 l[1] = tcg_temp_local_new();
2447 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
2448 cris_cc_mask(dc, CC_MASK_NZ);
2449 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2450 do_postinc(dc, memsize);
2451 tcg_temp_free(l[0]);
2452 tcg_temp_free(l[1]);
2456 static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
2460 LOG_DIS("addc [$r%u%s, $r%u\n",
2461 dc->op1, dc->postinc ? "+]" : "]",
2464 cris_evaluate_flags(dc);
2466 /* Set for this insn. */
2467 dc->flagx_known = 1;
2468 dc->flags_x = X_FLAG;
2470 cris_alu_m_alloc_temps(t);
2471 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
2472 cris_cc_mask(dc, CC_MASK_NZVC);
2473 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2475 cris_alu_m_free_temps(t);
2479 static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
2482 int memsize = memsize_zz(dc);
2484 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2485 memsize_char(memsize),
2486 dc->op1, dc->postinc ? "+]" : "]",
2487 dc->op2, dc->ir, dc->zzsize);
2489 cris_alu_m_alloc_temps(t);
2490 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2491 cris_cc_mask(dc, CC_MASK_NZVC);
2492 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2493 do_postinc(dc, memsize);
2494 cris_alu_m_free_temps(t);
2498 static int dec_or_m(CPUCRISState *env, DisasContext *dc)
2501 int memsize = memsize_zz(dc);
2503 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2504 memsize_char(memsize),
2505 dc->op1, dc->postinc ? "+]" : "]",
2508 cris_alu_m_alloc_temps(t);
2509 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2510 cris_cc_mask(dc, CC_MASK_NZ);
2511 cris_alu(dc, CC_OP_OR,
2512 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2513 do_postinc(dc, memsize);
2514 cris_alu_m_free_temps(t);
2518 static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
2521 int memsize = memsize_zz(dc);
2524 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2525 memsize_char(memsize),
2527 dc->postinc ? "+]" : "]",
2530 cris_alu_m_alloc_temps(t);
2531 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2532 cris_cc_mask(dc, 0);
2533 if (dc->op2 == PR_CCS) {
2534 cris_evaluate_flags(dc);
2535 if (dc->tb_flags & U_FLAG) {
2536 /* User space is not allowed to touch all flags. */
2537 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2538 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2539 tcg_gen_or_tl(t[1], t[0], t[1]);
2543 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2545 do_postinc(dc, memsize);
2546 cris_alu_m_free_temps(t);
2550 static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
2555 memsize = preg_sizes[dc->op2];
2557 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2558 memsize_char(memsize),
2559 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2561 /* prepare store. Address in T0, value in T1. */
2562 if (dc->op2 == PR_CCS) {
2563 cris_evaluate_flags(dc);
2565 t0 = tcg_temp_new();
2566 t_gen_mov_TN_preg(t0, dc->op2);
2567 cris_flush_cc_state(dc);
2568 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2571 cris_cc_mask(dc, 0);
2573 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2578 static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
2584 int nr = dc->op2 + 1;
2586 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2587 dc->postinc ? "+]" : "]", dc->op2);
2589 addr = tcg_temp_new();
2590 /* There are probably better ways of doing this. */
2591 cris_flush_cc_state(dc);
2592 for (i = 0; i < (nr >> 1); i++) {
2593 tmp[i] = tcg_temp_new_i64();
2594 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2595 gen_load64(dc, tmp[i], addr);
2598 tmp32 = tcg_temp_new_i32();
2599 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2600 gen_load(dc, tmp32, addr, 4, 0);
2604 tcg_temp_free(addr);
2606 for (i = 0; i < (nr >> 1); i++) {
2607 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2608 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2609 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2610 tcg_temp_free_i64(tmp[i]);
2613 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2614 tcg_temp_free(tmp32);
2617 /* writeback the updated pointer value. */
2619 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2622 /* gen_load might want to evaluate the previous insns flags. */
2623 cris_cc_mask(dc, 0);
2627 static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
2633 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2634 dc->postinc ? "+]" : "]");
2636 cris_flush_cc_state(dc);
2638 tmp = tcg_temp_new();
2639 addr = tcg_temp_new();
2640 tcg_gen_movi_tl(tmp, 4);
2641 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2642 for (i = 0; i <= dc->op2; i++) {
2643 /* Displace addr. */
2644 /* Perform the store. */
2645 gen_store(dc, addr, cpu_R[i], 4);
2646 tcg_gen_add_tl(addr, addr, tmp);
2649 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2651 cris_cc_mask(dc, 0);
2653 tcg_temp_free(addr);
2657 static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
2661 memsize = memsize_zz(dc);
2663 LOG_DIS("move.%c $r%u, [$r%u]\n",
2664 memsize_char(memsize), dc->op2, dc->op1);
2666 /* prepare store. */
2667 cris_flush_cc_state(dc);
2668 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2671 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2673 cris_cc_mask(dc, 0);
2677 static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
2679 LOG_DIS("lapcq %x, $r%u\n",
2680 dc->pc + dc->op1*2, dc->op2);
2681 cris_cc_mask(dc, 0);
2682 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2686 static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
2694 cris_cc_mask(dc, 0);
2695 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2696 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2700 tcg_gen_movi_tl(cpu_R[rd], pc);
2704 /* Jump to special reg. */
2705 static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
2707 LOG_DIS("jump $p%u\n", dc->op2);
2709 if (dc->op2 == PR_CCS) {
2710 cris_evaluate_flags(dc);
2712 t_gen_mov_TN_preg(env_btarget, dc->op2);
2713 /* rete will often have low bit set to indicate delayslot. */
2714 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2715 cris_cc_mask(dc, 0);
2716 cris_prepare_jmp(dc, JMP_INDIRECT);
2720 /* Jump and save. */
2721 static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
2723 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2724 cris_cc_mask(dc, 0);
2725 /* Store the return address in Pd. */
2726 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2730 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2732 cris_prepare_jmp(dc, JMP_INDIRECT);
2736 static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
2740 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2742 LOG_DIS("jas 0x%x\n", imm);
2743 cris_cc_mask(dc, 0);
2744 /* Store the return address in Pd. */
2745 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2748 cris_prepare_jmp(dc, JMP_DIRECT);
2752 static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
2756 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2758 LOG_DIS("jasc 0x%x\n", imm);
2759 cris_cc_mask(dc, 0);
2760 /* Store the return address in Pd. */
2761 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2764 cris_prepare_jmp(dc, JMP_DIRECT);
2768 static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
2770 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2771 cris_cc_mask(dc, 0);
2772 /* Store the return address in Pd. */
2773 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2774 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2775 cris_prepare_jmp(dc, JMP_INDIRECT);
2779 static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
2782 uint32_t cond = dc->op2;
2784 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
2786 LOG_DIS("b%s %d pc=%x dst=%x\n",
2787 cc_name(cond), offset,
2788 dc->pc, dc->pc + offset);
2790 cris_cc_mask(dc, 0);
2791 /* op2 holds the condition-code. */
2792 cris_prepare_cc_branch(dc, offset, cond);
2796 static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
2800 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2802 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2803 cris_cc_mask(dc, 0);
2804 /* Store the return address in Pd. */
2805 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2807 dc->jmp_pc = dc->pc + simm;
2808 cris_prepare_jmp(dc, JMP_DIRECT);
2812 static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
2815 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2817 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2818 cris_cc_mask(dc, 0);
2819 /* Store the return address in Pd. */
2820 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2822 dc->jmp_pc = dc->pc + simm;
2823 cris_prepare_jmp(dc, JMP_DIRECT);
2827 static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
2829 cris_cc_mask(dc, 0);
2831 if (dc->op2 == 15) {
2832 tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
2833 -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
2834 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2835 t_gen_raise_exception(EXCP_HLT);
2839 switch (dc->op2 & 7) {
2843 cris_evaluate_flags(dc);
2844 gen_helper_rfe(cpu_env);
2845 dc->is_jmp = DISAS_UPDATE;
2850 cris_evaluate_flags(dc);
2851 gen_helper_rfn(cpu_env);
2852 dc->is_jmp = DISAS_UPDATE;
2855 LOG_DIS("break %d\n", dc->op1);
2856 cris_evaluate_flags(dc);
2858 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2860 /* Breaks start at 16 in the exception vector. */
2861 t_gen_mov_env_TN(trap_vector,
2862 tcg_const_tl(dc->op1 + 16));
2863 t_gen_raise_exception(EXCP_BREAK);
2864 dc->is_jmp = DISAS_UPDATE;
2867 printf("op2=%x\n", dc->op2);
2875 static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
2880 static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
2885 static int dec_null(CPUCRISState *env, DisasContext *dc)
2887 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2888 dc->pc, dc->opcode, dc->op1, dc->op2);
2894 static struct decoder_info {
2899 int (*dec)(CPUCRISState *env, DisasContext *dc);
2901 /* Order matters here. */
2902 {DEC_MOVEQ, dec_moveq},
2903 {DEC_BTSTQ, dec_btstq},
2904 {DEC_CMPQ, dec_cmpq},
2905 {DEC_ADDOQ, dec_addoq},
2906 {DEC_ADDQ, dec_addq},
2907 {DEC_SUBQ, dec_subq},
2908 {DEC_ANDQ, dec_andq},
2910 {DEC_ASRQ, dec_asrq},
2911 {DEC_LSLQ, dec_lslq},
2912 {DEC_LSRQ, dec_lsrq},
2913 {DEC_BCCQ, dec_bccq},
2915 {DEC_BCC_IM, dec_bcc_im},
2916 {DEC_JAS_IM, dec_jas_im},
2917 {DEC_JAS_R, dec_jas_r},
2918 {DEC_JASC_IM, dec_jasc_im},
2919 {DEC_JASC_R, dec_jasc_r},
2920 {DEC_BAS_IM, dec_bas_im},
2921 {DEC_BASC_IM, dec_basc_im},
2922 {DEC_JUMP_P, dec_jump_p},
2923 {DEC_LAPC_IM, dec_lapc_im},
2924 {DEC_LAPCQ, dec_lapcq},
2926 {DEC_RFE_ETC, dec_rfe_etc},
2927 {DEC_ADDC_MR, dec_addc_mr},
2929 {DEC_MOVE_MP, dec_move_mp},
2930 {DEC_MOVE_PM, dec_move_pm},
2931 {DEC_MOVEM_MR, dec_movem_mr},
2932 {DEC_MOVEM_RM, dec_movem_rm},
2933 {DEC_MOVE_PR, dec_move_pr},
2934 {DEC_SCC_R, dec_scc_r},
2935 {DEC_SETF, dec_setclrf},
2936 {DEC_CLEARF, dec_setclrf},
2938 {DEC_MOVE_SR, dec_move_sr},
2939 {DEC_MOVE_RP, dec_move_rp},
2940 {DEC_SWAP_R, dec_swap_r},
2941 {DEC_ABS_R, dec_abs_r},
2942 {DEC_LZ_R, dec_lz_r},
2943 {DEC_MOVE_RS, dec_move_rs},
2944 {DEC_BTST_R, dec_btst_r},
2945 {DEC_ADDC_R, dec_addc_r},
2947 {DEC_DSTEP_R, dec_dstep_r},
2948 {DEC_XOR_R, dec_xor_r},
2949 {DEC_MCP_R, dec_mcp_r},
2950 {DEC_CMP_R, dec_cmp_r},
2952 {DEC_ADDI_R, dec_addi_r},
2953 {DEC_ADDI_ACR, dec_addi_acr},
2955 {DEC_ADD_R, dec_add_r},
2956 {DEC_SUB_R, dec_sub_r},
2958 {DEC_ADDU_R, dec_addu_r},
2959 {DEC_ADDS_R, dec_adds_r},
2960 {DEC_SUBU_R, dec_subu_r},
2961 {DEC_SUBS_R, dec_subs_r},
2962 {DEC_LSL_R, dec_lsl_r},
2964 {DEC_AND_R, dec_and_r},
2965 {DEC_OR_R, dec_or_r},
2966 {DEC_BOUND_R, dec_bound_r},
2967 {DEC_ASR_R, dec_asr_r},
2968 {DEC_LSR_R, dec_lsr_r},
2970 {DEC_MOVU_R, dec_movu_r},
2971 {DEC_MOVS_R, dec_movs_r},
2972 {DEC_NEG_R, dec_neg_r},
2973 {DEC_MOVE_R, dec_move_r},
2975 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2976 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2978 {DEC_MULS_R, dec_muls_r},
2979 {DEC_MULU_R, dec_mulu_r},
2981 {DEC_ADDU_M, dec_addu_m},
2982 {DEC_ADDS_M, dec_adds_m},
2983 {DEC_SUBU_M, dec_subu_m},
2984 {DEC_SUBS_M, dec_subs_m},
2986 {DEC_CMPU_M, dec_cmpu_m},
2987 {DEC_CMPS_M, dec_cmps_m},
2988 {DEC_MOVU_M, dec_movu_m},
2989 {DEC_MOVS_M, dec_movs_m},
2991 {DEC_CMP_M, dec_cmp_m},
2992 {DEC_ADDO_M, dec_addo_m},
2993 {DEC_BOUND_M, dec_bound_m},
2994 {DEC_ADD_M, dec_add_m},
2995 {DEC_SUB_M, dec_sub_m},
2996 {DEC_AND_M, dec_and_m},
2997 {DEC_OR_M, dec_or_m},
2998 {DEC_MOVE_RM, dec_move_rm},
2999 {DEC_TEST_M, dec_test_m},
3000 {DEC_MOVE_MR, dec_move_mr},
3005 static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
3010 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
3011 tcg_gen_debug_insn_start(dc->pc);
3014 /* Load a halfword onto the instruction register. */
3015 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
3017 /* Now decode it. */
3018 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3019 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3020 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3021 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3022 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3023 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3025 /* Large switch for all insns. */
3026 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3027 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
3028 insn_len = decinfo[i].dec(env, dc);
3033 #if !defined(CONFIG_USER_ONLY)
3034 /* Single-stepping ? */
3035 if (dc->tb_flags & S_FLAG) {
3036 TCGLabel *l1 = gen_new_label();
3037 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3038 /* We treat SPC as a break with an odd trap vector. */
3039 cris_evaluate_flags(dc);
3040 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3041 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3042 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3043 t_gen_raise_exception(EXCP_BREAK);
3050 static void check_breakpoint(CPUCRISState *env, DisasContext *dc)
3052 CPUState *cs = CPU(cris_env_get_cpu(env));
3055 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
3056 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
3057 if (bp->pc == dc->pc) {
3058 cris_evaluate_flags(dc);
3059 tcg_gen_movi_tl(env_pc, dc->pc);
3060 t_gen_raise_exception(EXCP_DEBUG);
3061 dc->is_jmp = DISAS_UPDATE;
3067 #include "translate_v10.c"
3070 * Delay slots on QEMU/CRIS.
3072 * If an exception hits on a delayslot, the core will let ERP (the Exception
3073 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3074 * to give SW a hint that the exception actually hit on the dslot.
3076 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3077 * the core and any jmp to an odd addresses will mask off that lsb. It is
3078 * simply there to let sw know there was an exception on a dslot.
3080 * When the software returns from an exception, the branch will re-execute.
3081 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3082 * and the branch and delayslot dont share pages.
3084 * The TB contaning the branch insn will set up env->btarget and evaluate
3085 * env->btaken. When the translation loop exits we will note that the branch
3086 * sequence is broken and let env->dslot be the size of the branch insn (those
3089 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3090 * set). It will also expect to have env->dslot setup with the size of the
3091 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3092 * will execute the dslot and take the branch, either to btarget or just one
3095 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3096 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3097 * branch and set lsb). Then env->dslot gets cleared so that the exception
3098 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3099 * masked off and we will reexecute the branch insn.
3103 /* generate intermediate code for basic block 'tb'. */
3105 gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
3108 CPUState *cs = CPU(cpu);
3109 CPUCRISState *env = &cpu->env;
3111 unsigned int insn_len;
3113 struct DisasContext ctx;
3114 struct DisasContext *dc = &ctx;
3115 uint32_t next_page_start;
3120 if (env->pregs[PR_VR] == 32) {
3121 dc->decoder = crisv32_decoder;
3122 dc->clear_locked_irq = 0;
3124 dc->decoder = crisv10_decoder;
3125 dc->clear_locked_irq = 1;
3128 /* Odd PC indicates that branch is rexecuting due to exception in the
3129 * delayslot, like in real hw.
3131 pc_start = tb->pc & ~1;
3135 dc->is_jmp = DISAS_NEXT;
3138 dc->singlestep_enabled = cs->singlestep_enabled;
3139 dc->flags_uptodate = 1;
3140 dc->flagx_known = 1;
3141 dc->flags_x = tb->flags & X_FLAG;
3142 dc->cc_x_uptodate = 0;
3145 dc->clear_prefix = 0;
3147 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3148 dc->cc_size_uptodate = -1;
3150 /* Decode TB flags. */
3151 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3152 | X_FLAG | PFIX_FLAG);
3153 dc->delayed_branch = !!(tb->flags & 7);
3154 if (dc->delayed_branch) {
3155 dc->jmp = JMP_INDIRECT;
3157 dc->jmp = JMP_NOJMP;
3160 dc->cpustate_changed = 0;
3162 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3164 "srch=%d pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
3170 search_pc, dc->pc, dc->ppc,
3171 (uint64_t)tb->flags,
3172 env->btarget, (unsigned)tb->flags & 7,
3174 env->pregs[PR_PID], env->pregs[PR_USP],
3175 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3176 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3177 env->regs[8], env->regs[9],
3178 env->regs[10], env->regs[11],
3179 env->regs[12], env->regs[13],
3180 env->regs[14], env->regs[15]);
3181 qemu_log("--------------\n");
3182 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3185 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3188 max_insns = tb->cflags & CF_COUNT_MASK;
3189 if (max_insns == 0) {
3190 max_insns = CF_COUNT_MASK;
3195 check_breakpoint(env, dc);
3198 j = tcg_op_buf_count();
3202 tcg_ctx.gen_opc_instr_start[lj++] = 0;
3205 if (dc->delayed_branch == 1) {
3206 tcg_ctx.gen_opc_pc[lj] = dc->ppc | 1;
3208 tcg_ctx.gen_opc_pc[lj] = dc->pc;
3210 tcg_ctx.gen_opc_instr_start[lj] = 1;
3211 tcg_ctx.gen_opc_icount[lj] = num_insns;
3215 LOG_DIS("%8.8x:\t", dc->pc);
3217 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
3222 insn_len = dc->decoder(env, dc);
3226 cris_clear_x_flag(dc);
3230 /* Check for delayed branches here. If we do it before
3231 actually generating any host code, the simulator will just
3232 loop doing nothing for on this program location. */
3233 if (dc->delayed_branch) {
3234 dc->delayed_branch--;
3235 if (dc->delayed_branch == 0) {
3236 if (tb->flags & 7) {
3237 t_gen_mov_env_TN(dslot, tcg_const_tl(0));
3239 if (dc->cpustate_changed || !dc->flagx_known
3240 || (dc->flags_x != (tb->flags & X_FLAG))) {
3241 cris_store_direct_jmp(dc);
3244 if (dc->clear_locked_irq) {
3245 dc->clear_locked_irq = 0;
3246 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3249 if (dc->jmp == JMP_DIRECT_CC) {
3250 TCGLabel *l1 = gen_new_label();
3251 cris_evaluate_flags(dc);
3253 /* Conditional jmp. */
3254 tcg_gen_brcondi_tl(TCG_COND_EQ,
3256 gen_goto_tb(dc, 1, dc->jmp_pc);
3258 gen_goto_tb(dc, 0, dc->pc);
3259 dc->is_jmp = DISAS_TB_JUMP;
3260 dc->jmp = JMP_NOJMP;
3261 } else if (dc->jmp == JMP_DIRECT) {
3262 cris_evaluate_flags(dc);
3263 gen_goto_tb(dc, 0, dc->jmp_pc);
3264 dc->is_jmp = DISAS_TB_JUMP;
3265 dc->jmp = JMP_NOJMP;
3267 t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc));
3268 dc->is_jmp = DISAS_JUMP;
3274 /* If we are rexecuting a branch due to exceptions on
3275 delay slots dont break. */
3276 if (!(tb->pc & 1) && cs->singlestep_enabled) {
3279 } while (!dc->is_jmp && !dc->cpustate_changed
3280 && !tcg_op_buf_full()
3282 && (dc->pc < next_page_start)
3283 && num_insns < max_insns);
3285 if (dc->clear_locked_irq) {
3286 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3291 if (tb->cflags & CF_LAST_IO)
3293 /* Force an update if the per-tb cpu state has changed. */
3294 if (dc->is_jmp == DISAS_NEXT
3295 && (dc->cpustate_changed || !dc->flagx_known
3296 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3297 dc->is_jmp = DISAS_UPDATE;
3298 tcg_gen_movi_tl(env_pc, npc);
3300 /* Broken branch+delayslot sequence. */
3301 if (dc->delayed_branch == 1) {
3302 /* Set env->dslot to the size of the branch insn. */
3303 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3304 cris_store_direct_jmp(dc);
3307 cris_evaluate_flags(dc);
3309 if (unlikely(cs->singlestep_enabled)) {
3310 if (dc->is_jmp == DISAS_NEXT) {
3311 tcg_gen_movi_tl(env_pc, npc);
3313 t_gen_raise_exception(EXCP_DEBUG);
3315 switch (dc->is_jmp) {
3317 gen_goto_tb(dc, 1, npc);
3322 /* indicate that the hash table must be used
3323 to find the next TB */
3328 /* nothing more to generate */
3332 gen_tb_end(tb, num_insns);
3335 j = tcg_op_buf_count();
3338 tcg_ctx.gen_opc_instr_start[lj++] = 0;
3341 tb->size = dc->pc - pc_start;
3342 tb->icount = num_insns;
3347 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3348 log_target_disas(cs, pc_start, dc->pc - pc_start,
3350 qemu_log("\nisize=%d osize=%d\n",
3351 dc->pc - pc_start, tcg_op_buf_count());
3357 void gen_intermediate_code (CPUCRISState *env, struct TranslationBlock *tb)
3359 gen_intermediate_code_internal(cris_env_get_cpu(env), tb, false);
3362 void gen_intermediate_code_pc (CPUCRISState *env, struct TranslationBlock *tb)
3364 gen_intermediate_code_internal(cris_env_get_cpu(env), tb, true);
3367 void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3370 CRISCPU *cpu = CRIS_CPU(cs);
3371 CPUCRISState *env = &cpu->env;
3379 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3380 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3381 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3383 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3386 for (i = 0; i < 16; i++) {
3387 cpu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]);
3388 if ((i + 1) % 4 == 0) {
3389 cpu_fprintf(f, "\n");
3392 cpu_fprintf(f, "\nspecial regs:\n");
3393 for (i = 0; i < 16; i++) {
3394 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3395 if ((i + 1) % 4 == 0) {
3396 cpu_fprintf(f, "\n");
3399 srs = env->pregs[PR_SRS];
3400 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3401 if (srs < ARRAY_SIZE(env->sregs)) {
3402 for (i = 0; i < 16; i++) {
3403 cpu_fprintf(f, "s%2.2d=%8.8x ",
3404 i, env->sregs[srs][i]);
3405 if ((i + 1) % 4 == 0) {
3406 cpu_fprintf(f, "\n");
3410 cpu_fprintf(f, "\n\n");
3414 void cris_initialize_tcg(void)
3418 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3419 cc_x = tcg_global_mem_new(TCG_AREG0,
3420 offsetof(CPUCRISState, cc_x), "cc_x");
3421 cc_src = tcg_global_mem_new(TCG_AREG0,
3422 offsetof(CPUCRISState, cc_src), "cc_src");
3423 cc_dest = tcg_global_mem_new(TCG_AREG0,
3424 offsetof(CPUCRISState, cc_dest),
3426 cc_result = tcg_global_mem_new(TCG_AREG0,
3427 offsetof(CPUCRISState, cc_result),
3429 cc_op = tcg_global_mem_new(TCG_AREG0,
3430 offsetof(CPUCRISState, cc_op), "cc_op");
3431 cc_size = tcg_global_mem_new(TCG_AREG0,
3432 offsetof(CPUCRISState, cc_size),
3434 cc_mask = tcg_global_mem_new(TCG_AREG0,
3435 offsetof(CPUCRISState, cc_mask),
3438 env_pc = tcg_global_mem_new(TCG_AREG0,
3439 offsetof(CPUCRISState, pc),
3441 env_btarget = tcg_global_mem_new(TCG_AREG0,
3442 offsetof(CPUCRISState, btarget),
3444 env_btaken = tcg_global_mem_new(TCG_AREG0,
3445 offsetof(CPUCRISState, btaken),
3447 for (i = 0; i < 16; i++) {
3448 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3449 offsetof(CPUCRISState, regs[i]),
3452 for (i = 0; i < 16; i++) {
3453 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3454 offsetof(CPUCRISState, pregs[i]),
3459 void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos)
3461 env->pc = tcg_ctx.gen_opc_pc[pc_pos];