4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * Copyright (c) 2012 SUSE LINUX Products GmbH
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
25 #include "qemu-common.h"
29 static void cris_cpu_set_pc(CPUState *cs, vaddr value)
31 CRISCPU *cpu = CRIS_CPU(cs);
36 static bool cris_cpu_has_work(CPUState *cs)
38 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
41 /* CPUClass::reset() */
42 static void cris_cpu_reset(CPUState *s)
44 CRISCPU *cpu = CRIS_CPU(s);
45 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
46 CPUCRISState *env = &cpu->env;
51 vr = env->pregs[PR_VR];
52 memset(env, 0, offsetof(CPUCRISState, load_info));
53 env->pregs[PR_VR] = vr;
56 #if defined(CONFIG_USER_ONLY)
57 /* start in user mode with interrupts enabled. */
58 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
61 env->pregs[PR_CCS] = 0;
65 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
70 if (cpu_model == NULL) {
74 #if defined(CONFIG_USER_ONLY)
75 if (strcasecmp(cpu_model, "any") == 0) {
76 return object_class_by_name("crisv32-" TYPE_CRIS_CPU);
80 typename = g_strdup_printf("%s-" TYPE_CRIS_CPU, cpu_model);
81 oc = object_class_by_name(typename);
83 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
84 object_class_is_abstract(oc))) {
90 CRISCPU *cpu_cris_init(const char *cpu_model)
92 return CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model));
95 /* Sort alphabetically by VR. */
96 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
98 CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
99 CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
102 if (ccc_a->vr > ccc_b->vr) {
104 } else if (ccc_a->vr < ccc_b->vr) {
111 static void cris_cpu_list_entry(gpointer data, gpointer user_data)
113 ObjectClass *oc = data;
114 CPUListState *s = user_data;
115 const char *typename = object_class_get_name(oc);
118 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_CRIS_CPU));
119 (*s->cpu_fprintf)(s->file, " %s\n", name);
123 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
127 .cpu_fprintf = cpu_fprintf,
131 list = object_class_get_list(TYPE_CRIS_CPU, false);
132 list = g_slist_sort(list, cris_cpu_list_compare);
133 (*cpu_fprintf)(f, "Available CPUs:\n");
134 g_slist_foreach(list, cris_cpu_list_entry, &s);
138 static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
140 CPUState *cs = CPU(dev);
141 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
146 ccc->parent_realize(dev, errp);
149 #ifndef CONFIG_USER_ONLY
150 static void cris_cpu_set_irq(void *opaque, int irq, int level)
152 CRISCPU *cpu = opaque;
153 CPUState *cs = CPU(cpu);
154 int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
157 cpu_interrupt(cs, type);
159 cpu_reset_interrupt(cs, type);
164 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
166 CRISCPU *cc = CRIS_CPU(cpu);
167 CPUCRISState *env = &cc->env;
169 if (env->pregs[PR_VR] != 32) {
170 info->mach = bfd_mach_cris_v0_v10;
171 info->print_insn = print_insn_crisv10;
173 info->mach = bfd_mach_cris_v32;
174 info->print_insn = print_insn_crisv32;
178 static void cris_cpu_initfn(Object *obj)
180 CPUState *cs = CPU(obj);
181 CRISCPU *cpu = CRIS_CPU(obj);
182 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
183 CPUCRISState *env = &cpu->env;
184 static bool tcg_initialized;
187 cpu_exec_init(cs, &error_abort);
189 env->pregs[PR_VR] = ccc->vr;
191 #ifndef CONFIG_USER_ONLY
192 /* IRQ and NMI lines. */
193 qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
196 if (tcg_enabled() && !tcg_initialized) {
197 tcg_initialized = true;
198 if (env->pregs[PR_VR] < 32) {
199 cris_initialize_crisv10_tcg();
201 cris_initialize_tcg();
206 static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
208 CPUClass *cc = CPU_CLASS(oc);
209 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
212 cc->do_interrupt = crisv10_cpu_do_interrupt;
213 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
216 static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
218 CPUClass *cc = CPU_CLASS(oc);
219 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
222 cc->do_interrupt = crisv10_cpu_do_interrupt;
223 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
226 static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
228 CPUClass *cc = CPU_CLASS(oc);
229 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
232 cc->do_interrupt = crisv10_cpu_do_interrupt;
233 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
236 static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
238 CPUClass *cc = CPU_CLASS(oc);
239 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
242 cc->do_interrupt = crisv10_cpu_do_interrupt;
243 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
246 static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
248 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
253 #define TYPE(model) model "-" TYPE_CRIS_CPU
255 static const TypeInfo cris_cpu_model_type_infos[] = {
257 .name = TYPE("crisv8"),
258 .parent = TYPE_CRIS_CPU,
259 .class_init = crisv8_cpu_class_init,
261 .name = TYPE("crisv9"),
262 .parent = TYPE_CRIS_CPU,
263 .class_init = crisv9_cpu_class_init,
265 .name = TYPE("crisv10"),
266 .parent = TYPE_CRIS_CPU,
267 .class_init = crisv10_cpu_class_init,
269 .name = TYPE("crisv11"),
270 .parent = TYPE_CRIS_CPU,
271 .class_init = crisv11_cpu_class_init,
273 .name = TYPE("crisv32"),
274 .parent = TYPE_CRIS_CPU,
275 .class_init = crisv32_cpu_class_init,
281 static void cris_cpu_class_init(ObjectClass *oc, void *data)
283 DeviceClass *dc = DEVICE_CLASS(oc);
284 CPUClass *cc = CPU_CLASS(oc);
285 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
287 ccc->parent_realize = dc->realize;
288 dc->realize = cris_cpu_realizefn;
290 ccc->parent_reset = cc->reset;
291 cc->reset = cris_cpu_reset;
293 cc->class_by_name = cris_cpu_class_by_name;
294 cc->has_work = cris_cpu_has_work;
295 cc->do_interrupt = cris_cpu_do_interrupt;
296 cc->cpu_exec_interrupt = cris_cpu_exec_interrupt;
297 cc->dump_state = cris_cpu_dump_state;
298 cc->set_pc = cris_cpu_set_pc;
299 cc->gdb_read_register = cris_cpu_gdb_read_register;
300 cc->gdb_write_register = cris_cpu_gdb_write_register;
301 #ifdef CONFIG_USER_ONLY
302 cc->handle_mmu_fault = cris_cpu_handle_mmu_fault;
304 cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
307 cc->gdb_num_core_regs = 49;
308 cc->gdb_stop_before_watchpoint = true;
310 cc->disas_set_info = cris_disas_set_info;
313 static const TypeInfo cris_cpu_type_info = {
314 .name = TYPE_CRIS_CPU,
316 .instance_size = sizeof(CRISCPU),
317 .instance_init = cris_cpu_initfn,
319 .class_size = sizeof(CRISCPUClass),
320 .class_init = cris_cpu_class_init,
323 static void cris_cpu_register_types(void)
327 type_register_static(&cris_cpu_type_info);
328 for (i = 0; i < ARRAY_SIZE(cris_cpu_model_type_infos); i++) {
329 type_register_static(&cris_cpu_model_type_infos[i]);
333 type_init(cris_cpu_register_types)