1 #ifndef TARGET_ARM_TRANSLATE_H
2 #define TARGET_ARM_TRANSLATE_H
5 typedef struct DisasContext {
9 /* Nonzero if this instruction has been conditionally skipped. */
11 /* The label that will be jumped to when the instruction is skipped. */
13 /* Thumb-2 conditional execution bits. */
16 struct TranslationBlock *tb;
17 int singlestep_enabled;
21 #if !defined(CONFIG_USER_ONLY)
24 ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
25 bool ns; /* Use non-secure CPREG bank on access */
26 int fp_excp_el; /* FP exception EL or 0 if enabled */
27 /* Flag indicating that exceptions from secure mode are routed to EL3. */
28 bool secure_routed_to_el3;
29 bool vfp_enabled; /* FP enabled via FPSCR.EN */
32 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
33 * so that top level loop can generate correct syndrome information.
39 uint64_t features; /* CPU features bits */
40 /* Because unallocated encodings generate different exception syndrome
41 * information from traps due to FP being disabled, we can't do a single
42 * "is fp access disabled" check at a high level in the decode tree.
43 * To help in catching bugs where the access check was forgotten in some
44 * code path, we set this flag when the access check is done, and assert
45 * that it is set at the point where we actually touch the FP regs.
47 bool fp_access_checked;
48 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
49 * single-step support).
53 /* True if the insn just emitted was a load-exclusive instruction
54 * (necessary for syndrome information for single step exceptions),
55 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
58 /* True if a single-step exception will be taken to the current EL */
60 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
62 #define TMP_A64_MAX 16
64 TCGv_i64 tmp_a64[TMP_A64_MAX];
67 typedef struct DisasCompare {
73 /* Share the TCG temporaries common between 32 and 64 bit modes. */
74 extern TCGv_env cpu_env;
75 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
76 extern TCGv_i64 cpu_exclusive_addr;
77 extern TCGv_i64 cpu_exclusive_val;
78 #ifdef CONFIG_USER_ONLY
79 extern TCGv_i64 cpu_exclusive_test;
80 extern TCGv_i32 cpu_exclusive_info;
83 static inline int arm_dc_feature(DisasContext *dc, int feature)
85 return (dc->features & (1ULL << feature)) != 0;
88 static inline int get_mem_index(DisasContext *s)
93 /* Function used to determine the target exception EL when otherwise not known
96 static inline int default_exception_el(DisasContext *s)
98 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
99 * there is no secure EL1, so we route exceptions to EL3. Otherwise,
100 * exceptions can only be routed to ELs above 1, so we target the higher of
101 * 1 or the current EL.
103 return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
104 ? 3 : MAX(1, s->current_el);
107 /* target-specific extra values for is_jmp */
108 /* These instructions trap after executing, so the A32/T32 decoder must
109 * defer them until after the conditional execution state has been updated.
110 * WFI also needs special handling when single-stepping.
114 /* For instructions which unconditionally cause an exception we can skip
115 * emitting unreachable code at the end of the TB in the A64 decoder
122 #define DISAS_YIELD 10
124 #ifdef TARGET_AARCH64
125 void a64_translate_init(void);
126 void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);
127 void gen_a64_set_pc_im(uint64_t val);
128 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
129 fprintf_function cpu_fprintf, int flags);
131 static inline void a64_translate_init(void)
135 static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
139 static inline void gen_a64_set_pc_im(uint64_t val)
143 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
144 fprintf_function cpu_fprintf,
150 void arm_test_cc(DisasCompare *cmp, int cc);
151 void arm_free_cc(DisasCompare *cmp);
152 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
153 void arm_gen_test_cc(int cc, TCGLabel *label);
155 #endif /* TARGET_ARM_TRANSLATE_H */