4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
25 #include "translate.h"
26 #include "internals.h"
27 #include "qemu/host-utils.h"
29 #include "exec/semihost.h"
30 #include "exec/gen-icount.h"
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
36 #include "trace-tcg.h"
38 static TCGv_i64 cpu_X[32];
39 static TCGv_i64 cpu_pc;
41 /* Load/store exclusive handling */
42 static TCGv_i64 cpu_exclusive_high;
44 static const char *regnames[] = {
45 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
46 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
47 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
48 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
52 A64_SHIFT_TYPE_LSL = 0,
53 A64_SHIFT_TYPE_LSR = 1,
54 A64_SHIFT_TYPE_ASR = 2,
55 A64_SHIFT_TYPE_ROR = 3
58 /* Table based decoder typedefs - used when the relevant bits for decode
59 * are too awkwardly scattered across the instruction (eg SIMD).
61 typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn);
63 typedef struct AArch64DecodeTable {
66 AArch64DecodeFn *disas_fn;
69 /* Function prototype for gen_ functions for calling Neon helpers */
70 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
71 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
72 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
73 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
74 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
75 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
76 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
77 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
78 typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
79 typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
80 typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
81 typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32);
82 typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
84 /* initialize TCG globals. */
85 void a64_translate_init(void)
89 cpu_pc = tcg_global_mem_new_i64(cpu_env,
90 offsetof(CPUARMState, pc),
92 for (i = 0; i < 32; i++) {
93 cpu_X[i] = tcg_global_mem_new_i64(cpu_env,
94 offsetof(CPUARMState, xregs[i]),
98 cpu_exclusive_high = tcg_global_mem_new_i64(cpu_env,
99 offsetof(CPUARMState, exclusive_high), "exclusive_high");
102 static inline ARMMMUIdx get_a64_user_mem_index(DisasContext *s)
104 /* Return the mmu_idx to use for A64 "unprivileged load/store" insns:
105 * if EL1, access as if EL0; otherwise access at current EL
107 switch (s->mmu_idx) {
108 case ARMMMUIdx_S12NSE1:
109 return ARMMMUIdx_S12NSE0;
110 case ARMMMUIdx_S1SE1:
111 return ARMMMUIdx_S1SE0;
113 g_assert_not_reached();
119 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
120 fprintf_function cpu_fprintf, int flags)
122 ARMCPU *cpu = ARM_CPU(cs);
123 CPUARMState *env = &cpu->env;
124 uint32_t psr = pstate_read(env);
126 int el = arm_current_el(env);
127 const char *ns_status;
129 cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
130 env->pc, env->xregs[31]);
131 for (i = 0; i < 31; i++) {
132 cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
134 cpu_fprintf(f, "\n");
140 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
141 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
146 cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
148 psr & PSTATE_N ? 'N' : '-',
149 psr & PSTATE_Z ? 'Z' : '-',
150 psr & PSTATE_C ? 'C' : '-',
151 psr & PSTATE_V ? 'V' : '-',
154 psr & PSTATE_SP ? 'h' : 't');
156 if (flags & CPU_DUMP_FPU) {
158 for (i = 0; i < numvfpregs; i += 2) {
159 uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
160 uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);
161 cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ",
163 vlo = float64_val(env->vfp.regs[(i + 1) * 2]);
164 vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]);
165 cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n",
168 cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
169 vfp_get_fpcr(env), vfp_get_fpsr(env));
173 void gen_a64_set_pc_im(uint64_t val)
175 tcg_gen_movi_i64(cpu_pc, val);
178 typedef struct DisasCompare64 {
183 static void a64_test_cc(DisasCompare64 *c64, int cc)
187 arm_test_cc(&c32, cc);
189 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
190 * properly. The NE/EQ comparisons are also fine with this choice. */
191 c64->cond = c32.cond;
192 c64->value = tcg_temp_new_i64();
193 tcg_gen_ext_i32_i64(c64->value, c32.value);
198 static void a64_free_cc(DisasCompare64 *c64)
200 tcg_temp_free_i64(c64->value);
203 static void gen_exception_internal(int excp)
205 TCGv_i32 tcg_excp = tcg_const_i32(excp);
207 assert(excp_is_internal(excp));
208 gen_helper_exception_internal(cpu_env, tcg_excp);
209 tcg_temp_free_i32(tcg_excp);
212 static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
214 TCGv_i32 tcg_excp = tcg_const_i32(excp);
215 TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
216 TCGv_i32 tcg_el = tcg_const_i32(target_el);
218 gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
220 tcg_temp_free_i32(tcg_el);
221 tcg_temp_free_i32(tcg_syn);
222 tcg_temp_free_i32(tcg_excp);
225 static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
227 gen_a64_set_pc_im(s->pc - offset);
228 gen_exception_internal(excp);
229 s->is_jmp = DISAS_EXC;
232 static void gen_exception_insn(DisasContext *s, int offset, int excp,
233 uint32_t syndrome, uint32_t target_el)
235 gen_a64_set_pc_im(s->pc - offset);
236 gen_exception(excp, syndrome, target_el);
237 s->is_jmp = DISAS_EXC;
240 static void gen_ss_advance(DisasContext *s)
242 /* If the singlestep state is Active-not-pending, advance to
247 gen_helper_clear_pstate_ss(cpu_env);
251 static void gen_step_complete_exception(DisasContext *s)
253 /* We just completed step of an insn. Move from Active-not-pending
254 * to Active-pending, and then also take the swstep exception.
255 * This corresponds to making the (IMPDEF) choice to prioritize
256 * swstep exceptions over asynchronous exceptions taken to an exception
257 * level where debug is disabled. This choice has the advantage that
258 * we do not need to maintain internal state corresponding to the
259 * ISV/EX syndrome bits between completion of the step and generation
260 * of the exception, and our syndrome information is always correct.
263 gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex),
264 default_exception_el(s));
265 s->is_jmp = DISAS_EXC;
268 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
270 /* No direct tb linking with singlestep (either QEMU's or the ARM
271 * debug architecture kind) or deterministic io
273 if (s->singlestep_enabled || s->ss_active || (s->tb->cflags & CF_LAST_IO)) {
277 /* Only link tbs from inside the same guest page */
278 if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
285 static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
287 TranslationBlock *tb;
290 if (use_goto_tb(s, n, dest)) {
292 gen_a64_set_pc_im(dest);
293 tcg_gen_exit_tb((intptr_t)tb + n);
294 s->is_jmp = DISAS_TB_JUMP;
296 gen_a64_set_pc_im(dest);
298 gen_step_complete_exception(s);
299 } else if (s->singlestep_enabled) {
300 gen_exception_internal(EXCP_DEBUG);
303 s->is_jmp = DISAS_TB_JUMP;
308 static void unallocated_encoding(DisasContext *s)
310 /* Unallocated and reserved encodings are uncategorized */
311 gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
312 default_exception_el(s));
315 #define unsupported_encoding(s, insn) \
317 qemu_log_mask(LOG_UNIMP, \
318 "%s:%d: unsupported instruction encoding 0x%08x " \
319 "at pc=%016" PRIx64 "\n", \
320 __FILE__, __LINE__, insn, s->pc - 4); \
321 unallocated_encoding(s); \
324 static void init_tmp_a64_array(DisasContext *s)
326 #ifdef CONFIG_DEBUG_TCG
328 for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) {
329 TCGV_UNUSED_I64(s->tmp_a64[i]);
332 s->tmp_a64_count = 0;
335 static void free_tmp_a64(DisasContext *s)
338 for (i = 0; i < s->tmp_a64_count; i++) {
339 tcg_temp_free_i64(s->tmp_a64[i]);
341 init_tmp_a64_array(s);
344 static TCGv_i64 new_tmp_a64(DisasContext *s)
346 assert(s->tmp_a64_count < TMP_A64_MAX);
347 return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
350 static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
352 TCGv_i64 t = new_tmp_a64(s);
353 tcg_gen_movi_i64(t, 0);
358 * Register access functions
360 * These functions are used for directly accessing a register in where
361 * changes to the final register value are likely to be made. If you
362 * need to use a register for temporary calculation (e.g. index type
363 * operations) use the read_* form.
365 * B1.2.1 Register mappings
367 * In instruction register encoding 31 can refer to ZR (zero register) or
368 * the SP (stack pointer) depending on context. In QEMU's case we map SP
369 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
370 * This is the point of the _sp forms.
372 static TCGv_i64 cpu_reg(DisasContext *s, int reg)
375 return new_tmp_a64_zero(s);
381 /* register access for when 31 == SP */
382 static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg)
387 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
388 * representing the register contents. This TCGv is an auto-freed
389 * temporary so it need not be explicitly freed, and may be modified.
391 static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
393 TCGv_i64 v = new_tmp_a64(s);
396 tcg_gen_mov_i64(v, cpu_X[reg]);
398 tcg_gen_ext32u_i64(v, cpu_X[reg]);
401 tcg_gen_movi_i64(v, 0);
406 static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
408 TCGv_i64 v = new_tmp_a64(s);
410 tcg_gen_mov_i64(v, cpu_X[reg]);
412 tcg_gen_ext32u_i64(v, cpu_X[reg]);
417 /* We should have at some point before trying to access an FP register
418 * done the necessary access check, so assert that
419 * (a) we did the check and
420 * (b) we didn't then just plough ahead anyway if it failed.
421 * Print the instruction pattern in the abort message so we can figure
422 * out what we need to fix if a user encounters this problem in the wild.
424 static inline void assert_fp_access_checked(DisasContext *s)
426 #ifdef CONFIG_DEBUG_TCG
427 if (unlikely(!s->fp_access_checked || s->fp_excp_el)) {
428 fprintf(stderr, "target-arm: FP access check missing for "
429 "instruction 0x%08x\n", s->insn);
435 /* Return the offset into CPUARMState of an element of specified
436 * size, 'element' places in from the least significant end of
437 * the FP/vector register Qn.
439 static inline int vec_reg_offset(DisasContext *s, int regno,
440 int element, TCGMemOp size)
442 int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
443 #ifdef HOST_WORDS_BIGENDIAN
444 /* This is complicated slightly because vfp.regs[2n] is
445 * still the low half and vfp.regs[2n+1] the high half
446 * of the 128 bit vector, even on big endian systems.
447 * Calculate the offset assuming a fully bigendian 128 bits,
448 * then XOR to account for the order of the two 64 bit halves.
450 offs += (16 - ((element + 1) * (1 << size)));
453 offs += element * (1 << size);
455 assert_fp_access_checked(s);
459 /* Return the offset into CPUARMState of a slice (from
460 * the least significant end) of FP register Qn (ie
462 * (Note that this is not the same mapping as for A32; see cpu.h)
464 static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size)
466 int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
467 #ifdef HOST_WORDS_BIGENDIAN
468 offs += (8 - (1 << size));
470 assert_fp_access_checked(s);
474 /* Offset of the high half of the 128 bit vector Qn */
475 static inline int fp_reg_hi_offset(DisasContext *s, int regno)
477 assert_fp_access_checked(s);
478 return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]);
481 /* Convenience accessors for reading and writing single and double
482 * FP registers. Writing clears the upper parts of the associated
483 * 128 bit vector register, as required by the architecture.
484 * Note that unlike the GP register accessors, the values returned
485 * by the read functions must be manually freed.
487 static TCGv_i64 read_fp_dreg(DisasContext *s, int reg)
489 TCGv_i64 v = tcg_temp_new_i64();
491 tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64));
495 static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
497 TCGv_i32 v = tcg_temp_new_i32();
499 tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32));
503 static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
505 TCGv_i64 tcg_zero = tcg_const_i64(0);
507 tcg_gen_st_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64));
508 tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(s, reg));
509 tcg_temp_free_i64(tcg_zero);
512 static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
514 TCGv_i64 tmp = tcg_temp_new_i64();
516 tcg_gen_extu_i32_i64(tmp, v);
517 write_fp_dreg(s, reg, tmp);
518 tcg_temp_free_i64(tmp);
521 static TCGv_ptr get_fpstatus_ptr(void)
523 TCGv_ptr statusptr = tcg_temp_new_ptr();
526 /* In A64 all instructions (both FP and Neon) use the FPCR;
527 * there is no equivalent of the A32 Neon "standard FPSCR value"
528 * and all operations use vfp.fp_status.
530 offset = offsetof(CPUARMState, vfp.fp_status);
531 tcg_gen_addi_ptr(statusptr, cpu_env, offset);
535 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
536 * than the 32 bit equivalent.
538 static inline void gen_set_NZ64(TCGv_i64 result)
540 tcg_gen_extr_i64_i32(cpu_ZF, cpu_NF, result);
541 tcg_gen_or_i32(cpu_ZF, cpu_ZF, cpu_NF);
544 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
545 static inline void gen_logic_CC(int sf, TCGv_i64 result)
548 gen_set_NZ64(result);
550 tcg_gen_extrl_i64_i32(cpu_ZF, result);
551 tcg_gen_mov_i32(cpu_NF, cpu_ZF);
553 tcg_gen_movi_i32(cpu_CF, 0);
554 tcg_gen_movi_i32(cpu_VF, 0);
557 /* dest = T0 + T1; compute C, N, V and Z flags */
558 static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
561 TCGv_i64 result, flag, tmp;
562 result = tcg_temp_new_i64();
563 flag = tcg_temp_new_i64();
564 tmp = tcg_temp_new_i64();
566 tcg_gen_movi_i64(tmp, 0);
567 tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp);
569 tcg_gen_extrl_i64_i32(cpu_CF, flag);
571 gen_set_NZ64(result);
573 tcg_gen_xor_i64(flag, result, t0);
574 tcg_gen_xor_i64(tmp, t0, t1);
575 tcg_gen_andc_i64(flag, flag, tmp);
576 tcg_temp_free_i64(tmp);
577 tcg_gen_extrh_i64_i32(cpu_VF, flag);
579 tcg_gen_mov_i64(dest, result);
580 tcg_temp_free_i64(result);
581 tcg_temp_free_i64(flag);
583 /* 32 bit arithmetic */
584 TCGv_i32 t0_32 = tcg_temp_new_i32();
585 TCGv_i32 t1_32 = tcg_temp_new_i32();
586 TCGv_i32 tmp = tcg_temp_new_i32();
588 tcg_gen_movi_i32(tmp, 0);
589 tcg_gen_extrl_i64_i32(t0_32, t0);
590 tcg_gen_extrl_i64_i32(t1_32, t1);
591 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp);
592 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
593 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
594 tcg_gen_xor_i32(tmp, t0_32, t1_32);
595 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
596 tcg_gen_extu_i32_i64(dest, cpu_NF);
598 tcg_temp_free_i32(tmp);
599 tcg_temp_free_i32(t0_32);
600 tcg_temp_free_i32(t1_32);
604 /* dest = T0 - T1; compute C, N, V and Z flags */
605 static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
608 /* 64 bit arithmetic */
609 TCGv_i64 result, flag, tmp;
611 result = tcg_temp_new_i64();
612 flag = tcg_temp_new_i64();
613 tcg_gen_sub_i64(result, t0, t1);
615 gen_set_NZ64(result);
617 tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1);
618 tcg_gen_extrl_i64_i32(cpu_CF, flag);
620 tcg_gen_xor_i64(flag, result, t0);
621 tmp = tcg_temp_new_i64();
622 tcg_gen_xor_i64(tmp, t0, t1);
623 tcg_gen_and_i64(flag, flag, tmp);
624 tcg_temp_free_i64(tmp);
625 tcg_gen_extrh_i64_i32(cpu_VF, flag);
626 tcg_gen_mov_i64(dest, result);
627 tcg_temp_free_i64(flag);
628 tcg_temp_free_i64(result);
630 /* 32 bit arithmetic */
631 TCGv_i32 t0_32 = tcg_temp_new_i32();
632 TCGv_i32 t1_32 = tcg_temp_new_i32();
635 tcg_gen_extrl_i64_i32(t0_32, t0);
636 tcg_gen_extrl_i64_i32(t1_32, t1);
637 tcg_gen_sub_i32(cpu_NF, t0_32, t1_32);
638 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
639 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32);
640 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
641 tmp = tcg_temp_new_i32();
642 tcg_gen_xor_i32(tmp, t0_32, t1_32);
643 tcg_temp_free_i32(t0_32);
644 tcg_temp_free_i32(t1_32);
645 tcg_gen_and_i32(cpu_VF, cpu_VF, tmp);
646 tcg_temp_free_i32(tmp);
647 tcg_gen_extu_i32_i64(dest, cpu_NF);
651 /* dest = T0 + T1 + CF; do not compute flags. */
652 static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
654 TCGv_i64 flag = tcg_temp_new_i64();
655 tcg_gen_extu_i32_i64(flag, cpu_CF);
656 tcg_gen_add_i64(dest, t0, t1);
657 tcg_gen_add_i64(dest, dest, flag);
658 tcg_temp_free_i64(flag);
661 tcg_gen_ext32u_i64(dest, dest);
665 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
666 static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
669 TCGv_i64 result, cf_64, vf_64, tmp;
670 result = tcg_temp_new_i64();
671 cf_64 = tcg_temp_new_i64();
672 vf_64 = tcg_temp_new_i64();
673 tmp = tcg_const_i64(0);
675 tcg_gen_extu_i32_i64(cf_64, cpu_CF);
676 tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp);
677 tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp);
678 tcg_gen_extrl_i64_i32(cpu_CF, cf_64);
679 gen_set_NZ64(result);
681 tcg_gen_xor_i64(vf_64, result, t0);
682 tcg_gen_xor_i64(tmp, t0, t1);
683 tcg_gen_andc_i64(vf_64, vf_64, tmp);
684 tcg_gen_extrh_i64_i32(cpu_VF, vf_64);
686 tcg_gen_mov_i64(dest, result);
688 tcg_temp_free_i64(tmp);
689 tcg_temp_free_i64(vf_64);
690 tcg_temp_free_i64(cf_64);
691 tcg_temp_free_i64(result);
693 TCGv_i32 t0_32, t1_32, tmp;
694 t0_32 = tcg_temp_new_i32();
695 t1_32 = tcg_temp_new_i32();
696 tmp = tcg_const_i32(0);
698 tcg_gen_extrl_i64_i32(t0_32, t0);
699 tcg_gen_extrl_i64_i32(t1_32, t1);
700 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp);
701 tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp);
703 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
704 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
705 tcg_gen_xor_i32(tmp, t0_32, t1_32);
706 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
707 tcg_gen_extu_i32_i64(dest, cpu_NF);
709 tcg_temp_free_i32(tmp);
710 tcg_temp_free_i32(t1_32);
711 tcg_temp_free_i32(t0_32);
716 * Load/Store generators
720 * Store from GPR register to memory.
722 static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source,
723 TCGv_i64 tcg_addr, int size, int memidx)
726 tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size);
729 static void do_gpr_st(DisasContext *s, TCGv_i64 source,
730 TCGv_i64 tcg_addr, int size)
732 do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s));
736 * Load from memory to GPR register
738 static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
739 int size, bool is_signed, bool extend, int memidx)
741 TCGMemOp memop = s->be_data + size;
749 tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop);
751 if (extend && is_signed) {
753 tcg_gen_ext32u_i64(dest, dest);
757 static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
758 int size, bool is_signed, bool extend)
760 do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend,
765 * Store from FP register to memory
767 static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
769 /* This writes the bottom N bits of a 128 bit wide vector to memory */
770 TCGv_i64 tmp = tcg_temp_new_i64();
771 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64));
773 tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s),
776 bool be = s->be_data == MO_BE;
777 TCGv_i64 tcg_hiaddr = tcg_temp_new_i64();
779 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
780 tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),
782 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx));
783 tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),
785 tcg_temp_free_i64(tcg_hiaddr);
788 tcg_temp_free_i64(tmp);
792 * Load from memory to FP register
794 static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
796 /* This always zero-extends and writes to a full 128 bit wide vector */
797 TCGv_i64 tmplo = tcg_temp_new_i64();
801 TCGMemOp memop = s->be_data + size;
802 tmphi = tcg_const_i64(0);
803 tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
805 bool be = s->be_data == MO_BE;
808 tmphi = tcg_temp_new_i64();
809 tcg_hiaddr = tcg_temp_new_i64();
811 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
812 tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),
814 tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),
816 tcg_temp_free_i64(tcg_hiaddr);
819 tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64));
820 tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));
822 tcg_temp_free_i64(tmplo);
823 tcg_temp_free_i64(tmphi);
827 * Vector load/store helpers.
829 * The principal difference between this and a FP load is that we don't
830 * zero extend as we are filling a partial chunk of the vector register.
831 * These functions don't support 128 bit loads/stores, which would be
832 * normal load/store operations.
834 * The _i32 versions are useful when operating on 32 bit quantities
835 * (eg for floating point single or using Neon helper functions).
838 /* Get value of an element within a vector register */
839 static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
840 int element, TCGMemOp memop)
842 int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
845 tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);
848 tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);
851 tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);
854 tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);
857 tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);
860 tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);
864 tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off);
867 g_assert_not_reached();
871 static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,
872 int element, TCGMemOp memop)
874 int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
877 tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off);
880 tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off);
883 tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off);
886 tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off);
890 tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off);
893 g_assert_not_reached();
897 /* Set value of an element within a vector register */
898 static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
899 int element, TCGMemOp memop)
901 int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
904 tcg_gen_st8_i64(tcg_src, cpu_env, vect_off);
907 tcg_gen_st16_i64(tcg_src, cpu_env, vect_off);
910 tcg_gen_st32_i64(tcg_src, cpu_env, vect_off);
913 tcg_gen_st_i64(tcg_src, cpu_env, vect_off);
916 g_assert_not_reached();
920 static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
921 int destidx, int element, TCGMemOp memop)
923 int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
926 tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);
929 tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);
932 tcg_gen_st_i32(tcg_src, cpu_env, vect_off);
935 g_assert_not_reached();
939 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
940 * vector ops all need to do this).
942 static void clear_vec_high(DisasContext *s, int rd)
944 TCGv_i64 tcg_zero = tcg_const_i64(0);
946 write_vec_element(s, tcg_zero, rd, 1, MO_64);
947 tcg_temp_free_i64(tcg_zero);
950 /* Store from vector register to memory */
951 static void do_vec_st(DisasContext *s, int srcidx, int element,
952 TCGv_i64 tcg_addr, int size)
954 TCGMemOp memop = s->be_data + size;
955 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
957 read_vec_element(s, tcg_tmp, srcidx, element, size);
958 tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
960 tcg_temp_free_i64(tcg_tmp);
963 /* Load from memory to vector register */
964 static void do_vec_ld(DisasContext *s, int destidx, int element,
965 TCGv_i64 tcg_addr, int size)
967 TCGMemOp memop = s->be_data + size;
968 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
970 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
971 write_vec_element(s, tcg_tmp, destidx, element, size);
973 tcg_temp_free_i64(tcg_tmp);
976 /* Check that FP/Neon access is enabled. If it is, return
977 * true. If not, emit code to generate an appropriate exception,
978 * and return false; the caller should not emit any code for
979 * the instruction. Note that this check must happen after all
980 * unallocated-encoding checks (otherwise the syndrome information
981 * for the resulting exception will be incorrect).
983 static inline bool fp_access_check(DisasContext *s)
985 assert(!s->fp_access_checked);
986 s->fp_access_checked = true;
988 if (!s->fp_excp_el) {
992 gen_exception_insn(s, 4, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false),
998 * This utility function is for doing register extension with an
999 * optional shift. You will likely want to pass a temporary for the
1000 * destination register. See DecodeRegExtend() in the ARM ARM.
1002 static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in,
1003 int option, unsigned int shift)
1005 int extsize = extract32(option, 0, 2);
1006 bool is_signed = extract32(option, 2, 1);
1011 tcg_gen_ext8s_i64(tcg_out, tcg_in);
1014 tcg_gen_ext16s_i64(tcg_out, tcg_in);
1017 tcg_gen_ext32s_i64(tcg_out, tcg_in);
1020 tcg_gen_mov_i64(tcg_out, tcg_in);
1026 tcg_gen_ext8u_i64(tcg_out, tcg_in);
1029 tcg_gen_ext16u_i64(tcg_out, tcg_in);
1032 tcg_gen_ext32u_i64(tcg_out, tcg_in);
1035 tcg_gen_mov_i64(tcg_out, tcg_in);
1041 tcg_gen_shli_i64(tcg_out, tcg_out, shift);
1045 static inline void gen_check_sp_alignment(DisasContext *s)
1047 /* The AArch64 architecture mandates that (if enabled via PSTATE
1048 * or SCTLR bits) there is a check that SP is 16-aligned on every
1049 * SP-relative load or store (with an exception generated if it is not).
1050 * In line with general QEMU practice regarding misaligned accesses,
1051 * we omit these checks for the sake of guest program performance.
1052 * This function is provided as a hook so we can more easily add these
1053 * checks in future (possibly as a "favour catching guest program bugs
1054 * over speed" user selectable option).
1059 * This provides a simple table based table lookup decoder. It is
1060 * intended to be used when the relevant bits for decode are too
1061 * awkwardly placed and switch/if based logic would be confusing and
1062 * deeply nested. Since it's a linear search through the table, tables
1063 * should be kept small.
1065 * It returns the first handler where insn & mask == pattern, or
1066 * NULL if there is no match.
1067 * The table is terminated by an empty mask (i.e. 0)
1069 static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
1072 const AArch64DecodeTable *tptr = table;
1074 while (tptr->mask) {
1075 if ((insn & tptr->mask) == tptr->pattern) {
1076 return tptr->disas_fn;
1084 * the instruction disassembly implemented here matches
1085 * the instruction encoding classifications in chapter 3 (C3)
1086 * of the ARM Architecture Reference Manual (DDI0487A_a)
1089 /* C3.2.7 Unconditional branch (immediate)
1091 * +----+-----------+-------------------------------------+
1092 * | op | 0 0 1 0 1 | imm26 |
1093 * +----+-----------+-------------------------------------+
1095 static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
1097 uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
1099 if (insn & (1U << 31)) {
1100 /* C5.6.26 BL Branch with link */
1101 tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
1104 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1105 gen_goto_tb(s, 0, addr);
1108 /* C3.2.1 Compare & branch (immediate)
1109 * 31 30 25 24 23 5 4 0
1110 * +----+-------------+----+---------------------+--------+
1111 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1112 * +----+-------------+----+---------------------+--------+
1114 static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
1116 unsigned int sf, op, rt;
1118 TCGLabel *label_match;
1121 sf = extract32(insn, 31, 1);
1122 op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
1123 rt = extract32(insn, 0, 5);
1124 addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
1126 tcg_cmp = read_cpu_reg(s, rt, sf);
1127 label_match = gen_new_label();
1129 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1130 tcg_cmp, 0, label_match);
1132 gen_goto_tb(s, 0, s->pc);
1133 gen_set_label(label_match);
1134 gen_goto_tb(s, 1, addr);
1137 /* C3.2.5 Test & branch (immediate)
1138 * 31 30 25 24 23 19 18 5 4 0
1139 * +----+-------------+----+-------+-------------+------+
1140 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1141 * +----+-------------+----+-------+-------------+------+
1143 static void disas_test_b_imm(DisasContext *s, uint32_t insn)
1145 unsigned int bit_pos, op, rt;
1147 TCGLabel *label_match;
1150 bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
1151 op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
1152 addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
1153 rt = extract32(insn, 0, 5);
1155 tcg_cmp = tcg_temp_new_i64();
1156 tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
1157 label_match = gen_new_label();
1158 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1159 tcg_cmp, 0, label_match);
1160 tcg_temp_free_i64(tcg_cmp);
1161 gen_goto_tb(s, 0, s->pc);
1162 gen_set_label(label_match);
1163 gen_goto_tb(s, 1, addr);
1166 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1167 * 31 25 24 23 5 4 3 0
1168 * +---------------+----+---------------------+----+------+
1169 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1170 * +---------------+----+---------------------+----+------+
1172 static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
1177 if ((insn & (1 << 4)) || (insn & (1 << 24))) {
1178 unallocated_encoding(s);
1181 addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
1182 cond = extract32(insn, 0, 4);
1185 /* genuinely conditional branches */
1186 TCGLabel *label_match = gen_new_label();
1187 arm_gen_test_cc(cond, label_match);
1188 gen_goto_tb(s, 0, s->pc);
1189 gen_set_label(label_match);
1190 gen_goto_tb(s, 1, addr);
1192 /* 0xe and 0xf are both "always" conditions */
1193 gen_goto_tb(s, 0, addr);
1198 static void handle_hint(DisasContext *s, uint32_t insn,
1199 unsigned int op1, unsigned int op2, unsigned int crm)
1201 unsigned int selector = crm << 3 | op2;
1204 unallocated_encoding(s);
1212 s->is_jmp = DISAS_WFI;
1215 s->is_jmp = DISAS_YIELD;
1218 s->is_jmp = DISAS_WFE;
1222 /* we treat all as NOP at least for now */
1225 /* default specified as NOP equivalent */
1230 static void gen_clrex(DisasContext *s, uint32_t insn)
1232 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
1235 /* CLREX, DSB, DMB, ISB */
1236 static void handle_sync(DisasContext *s, uint32_t insn,
1237 unsigned int op1, unsigned int op2, unsigned int crm)
1240 unallocated_encoding(s);
1250 /* We don't emulate caches so barriers are no-ops */
1253 /* We need to break the TB after this insn to execute
1254 * a self-modified code correctly and also to take
1255 * any pending interrupts immediately.
1257 s->is_jmp = DISAS_UPDATE;
1260 unallocated_encoding(s);
1265 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1266 static void handle_msr_i(DisasContext *s, uint32_t insn,
1267 unsigned int op1, unsigned int op2, unsigned int crm)
1269 int op = op1 << 3 | op2;
1271 case 0x05: /* SPSel */
1272 if (s->current_el == 0) {
1273 unallocated_encoding(s);
1277 case 0x1e: /* DAIFSet */
1278 case 0x1f: /* DAIFClear */
1280 TCGv_i32 tcg_imm = tcg_const_i32(crm);
1281 TCGv_i32 tcg_op = tcg_const_i32(op);
1282 gen_a64_set_pc_im(s->pc - 4);
1283 gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm);
1284 tcg_temp_free_i32(tcg_imm);
1285 tcg_temp_free_i32(tcg_op);
1286 s->is_jmp = DISAS_UPDATE;
1290 unallocated_encoding(s);
1295 static void gen_get_nzcv(TCGv_i64 tcg_rt)
1297 TCGv_i32 tmp = tcg_temp_new_i32();
1298 TCGv_i32 nzcv = tcg_temp_new_i32();
1300 /* build bit 31, N */
1301 tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31));
1302 /* build bit 30, Z */
1303 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0);
1304 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1);
1305 /* build bit 29, C */
1306 tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1);
1307 /* build bit 28, V */
1308 tcg_gen_shri_i32(tmp, cpu_VF, 31);
1309 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1);
1310 /* generate result */
1311 tcg_gen_extu_i32_i64(tcg_rt, nzcv);
1313 tcg_temp_free_i32(nzcv);
1314 tcg_temp_free_i32(tmp);
1317 static void gen_set_nzcv(TCGv_i64 tcg_rt)
1320 TCGv_i32 nzcv = tcg_temp_new_i32();
1322 /* take NZCV from R[t] */
1323 tcg_gen_extrl_i64_i32(nzcv, tcg_rt);
1326 tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31));
1328 tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30));
1329 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0);
1331 tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29));
1332 tcg_gen_shri_i32(cpu_CF, cpu_CF, 29);
1334 tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28));
1335 tcg_gen_shli_i32(cpu_VF, cpu_VF, 3);
1336 tcg_temp_free_i32(nzcv);
1339 /* C5.6.129 MRS - move from system register
1340 * C5.6.131 MSR (register) - move to system register
1343 * These are all essentially the same insn in 'read' and 'write'
1344 * versions, with varying op0 fields.
1346 static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
1347 unsigned int op0, unsigned int op1, unsigned int op2,
1348 unsigned int crn, unsigned int crm, unsigned int rt)
1350 const ARMCPRegInfo *ri;
1353 ri = get_arm_cp_reginfo(s->cp_regs,
1354 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
1355 crn, crm, op0, op1, op2));
1358 /* Unknown register; this might be a guest error or a QEMU
1359 * unimplemented feature.
1361 qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 "
1362 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1363 isread ? "read" : "write", op0, op1, crn, crm, op2);
1364 unallocated_encoding(s);
1368 /* Check access permissions */
1369 if (!cp_access_ok(s->current_el, ri, isread)) {
1370 unallocated_encoding(s);
1375 /* Emit code to perform further access permissions checks at
1376 * runtime; this may result in an exception.
1379 TCGv_i32 tcg_syn, tcg_isread;
1382 gen_a64_set_pc_im(s->pc - 4);
1383 tmpptr = tcg_const_ptr(ri);
1384 syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
1385 tcg_syn = tcg_const_i32(syndrome);
1386 tcg_isread = tcg_const_i32(isread);
1387 gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread);
1388 tcg_temp_free_ptr(tmpptr);
1389 tcg_temp_free_i32(tcg_syn);
1390 tcg_temp_free_i32(tcg_isread);
1393 /* Handle special cases first */
1394 switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
1398 tcg_rt = cpu_reg(s, rt);
1400 gen_get_nzcv(tcg_rt);
1402 gen_set_nzcv(tcg_rt);
1405 case ARM_CP_CURRENTEL:
1406 /* Reads as current EL value from pstate, which is
1407 * guaranteed to be constant by the tb flags.
1409 tcg_rt = cpu_reg(s, rt);
1410 tcg_gen_movi_i64(tcg_rt, s->current_el << 2);
1413 /* Writes clear the aligned block of memory which rt points into. */
1414 tcg_rt = cpu_reg(s, rt);
1415 gen_helper_dc_zva(cpu_env, tcg_rt);
1421 if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
1425 tcg_rt = cpu_reg(s, rt);
1428 if (ri->type & ARM_CP_CONST) {
1429 tcg_gen_movi_i64(tcg_rt, ri->resetvalue);
1430 } else if (ri->readfn) {
1432 tmpptr = tcg_const_ptr(ri);
1433 gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr);
1434 tcg_temp_free_ptr(tmpptr);
1436 tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
1439 if (ri->type & ARM_CP_CONST) {
1440 /* If not forbidden by access permissions, treat as WI */
1442 } else if (ri->writefn) {
1444 tmpptr = tcg_const_ptr(ri);
1445 gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt);
1446 tcg_temp_free_ptr(tmpptr);
1448 tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
1452 if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
1453 /* I/O operations must end the TB here (whether read or write) */
1455 s->is_jmp = DISAS_UPDATE;
1456 } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
1457 /* We default to ending the TB on a coprocessor register write,
1458 * but allow this to be suppressed by the register definition
1459 * (usually only necessary to work around guest bugs).
1461 s->is_jmp = DISAS_UPDATE;
1466 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1467 * +---------------------+---+-----+-----+-------+-------+-----+------+
1468 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1469 * +---------------------+---+-----+-----+-------+-------+-----+------+
1471 static void disas_system(DisasContext *s, uint32_t insn)
1473 unsigned int l, op0, op1, crn, crm, op2, rt;
1474 l = extract32(insn, 21, 1);
1475 op0 = extract32(insn, 19, 2);
1476 op1 = extract32(insn, 16, 3);
1477 crn = extract32(insn, 12, 4);
1478 crm = extract32(insn, 8, 4);
1479 op2 = extract32(insn, 5, 3);
1480 rt = extract32(insn, 0, 5);
1483 if (l || rt != 31) {
1484 unallocated_encoding(s);
1488 case 2: /* C5.6.68 HINT */
1489 handle_hint(s, insn, op1, op2, crm);
1491 case 3: /* CLREX, DSB, DMB, ISB */
1492 handle_sync(s, insn, op1, op2, crm);
1494 case 4: /* C5.6.130 MSR (immediate) */
1495 handle_msr_i(s, insn, op1, op2, crm);
1498 unallocated_encoding(s);
1503 handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
1506 /* C3.2.3 Exception generation
1508 * 31 24 23 21 20 5 4 2 1 0
1509 * +-----------------+-----+------------------------+-----+----+
1510 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1511 * +-----------------------+------------------------+----------+
1513 static void disas_exc(DisasContext *s, uint32_t insn)
1515 int opc = extract32(insn, 21, 3);
1516 int op2_ll = extract32(insn, 0, 5);
1517 int imm16 = extract32(insn, 5, 16);
1522 /* For SVC, HVC and SMC we advance the single-step state
1523 * machine before taking the exception. This is architecturally
1524 * mandated, to ensure that single-stepping a system call
1525 * instruction works properly.
1530 gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16),
1531 default_exception_el(s));
1534 if (s->current_el == 0) {
1535 unallocated_encoding(s);
1538 /* The pre HVC helper handles cases when HVC gets trapped
1539 * as an undefined insn by runtime configuration.
1541 gen_a64_set_pc_im(s->pc - 4);
1542 gen_helper_pre_hvc(cpu_env);
1544 gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2);
1547 if (s->current_el == 0) {
1548 unallocated_encoding(s);
1551 gen_a64_set_pc_im(s->pc - 4);
1552 tmp = tcg_const_i32(syn_aa64_smc(imm16));
1553 gen_helper_pre_smc(cpu_env, tmp);
1554 tcg_temp_free_i32(tmp);
1556 gen_exception_insn(s, 0, EXCP_SMC, syn_aa64_smc(imm16), 3);
1559 unallocated_encoding(s);
1565 unallocated_encoding(s);
1569 gen_exception_insn(s, 4, EXCP_BKPT, syn_aa64_bkpt(imm16),
1570 default_exception_el(s));
1574 unallocated_encoding(s);
1577 /* HLT. This has two purposes.
1578 * Architecturally, it is an external halting debug instruction.
1579 * Since QEMU doesn't implement external debug, we treat this as
1580 * it is required for halting debug disabled: it will UNDEF.
1581 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1583 if (semihosting_enabled() && imm16 == 0xf000) {
1584 #ifndef CONFIG_USER_ONLY
1585 /* In system mode, don't allow userspace access to semihosting,
1586 * to provide some semblance of security (and for consistency
1587 * with our 32-bit semihosting).
1589 if (s->current_el == 0) {
1590 unsupported_encoding(s, insn);
1594 gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
1596 unsupported_encoding(s, insn);
1600 if (op2_ll < 1 || op2_ll > 3) {
1601 unallocated_encoding(s);
1604 /* DCPS1, DCPS2, DCPS3 */
1605 unsupported_encoding(s, insn);
1608 unallocated_encoding(s);
1613 /* C3.2.7 Unconditional branch (register)
1614 * 31 25 24 21 20 16 15 10 9 5 4 0
1615 * +---------------+-------+-------+-------+------+-------+
1616 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1617 * +---------------+-------+-------+-------+------+-------+
1619 static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
1621 unsigned int opc, op2, op3, rn, op4;
1623 opc = extract32(insn, 21, 4);
1624 op2 = extract32(insn, 16, 5);
1625 op3 = extract32(insn, 10, 6);
1626 rn = extract32(insn, 5, 5);
1627 op4 = extract32(insn, 0, 5);
1629 if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) {
1630 unallocated_encoding(s);
1637 tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
1640 tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
1641 tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
1644 if (s->current_el == 0) {
1645 unallocated_encoding(s);
1648 gen_helper_exception_return(cpu_env);
1649 s->is_jmp = DISAS_JUMP;
1653 unallocated_encoding(s);
1655 unsupported_encoding(s, insn);
1659 unallocated_encoding(s);
1663 s->is_jmp = DISAS_JUMP;
1666 /* C3.2 Branches, exception generating and system instructions */
1667 static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
1669 switch (extract32(insn, 25, 7)) {
1670 case 0x0a: case 0x0b:
1671 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1672 disas_uncond_b_imm(s, insn);
1674 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1675 disas_comp_b_imm(s, insn);
1677 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1678 disas_test_b_imm(s, insn);
1680 case 0x2a: /* Conditional branch (immediate) */
1681 disas_cond_b_imm(s, insn);
1683 case 0x6a: /* Exception generation / System */
1684 if (insn & (1 << 24)) {
1685 disas_system(s, insn);
1690 case 0x6b: /* Unconditional branch (register) */
1691 disas_uncond_b_reg(s, insn);
1694 unallocated_encoding(s);
1700 * Load/Store exclusive instructions are implemented by remembering
1701 * the value/address loaded, and seeing if these are the same
1702 * when the store is performed. This is not actually the architecturally
1703 * mandated semantics, but it works for typical guest code sequences
1704 * and avoids having to monitor regular stores.
1706 * In system emulation mode only one CPU will be running at once, so
1707 * this sequence is effectively atomic. In user emulation mode we
1708 * throw an exception and handle the atomic operation elsewhere.
1710 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
1711 TCGv_i64 addr, int size, bool is_pair)
1713 TCGv_i64 tmp = tcg_temp_new_i64();
1714 TCGMemOp memop = s->be_data + size;
1716 g_assert(size <= 3);
1717 tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop);
1720 TCGv_i64 addr2 = tcg_temp_new_i64();
1721 TCGv_i64 hitmp = tcg_temp_new_i64();
1723 g_assert(size >= 2);
1724 tcg_gen_addi_i64(addr2, addr, 1 << size);
1725 tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop);
1726 tcg_temp_free_i64(addr2);
1727 tcg_gen_mov_i64(cpu_exclusive_high, hitmp);
1728 tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp);
1729 tcg_temp_free_i64(hitmp);
1732 tcg_gen_mov_i64(cpu_exclusive_val, tmp);
1733 tcg_gen_mov_i64(cpu_reg(s, rt), tmp);
1735 tcg_temp_free_i64(tmp);
1736 tcg_gen_mov_i64(cpu_exclusive_addr, addr);
1739 #ifdef CONFIG_USER_ONLY
1740 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
1741 TCGv_i64 addr, int size, int is_pair)
1743 tcg_gen_mov_i64(cpu_exclusive_test, addr);
1744 tcg_gen_movi_i32(cpu_exclusive_info,
1745 size | is_pair << 2 | (rd << 4) | (rt << 9) | (rt2 << 14));
1746 gen_exception_internal_insn(s, 4, EXCP_STREX);
1749 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
1750 TCGv_i64 inaddr, int size, int is_pair)
1752 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1753 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1756 * [addr + datasize] = {Rt2};
1762 * env->exclusive_addr = -1;
1764 TCGLabel *fail_label = gen_new_label();
1765 TCGLabel *done_label = gen_new_label();
1766 TCGv_i64 addr = tcg_temp_local_new_i64();
1769 /* Copy input into a local temp so it is not trashed when the
1770 * basic block ends at the branch insn.
1772 tcg_gen_mov_i64(addr, inaddr);
1773 tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
1775 tmp = tcg_temp_new_i64();
1776 tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), s->be_data + size);
1777 tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
1778 tcg_temp_free_i64(tmp);
1781 TCGv_i64 addrhi = tcg_temp_new_i64();
1782 TCGv_i64 tmphi = tcg_temp_new_i64();
1784 tcg_gen_addi_i64(addrhi, addr, 1 << size);
1785 tcg_gen_qemu_ld_i64(tmphi, addrhi, get_mem_index(s),
1787 tcg_gen_brcond_i64(TCG_COND_NE, tmphi, cpu_exclusive_high, fail_label);
1789 tcg_temp_free_i64(tmphi);
1790 tcg_temp_free_i64(addrhi);
1793 /* We seem to still have the exclusive monitor, so do the store */
1794 tcg_gen_qemu_st_i64(cpu_reg(s, rt), addr, get_mem_index(s),
1797 TCGv_i64 addrhi = tcg_temp_new_i64();
1799 tcg_gen_addi_i64(addrhi, addr, 1 << size);
1800 tcg_gen_qemu_st_i64(cpu_reg(s, rt2), addrhi,
1801 get_mem_index(s), s->be_data + size);
1802 tcg_temp_free_i64(addrhi);
1805 tcg_temp_free_i64(addr);
1807 tcg_gen_movi_i64(cpu_reg(s, rd), 0);
1808 tcg_gen_br(done_label);
1809 gen_set_label(fail_label);
1810 tcg_gen_movi_i64(cpu_reg(s, rd), 1);
1811 gen_set_label(done_label);
1812 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
1817 /* C3.3.6 Load/store exclusive
1819 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1820 * +-----+-------------+----+---+----+------+----+-------+------+------+
1821 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1822 * +-----+-------------+----+---+----+------+----+-------+------+------+
1824 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1825 * L: 0 -> store, 1 -> load
1826 * o2: 0 -> exclusive, 1 -> not
1827 * o1: 0 -> single register, 1 -> register pair
1828 * o0: 1 -> load-acquire/store-release, 0 -> not
1830 static void disas_ldst_excl(DisasContext *s, uint32_t insn)
1832 int rt = extract32(insn, 0, 5);
1833 int rn = extract32(insn, 5, 5);
1834 int rt2 = extract32(insn, 10, 5);
1835 int is_lasr = extract32(insn, 15, 1);
1836 int rs = extract32(insn, 16, 5);
1837 int is_pair = extract32(insn, 21, 1);
1838 int is_store = !extract32(insn, 22, 1);
1839 int is_excl = !extract32(insn, 23, 1);
1840 int size = extract32(insn, 30, 2);
1843 if ((!is_excl && !is_pair && !is_lasr) ||
1844 (!is_excl && is_pair) ||
1845 (is_pair && size < 2)) {
1846 unallocated_encoding(s);
1851 gen_check_sp_alignment(s);
1853 tcg_addr = read_cpu_reg_sp(s, rn, 1);
1855 /* Note that since TCG is single threaded load-acquire/store-release
1856 * semantics require no extra if (is_lasr) { ... } handling.
1862 gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
1864 gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
1867 TCGv_i64 tcg_rt = cpu_reg(s, rt);
1869 do_gpr_st(s, tcg_rt, tcg_addr, size);
1871 do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false);
1877 * C3.3.5 Load register (literal)
1879 * 31 30 29 27 26 25 24 23 5 4 0
1880 * +-----+-------+---+-----+-------------------+-------+
1881 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1882 * +-----+-------+---+-----+-------------------+-------+
1884 * V: 1 -> vector (simd/fp)
1885 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1886 * 10-> 32 bit signed, 11 -> prefetch
1887 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1889 static void disas_ld_lit(DisasContext *s, uint32_t insn)
1891 int rt = extract32(insn, 0, 5);
1892 int64_t imm = sextract32(insn, 5, 19) << 2;
1893 bool is_vector = extract32(insn, 26, 1);
1894 int opc = extract32(insn, 30, 2);
1895 bool is_signed = false;
1897 TCGv_i64 tcg_rt, tcg_addr;
1901 unallocated_encoding(s);
1905 if (!fp_access_check(s)) {
1910 /* PRFM (literal) : prefetch */
1913 size = 2 + extract32(opc, 0, 1);
1914 is_signed = extract32(opc, 1, 1);
1917 tcg_rt = cpu_reg(s, rt);
1919 tcg_addr = tcg_const_i64((s->pc - 4) + imm);
1921 do_fp_ld(s, rt, tcg_addr, size);
1923 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
1925 tcg_temp_free_i64(tcg_addr);
1929 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1930 * C5.6.81 LDP (Load Pair - non vector)
1931 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1932 * C5.6.176 STNP (Store Pair - non-temporal hint)
1933 * C5.6.177 STP (Store Pair - non vector)
1934 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1935 * C6.3.165 LDP (Load Pair of SIMD&FP)
1936 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1937 * C6.3.284 STP (Store Pair of SIMD&FP)
1939 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1940 * +-----+-------+---+---+-------+---+-----------------------------+
1941 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1942 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1944 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1946 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1947 * V: 0 -> GPR, 1 -> Vector
1948 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1949 * 10 -> signed offset, 11 -> pre-index
1950 * L: 0 -> Store 1 -> Load
1952 * Rt, Rt2 = GPR or SIMD registers to be stored
1953 * Rn = general purpose register containing address
1954 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1956 static void disas_ldst_pair(DisasContext *s, uint32_t insn)
1958 int rt = extract32(insn, 0, 5);
1959 int rn = extract32(insn, 5, 5);
1960 int rt2 = extract32(insn, 10, 5);
1961 uint64_t offset = sextract64(insn, 15, 7);
1962 int index = extract32(insn, 23, 2);
1963 bool is_vector = extract32(insn, 26, 1);
1964 bool is_load = extract32(insn, 22, 1);
1965 int opc = extract32(insn, 30, 2);
1967 bool is_signed = false;
1968 bool postindex = false;
1971 TCGv_i64 tcg_addr; /* calculated address */
1975 unallocated_encoding(s);
1982 size = 2 + extract32(opc, 1, 1);
1983 is_signed = extract32(opc, 0, 1);
1984 if (!is_load && is_signed) {
1985 unallocated_encoding(s);
1991 case 1: /* post-index */
1996 /* signed offset with "non-temporal" hint. Since we don't emulate
1997 * caches we don't care about hints to the cache system about
1998 * data access patterns, and handle this identically to plain
2002 /* There is no non-temporal-hint version of LDPSW */
2003 unallocated_encoding(s);
2008 case 2: /* signed offset, rn not updated */
2011 case 3: /* pre-index */
2017 if (is_vector && !fp_access_check(s)) {
2024 gen_check_sp_alignment(s);
2027 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2030 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
2035 do_fp_ld(s, rt, tcg_addr, size);
2037 do_fp_st(s, rt, tcg_addr, size);
2040 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2042 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
2044 do_gpr_st(s, tcg_rt, tcg_addr, size);
2047 tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
2050 do_fp_ld(s, rt2, tcg_addr, size);
2052 do_fp_st(s, rt2, tcg_addr, size);
2055 TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);
2057 do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false);
2059 do_gpr_st(s, tcg_rt2, tcg_addr, size);
2065 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size));
2067 tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size);
2069 tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
2074 * C3.3.8 Load/store (immediate post-indexed)
2075 * C3.3.9 Load/store (immediate pre-indexed)
2076 * C3.3.12 Load/store (unscaled immediate)
2078 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2079 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2080 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2081 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2083 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2085 * V = 0 -> non-vector
2086 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2087 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2089 static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn)
2091 int rt = extract32(insn, 0, 5);
2092 int rn = extract32(insn, 5, 5);
2093 int imm9 = sextract32(insn, 12, 9);
2094 int opc = extract32(insn, 22, 2);
2095 int size = extract32(insn, 30, 2);
2096 int idx = extract32(insn, 10, 2);
2097 bool is_signed = false;
2098 bool is_store = false;
2099 bool is_extended = false;
2100 bool is_unpriv = (idx == 2);
2101 bool is_vector = extract32(insn, 26, 1);
2108 size |= (opc & 2) << 1;
2109 if (size > 4 || is_unpriv) {
2110 unallocated_encoding(s);
2113 is_store = ((opc & 1) == 0);
2114 if (!fp_access_check(s)) {
2118 if (size == 3 && opc == 2) {
2119 /* PRFM - prefetch */
2121 unallocated_encoding(s);
2126 if (opc == 3 && size > 1) {
2127 unallocated_encoding(s);
2130 is_store = (opc == 0);
2131 is_signed = opc & (1<<1);
2132 is_extended = (size < 3) && (opc & 1);
2152 gen_check_sp_alignment(s);
2154 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2157 tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
2162 do_fp_st(s, rt, tcg_addr, size);
2164 do_fp_ld(s, rt, tcg_addr, size);
2167 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2168 int memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s);
2171 do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx);
2173 do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size,
2174 is_signed, is_extended, memidx);
2179 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
2181 tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
2183 tcg_gen_mov_i64(tcg_rn, tcg_addr);
2188 * C3.3.10 Load/store (register offset)
2190 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2191 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2192 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2193 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2196 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2197 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2199 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2200 * opc<0>: 0 -> store, 1 -> load
2201 * V: 1 -> vector/simd
2202 * opt: extend encoding (see DecodeRegExtend)
2203 * S: if S=1 then scale (essentially index by sizeof(size))
2204 * Rt: register to transfer into/out of
2205 * Rn: address register or SP for base
2206 * Rm: offset register or ZR for offset
2208 static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn)
2210 int rt = extract32(insn, 0, 5);
2211 int rn = extract32(insn, 5, 5);
2212 int shift = extract32(insn, 12, 1);
2213 int rm = extract32(insn, 16, 5);
2214 int opc = extract32(insn, 22, 2);
2215 int opt = extract32(insn, 13, 3);
2216 int size = extract32(insn, 30, 2);
2217 bool is_signed = false;
2218 bool is_store = false;
2219 bool is_extended = false;
2220 bool is_vector = extract32(insn, 26, 1);
2225 if (extract32(opt, 1, 1) == 0) {
2226 unallocated_encoding(s);
2231 size |= (opc & 2) << 1;
2233 unallocated_encoding(s);
2236 is_store = !extract32(opc, 0, 1);
2237 if (!fp_access_check(s)) {
2241 if (size == 3 && opc == 2) {
2242 /* PRFM - prefetch */
2245 if (opc == 3 && size > 1) {
2246 unallocated_encoding(s);
2249 is_store = (opc == 0);
2250 is_signed = extract32(opc, 1, 1);
2251 is_extended = (size < 3) && extract32(opc, 0, 1);
2255 gen_check_sp_alignment(s);
2257 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2259 tcg_rm = read_cpu_reg(s, rm, 1);
2260 ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
2262 tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm);
2266 do_fp_st(s, rt, tcg_addr, size);
2268 do_fp_ld(s, rt, tcg_addr, size);
2271 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2273 do_gpr_st(s, tcg_rt, tcg_addr, size);
2275 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended);
2281 * C3.3.13 Load/store (unsigned immediate)
2283 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2284 * +----+-------+---+-----+-----+------------+-------+------+
2285 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2286 * +----+-------+---+-----+-----+------------+-------+------+
2289 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2290 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2292 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2293 * opc<0>: 0 -> store, 1 -> load
2294 * Rn: base address register (inc SP)
2295 * Rt: target register
2297 static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn)
2299 int rt = extract32(insn, 0, 5);
2300 int rn = extract32(insn, 5, 5);
2301 unsigned int imm12 = extract32(insn, 10, 12);
2302 bool is_vector = extract32(insn, 26, 1);
2303 int size = extract32(insn, 30, 2);
2304 int opc = extract32(insn, 22, 2);
2305 unsigned int offset;
2310 bool is_signed = false;
2311 bool is_extended = false;
2314 size |= (opc & 2) << 1;
2316 unallocated_encoding(s);
2319 is_store = !extract32(opc, 0, 1);
2320 if (!fp_access_check(s)) {
2324 if (size == 3 && opc == 2) {
2325 /* PRFM - prefetch */
2328 if (opc == 3 && size > 1) {
2329 unallocated_encoding(s);
2332 is_store = (opc == 0);
2333 is_signed = extract32(opc, 1, 1);
2334 is_extended = (size < 3) && extract32(opc, 0, 1);
2338 gen_check_sp_alignment(s);
2340 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2341 offset = imm12 << size;
2342 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
2346 do_fp_st(s, rt, tcg_addr, size);
2348 do_fp_ld(s, rt, tcg_addr, size);
2351 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2353 do_gpr_st(s, tcg_rt, tcg_addr, size);
2355 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended);
2360 /* Load/store register (all forms) */
2361 static void disas_ldst_reg(DisasContext *s, uint32_t insn)
2363 switch (extract32(insn, 24, 2)) {
2365 if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) {
2366 disas_ldst_reg_roffset(s, insn);
2368 /* Load/store register (unscaled immediate)
2369 * Load/store immediate pre/post-indexed
2370 * Load/store register unprivileged
2372 disas_ldst_reg_imm9(s, insn);
2376 disas_ldst_reg_unsigned_imm(s, insn);
2379 unallocated_encoding(s);
2384 /* C3.3.1 AdvSIMD load/store multiple structures
2386 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2387 * +---+---+---------------+---+-------------+--------+------+------+------+
2388 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2389 * +---+---+---------------+---+-------------+--------+------+------+------+
2391 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2393 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2394 * +---+---+---------------+---+---+---------+--------+------+------+------+
2395 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2396 * +---+---+---------------+---+---+---------+--------+------+------+------+
2398 * Rt: first (or only) SIMD&FP register to be transferred
2399 * Rn: base address or SP
2400 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2402 static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
2404 int rt = extract32(insn, 0, 5);
2405 int rn = extract32(insn, 5, 5);
2406 int size = extract32(insn, 10, 2);
2407 int opcode = extract32(insn, 12, 4);
2408 bool is_store = !extract32(insn, 22, 1);
2409 bool is_postidx = extract32(insn, 23, 1);
2410 bool is_q = extract32(insn, 30, 1);
2411 TCGv_i64 tcg_addr, tcg_rn;
2413 int ebytes = 1 << size;
2414 int elements = (is_q ? 128 : 64) / (8 << size);
2415 int rpt; /* num iterations */
2416 int selem; /* structure elements */
2419 if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) {
2420 unallocated_encoding(s);
2424 /* From the shared decode logic */
2455 unallocated_encoding(s);
2459 if (size == 3 && !is_q && selem != 1) {
2461 unallocated_encoding(s);
2465 if (!fp_access_check(s)) {
2470 gen_check_sp_alignment(s);
2473 tcg_rn = cpu_reg_sp(s, rn);
2474 tcg_addr = tcg_temp_new_i64();
2475 tcg_gen_mov_i64(tcg_addr, tcg_rn);
2477 for (r = 0; r < rpt; r++) {
2479 for (e = 0; e < elements; e++) {
2480 int tt = (rt + r) % 32;
2482 for (xs = 0; xs < selem; xs++) {
2484 do_vec_st(s, tt, e, tcg_addr, size);
2486 do_vec_ld(s, tt, e, tcg_addr, size);
2488 /* For non-quad operations, setting a slice of the low
2489 * 64 bits of the register clears the high 64 bits (in
2490 * the ARM ARM pseudocode this is implicit in the fact
2491 * that 'rval' is a 64 bit wide variable). We optimize
2492 * by noticing that we only need to do this the first
2493 * time we touch a register.
2495 if (!is_q && e == 0 && (r == 0 || xs == selem - 1)) {
2496 clear_vec_high(s, tt);
2499 tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
2506 int rm = extract32(insn, 16, 5);
2508 tcg_gen_mov_i64(tcg_rn, tcg_addr);
2510 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
2513 tcg_temp_free_i64(tcg_addr);
2516 /* C3.3.3 AdvSIMD load/store single structure
2518 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2519 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2520 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2521 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2523 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2525 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2526 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2527 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2528 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2530 * Rt: first (or only) SIMD&FP register to be transferred
2531 * Rn: base address or SP
2532 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2533 * index = encoded in Q:S:size dependent on size
2535 * lane_size = encoded in R, opc
2536 * transfer width = encoded in opc, S, size
2538 static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
2540 int rt = extract32(insn, 0, 5);
2541 int rn = extract32(insn, 5, 5);
2542 int size = extract32(insn, 10, 2);
2543 int S = extract32(insn, 12, 1);
2544 int opc = extract32(insn, 13, 3);
2545 int R = extract32(insn, 21, 1);
2546 int is_load = extract32(insn, 22, 1);
2547 int is_postidx = extract32(insn, 23, 1);
2548 int is_q = extract32(insn, 30, 1);
2550 int scale = extract32(opc, 1, 2);
2551 int selem = (extract32(opc, 0, 1) << 1 | R) + 1;
2552 bool replicate = false;
2553 int index = is_q << 3 | S << 2 | size;
2555 TCGv_i64 tcg_addr, tcg_rn;
2559 if (!is_load || S) {
2560 unallocated_encoding(s);
2569 if (extract32(size, 0, 1)) {
2570 unallocated_encoding(s);
2576 if (extract32(size, 1, 1)) {
2577 unallocated_encoding(s);
2580 if (!extract32(size, 0, 1)) {
2584 unallocated_encoding(s);
2592 g_assert_not_reached();
2595 if (!fp_access_check(s)) {
2599 ebytes = 1 << scale;
2602 gen_check_sp_alignment(s);
2605 tcg_rn = cpu_reg_sp(s, rn);
2606 tcg_addr = tcg_temp_new_i64();
2607 tcg_gen_mov_i64(tcg_addr, tcg_rn);
2609 for (xs = 0; xs < selem; xs++) {
2611 /* Load and replicate to all elements */
2613 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
2615 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr,
2616 get_mem_index(s), s->be_data + scale);
2619 mulconst = 0x0101010101010101ULL;
2622 mulconst = 0x0001000100010001ULL;
2625 mulconst = 0x0000000100000001ULL;
2631 g_assert_not_reached();
2634 tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst);
2636 write_vec_element(s, tcg_tmp, rt, 0, MO_64);
2638 write_vec_element(s, tcg_tmp, rt, 1, MO_64);
2640 clear_vec_high(s, rt);
2642 tcg_temp_free_i64(tcg_tmp);
2644 /* Load/store one element per register */
2646 do_vec_ld(s, rt, index, tcg_addr, s->be_data + scale);
2648 do_vec_st(s, rt, index, tcg_addr, s->be_data + scale);
2651 tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
2656 int rm = extract32(insn, 16, 5);
2658 tcg_gen_mov_i64(tcg_rn, tcg_addr);
2660 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
2663 tcg_temp_free_i64(tcg_addr);
2666 /* C3.3 Loads and stores */
2667 static void disas_ldst(DisasContext *s, uint32_t insn)
2669 switch (extract32(insn, 24, 6)) {
2670 case 0x08: /* Load/store exclusive */
2671 disas_ldst_excl(s, insn);
2673 case 0x18: case 0x1c: /* Load register (literal) */
2674 disas_ld_lit(s, insn);
2676 case 0x28: case 0x29:
2677 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2678 disas_ldst_pair(s, insn);
2680 case 0x38: case 0x39:
2681 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2682 disas_ldst_reg(s, insn);
2684 case 0x0c: /* AdvSIMD load/store multiple structures */
2685 disas_ldst_multiple_struct(s, insn);
2687 case 0x0d: /* AdvSIMD load/store single structure */
2688 disas_ldst_single_struct(s, insn);
2691 unallocated_encoding(s);
2696 /* C3.4.6 PC-rel. addressing
2697 * 31 30 29 28 24 23 5 4 0
2698 * +----+-------+-----------+-------------------+------+
2699 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2700 * +----+-------+-----------+-------------------+------+
2702 static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
2704 unsigned int page, rd;
2708 page = extract32(insn, 31, 1);
2709 /* SignExtend(immhi:immlo) -> offset */
2710 offset = sextract64(insn, 5, 19);
2711 offset = offset << 2 | extract32(insn, 29, 2);
2712 rd = extract32(insn, 0, 5);
2716 /* ADRP (page based) */
2721 tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
2725 * C3.4.1 Add/subtract (immediate)
2727 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2728 * +--+--+--+-----------+-----+-------------+-----+-----+
2729 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2730 * +--+--+--+-----------+-----+-------------+-----+-----+
2732 * sf: 0 -> 32bit, 1 -> 64bit
2733 * op: 0 -> add , 1 -> sub
2735 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2737 static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
2739 int rd = extract32(insn, 0, 5);
2740 int rn = extract32(insn, 5, 5);
2741 uint64_t imm = extract32(insn, 10, 12);
2742 int shift = extract32(insn, 22, 2);
2743 bool setflags = extract32(insn, 29, 1);
2744 bool sub_op = extract32(insn, 30, 1);
2745 bool is_64bit = extract32(insn, 31, 1);
2747 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
2748 TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd);
2749 TCGv_i64 tcg_result;
2758 unallocated_encoding(s);
2762 tcg_result = tcg_temp_new_i64();
2765 tcg_gen_subi_i64(tcg_result, tcg_rn, imm);
2767 tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
2770 TCGv_i64 tcg_imm = tcg_const_i64(imm);
2772 gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
2774 gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
2776 tcg_temp_free_i64(tcg_imm);
2780 tcg_gen_mov_i64(tcg_rd, tcg_result);
2782 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
2785 tcg_temp_free_i64(tcg_result);
2788 /* The input should be a value in the bottom e bits (with higher
2789 * bits zero); returns that value replicated into every element
2790 * of size e in a 64 bit integer.
2792 static uint64_t bitfield_replicate(uint64_t mask, unsigned int e)
2802 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2803 static inline uint64_t bitmask64(unsigned int length)
2805 assert(length > 0 && length <= 64);
2806 return ~0ULL >> (64 - length);
2809 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2810 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2811 * value (ie should cause a guest UNDEF exception), and true if they are
2812 * valid, in which case the decoded bit pattern is written to result.
2814 static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
2815 unsigned int imms, unsigned int immr)
2818 unsigned e, levels, s, r;
2821 assert(immn < 2 && imms < 64 && immr < 64);
2823 /* The bit patterns we create here are 64 bit patterns which
2824 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2825 * 64 bits each. Each element contains the same value: a run
2826 * of between 1 and e-1 non-zero bits, rotated within the
2827 * element by between 0 and e-1 bits.
2829 * The element size and run length are encoded into immn (1 bit)
2830 * and imms (6 bits) as follows:
2831 * 64 bit elements: immn = 1, imms = <length of run - 1>
2832 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2833 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2834 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2835 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2836 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2837 * Notice that immn = 0, imms = 11111x is the only combination
2838 * not covered by one of the above options; this is reserved.
2839 * Further, <length of run - 1> all-ones is a reserved pattern.
2841 * In all cases the rotation is by immr % e (and immr is 6 bits).
2844 /* First determine the element size */
2845 len = 31 - clz32((immn << 6) | (~imms & 0x3f));
2847 /* This is the immn == 0, imms == 0x11111x case */
2857 /* <length of run - 1> mustn't be all-ones. */
2861 /* Create the value of one element: s+1 set bits rotated
2862 * by r within the element (which is e bits wide)...
2864 mask = bitmask64(s + 1);
2866 mask = (mask >> r) | (mask << (e - r));
2867 mask &= bitmask64(e);
2869 /* ...then replicate the element over the whole 64 bit value */
2870 mask = bitfield_replicate(mask, e);
2875 /* C3.4.4 Logical (immediate)
2876 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2877 * +----+-----+-------------+---+------+------+------+------+
2878 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2879 * +----+-----+-------------+---+------+------+------+------+
2881 static void disas_logic_imm(DisasContext *s, uint32_t insn)
2883 unsigned int sf, opc, is_n, immr, imms, rn, rd;
2884 TCGv_i64 tcg_rd, tcg_rn;
2886 bool is_and = false;
2888 sf = extract32(insn, 31, 1);
2889 opc = extract32(insn, 29, 2);
2890 is_n = extract32(insn, 22, 1);
2891 immr = extract32(insn, 16, 6);
2892 imms = extract32(insn, 10, 6);
2893 rn = extract32(insn, 5, 5);
2894 rd = extract32(insn, 0, 5);
2897 unallocated_encoding(s);
2901 if (opc == 0x3) { /* ANDS */
2902 tcg_rd = cpu_reg(s, rd);
2904 tcg_rd = cpu_reg_sp(s, rd);
2906 tcg_rn = cpu_reg(s, rn);
2908 if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) {
2909 /* some immediate field values are reserved */
2910 unallocated_encoding(s);
2915 wmask &= 0xffffffff;
2919 case 0x3: /* ANDS */
2921 tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask);
2925 tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask);
2928 tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask);
2931 assert(FALSE); /* must handle all above */
2935 if (!sf && !is_and) {
2936 /* zero extend final result; we know we can skip this for AND
2937 * since the immediate had the high 32 bits clear.
2939 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2942 if (opc == 3) { /* ANDS */
2943 gen_logic_CC(sf, tcg_rd);
2948 * C3.4.5 Move wide (immediate)
2950 * 31 30 29 28 23 22 21 20 5 4 0
2951 * +--+-----+-------------+-----+----------------+------+
2952 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2953 * +--+-----+-------------+-----+----------------+------+
2955 * sf: 0 -> 32 bit, 1 -> 64 bit
2956 * opc: 00 -> N, 10 -> Z, 11 -> K
2957 * hw: shift/16 (0,16, and sf only 32, 48)
2959 static void disas_movw_imm(DisasContext *s, uint32_t insn)
2961 int rd = extract32(insn, 0, 5);
2962 uint64_t imm = extract32(insn, 5, 16);
2963 int sf = extract32(insn, 31, 1);
2964 int opc = extract32(insn, 29, 2);
2965 int pos = extract32(insn, 21, 2) << 4;
2966 TCGv_i64 tcg_rd = cpu_reg(s, rd);
2969 if (!sf && (pos >= 32)) {
2970 unallocated_encoding(s);
2984 tcg_gen_movi_i64(tcg_rd, imm);
2987 tcg_imm = tcg_const_i64(imm);
2988 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
2989 tcg_temp_free_i64(tcg_imm);
2991 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2995 unallocated_encoding(s);
3001 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3002 * +----+-----+-------------+---+------+------+------+------+
3003 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3004 * +----+-----+-------------+---+------+------+------+------+
3006 static void disas_bitfield(DisasContext *s, uint32_t insn)
3008 unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len;
3009 TCGv_i64 tcg_rd, tcg_tmp;
3011 sf = extract32(insn, 31, 1);
3012 opc = extract32(insn, 29, 2);
3013 n = extract32(insn, 22, 1);
3014 ri = extract32(insn, 16, 6);
3015 si = extract32(insn, 10, 6);
3016 rn = extract32(insn, 5, 5);
3017 rd = extract32(insn, 0, 5);
3018 bitsize = sf ? 64 : 32;
3020 if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) {
3021 unallocated_encoding(s);
3025 tcg_rd = cpu_reg(s, rd);
3027 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3028 to be smaller than bitsize, we'll never reference data outside the
3029 low 32-bits anyway. */
3030 tcg_tmp = read_cpu_reg(s, rn, 1);
3032 /* Recognize the common aliases. */
3033 if (opc == 0) { /* SBFM */
3035 if (si == 7) { /* SXTB */
3036 tcg_gen_ext8s_i64(tcg_rd, tcg_tmp);
3038 } else if (si == 15) { /* SXTH */
3039 tcg_gen_ext16s_i64(tcg_rd, tcg_tmp);
3041 } else if (si == 31) { /* SXTW */
3042 tcg_gen_ext32s_i64(tcg_rd, tcg_tmp);
3046 if (si == 63 || (si == 31 && ri <= si)) { /* ASR */
3048 tcg_gen_ext32s_i64(tcg_tmp, tcg_tmp);
3050 tcg_gen_sari_i64(tcg_rd, tcg_tmp, ri);
3053 } else if (opc == 2) { /* UBFM */
3054 if (ri == 0) { /* UXTB, UXTH, plus non-canonical AND */
3055 tcg_gen_andi_i64(tcg_rd, tcg_tmp, bitmask64(si + 1));
3058 if (si == 63 || (si == 31 && ri <= si)) { /* LSR */
3060 tcg_gen_ext32u_i64(tcg_tmp, tcg_tmp);
3062 tcg_gen_shri_i64(tcg_rd, tcg_tmp, ri);
3065 if (si + 1 == ri && si != bitsize - 1) { /* LSL */
3066 int shift = bitsize - 1 - si;
3067 tcg_gen_shli_i64(tcg_rd, tcg_tmp, shift);
3072 if (opc != 1) { /* SBFM or UBFM */
3073 tcg_gen_movi_i64(tcg_rd, 0);
3076 /* do the bit move operation */
3078 /* Wd<s-r:0> = Wn<s:r> */
3079 tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
3081 len = (si - ri) + 1;
3083 /* Wd<32+s-r,32-r> = Wn<s:0> */
3088 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
3090 if (opc == 0) { /* SBFM - sign extend the destination field */
3091 tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len));
3092 tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len));
3096 if (!sf) { /* zero extend final result */
3097 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3102 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3103 * +----+------+-------------+---+----+------+--------+------+------+
3104 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3105 * +----+------+-------------+---+----+------+--------+------+------+
3107 static void disas_extract(DisasContext *s, uint32_t insn)
3109 unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0;
3111 sf = extract32(insn, 31, 1);
3112 n = extract32(insn, 22, 1);
3113 rm = extract32(insn, 16, 5);
3114 imm = extract32(insn, 10, 6);
3115 rn = extract32(insn, 5, 5);
3116 rd = extract32(insn, 0, 5);
3117 op21 = extract32(insn, 29, 2);
3118 op0 = extract32(insn, 21, 1);
3119 bitsize = sf ? 64 : 32;
3121 if (sf != n || op21 || op0 || imm >= bitsize) {
3122 unallocated_encoding(s);
3124 TCGv_i64 tcg_rd, tcg_rm, tcg_rn;
3126 tcg_rd = cpu_reg(s, rd);
3128 if (unlikely(imm == 0)) {
3129 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3130 * so an extract from bit 0 is a special case.
3133 tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm));
3135 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
3137 } else if (rm == rn) { /* ROR */
3138 tcg_rm = cpu_reg(s, rm);
3140 tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
3142 TCGv_i32 tmp = tcg_temp_new_i32();
3143 tcg_gen_extrl_i64_i32(tmp, tcg_rm);
3144 tcg_gen_rotri_i32(tmp, tmp, imm);
3145 tcg_gen_extu_i32_i64(tcg_rd, tmp);
3146 tcg_temp_free_i32(tmp);
3149 tcg_rm = read_cpu_reg(s, rm, sf);
3150 tcg_rn = read_cpu_reg(s, rn, sf);
3151 tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
3152 tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
3153 tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
3155 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3161 /* C3.4 Data processing - immediate */
3162 static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
3164 switch (extract32(insn, 23, 6)) {
3165 case 0x20: case 0x21: /* PC-rel. addressing */
3166 disas_pc_rel_adr(s, insn);
3168 case 0x22: case 0x23: /* Add/subtract (immediate) */
3169 disas_add_sub_imm(s, insn);
3171 case 0x24: /* Logical (immediate) */
3172 disas_logic_imm(s, insn);
3174 case 0x25: /* Move wide (immediate) */
3175 disas_movw_imm(s, insn);
3177 case 0x26: /* Bitfield */
3178 disas_bitfield(s, insn);
3180 case 0x27: /* Extract */
3181 disas_extract(s, insn);
3184 unallocated_encoding(s);
3189 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3190 * Note that it is the caller's responsibility to ensure that the
3191 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3192 * mandated semantics for out of range shifts.
3194 static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf,
3195 enum a64_shift_type shift_type, TCGv_i64 shift_amount)
3197 switch (shift_type) {
3198 case A64_SHIFT_TYPE_LSL:
3199 tcg_gen_shl_i64(dst, src, shift_amount);
3201 case A64_SHIFT_TYPE_LSR:
3202 tcg_gen_shr_i64(dst, src, shift_amount);
3204 case A64_SHIFT_TYPE_ASR:
3206 tcg_gen_ext32s_i64(dst, src);
3208 tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount);
3210 case A64_SHIFT_TYPE_ROR:
3212 tcg_gen_rotr_i64(dst, src, shift_amount);
3215 t0 = tcg_temp_new_i32();
3216 t1 = tcg_temp_new_i32();
3217 tcg_gen_extrl_i64_i32(t0, src);
3218 tcg_gen_extrl_i64_i32(t1, shift_amount);
3219 tcg_gen_rotr_i32(t0, t0, t1);
3220 tcg_gen_extu_i32_i64(dst, t0);
3221 tcg_temp_free_i32(t0);
3222 tcg_temp_free_i32(t1);
3226 assert(FALSE); /* all shift types should be handled */
3230 if (!sf) { /* zero extend final result */
3231 tcg_gen_ext32u_i64(dst, dst);
3235 /* Shift a TCGv src by immediate, put result in dst.
3236 * The shift amount must be in range (this should always be true as the
3237 * relevant instructions will UNDEF on bad shift immediates).
3239 static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
3240 enum a64_shift_type shift_type, unsigned int shift_i)
3242 assert(shift_i < (sf ? 64 : 32));
3245 tcg_gen_mov_i64(dst, src);
3247 TCGv_i64 shift_const;
3249 shift_const = tcg_const_i64(shift_i);
3250 shift_reg(dst, src, sf, shift_type, shift_const);
3251 tcg_temp_free_i64(shift_const);
3255 /* C3.5.10 Logical (shifted register)
3256 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3257 * +----+-----+-----------+-------+---+------+--------+------+------+
3258 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3259 * +----+-----+-----------+-------+---+------+--------+------+------+
3261 static void disas_logic_reg(DisasContext *s, uint32_t insn)
3263 TCGv_i64 tcg_rd, tcg_rn, tcg_rm;
3264 unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd;
3266 sf = extract32(insn, 31, 1);
3267 opc = extract32(insn, 29, 2);
3268 shift_type = extract32(insn, 22, 2);
3269 invert = extract32(insn, 21, 1);
3270 rm = extract32(insn, 16, 5);
3271 shift_amount = extract32(insn, 10, 6);
3272 rn = extract32(insn, 5, 5);
3273 rd = extract32(insn, 0, 5);
3275 if (!sf && (shift_amount & (1 << 5))) {
3276 unallocated_encoding(s);
3280 tcg_rd = cpu_reg(s, rd);
3282 if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) {
3283 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3284 * register-register MOV and MVN, so it is worth special casing.
3286 tcg_rm = cpu_reg(s, rm);
3288 tcg_gen_not_i64(tcg_rd, tcg_rm);
3290 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3294 tcg_gen_mov_i64(tcg_rd, tcg_rm);
3296 tcg_gen_ext32u_i64(tcg_rd, tcg_rm);
3302 tcg_rm = read_cpu_reg(s, rm, sf);
3305 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount);
3308 tcg_rn = cpu_reg(s, rn);
3310 switch (opc | (invert << 2)) {
3313 tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
3316 tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm);
3319 tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm);
3323 tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm);
3326 tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm);
3329 tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm);
3337 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3341 gen_logic_CC(sf, tcg_rd);
3346 * C3.5.1 Add/subtract (extended register)
3348 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3349 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3350 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3351 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3353 * sf: 0 -> 32bit, 1 -> 64bit
3354 * op: 0 -> add , 1 -> sub
3357 * option: extension type (see DecodeRegExtend)
3358 * imm3: optional shift to Rm
3360 * Rd = Rn + LSL(extend(Rm), amount)
3362 static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
3364 int rd = extract32(insn, 0, 5);
3365 int rn = extract32(insn, 5, 5);
3366 int imm3 = extract32(insn, 10, 3);
3367 int option = extract32(insn, 13, 3);
3368 int rm = extract32(insn, 16, 5);
3369 bool setflags = extract32(insn, 29, 1);
3370 bool sub_op = extract32(insn, 30, 1);
3371 bool sf = extract32(insn, 31, 1);
3373 TCGv_i64 tcg_rm, tcg_rn; /* temps */
3375 TCGv_i64 tcg_result;
3378 unallocated_encoding(s);
3382 /* non-flag setting ops may use SP */
3384 tcg_rd = cpu_reg_sp(s, rd);
3386 tcg_rd = cpu_reg(s, rd);
3388 tcg_rn = read_cpu_reg_sp(s, rn, sf);
3390 tcg_rm = read_cpu_reg(s, rm, sf);
3391 ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);
3393 tcg_result = tcg_temp_new_i64();
3397 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
3399 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
3403 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
3405 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
3410 tcg_gen_mov_i64(tcg_rd, tcg_result);
3412 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3415 tcg_temp_free_i64(tcg_result);
3419 * C3.5.2 Add/subtract (shifted register)
3421 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3422 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3423 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3424 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3426 * sf: 0 -> 32bit, 1 -> 64bit
3427 * op: 0 -> add , 1 -> sub
3429 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3430 * imm6: Shift amount to apply to Rm before the add/sub
3432 static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
3434 int rd = extract32(insn, 0, 5);
3435 int rn = extract32(insn, 5, 5);
3436 int imm6 = extract32(insn, 10, 6);
3437 int rm = extract32(insn, 16, 5);
3438 int shift_type = extract32(insn, 22, 2);
3439 bool setflags = extract32(insn, 29, 1);
3440 bool sub_op = extract32(insn, 30, 1);
3441 bool sf = extract32(insn, 31, 1);
3443 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3444 TCGv_i64 tcg_rn, tcg_rm;
3445 TCGv_i64 tcg_result;
3447 if ((shift_type == 3) || (!sf && (imm6 > 31))) {
3448 unallocated_encoding(s);
3452 tcg_rn = read_cpu_reg(s, rn, sf);
3453 tcg_rm = read_cpu_reg(s, rm, sf);
3455 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6);
3457 tcg_result = tcg_temp_new_i64();
3461 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
3463 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
3467 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
3469 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
3474 tcg_gen_mov_i64(tcg_rd, tcg_result);
3476 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3479 tcg_temp_free_i64(tcg_result);
3482 /* C3.5.9 Data-processing (3 source)
3484 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3485 +--+------+-----------+------+------+----+------+------+------+
3486 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3487 +--+------+-----------+------+------+----+------+------+------+
3490 static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
3492 int rd = extract32(insn, 0, 5);
3493 int rn = extract32(insn, 5, 5);
3494 int ra = extract32(insn, 10, 5);
3495 int rm = extract32(insn, 16, 5);
3496 int op_id = (extract32(insn, 29, 3) << 4) |
3497 (extract32(insn, 21, 3) << 1) |
3498 extract32(insn, 15, 1);
3499 bool sf = extract32(insn, 31, 1);
3500 bool is_sub = extract32(op_id, 0, 1);
3501 bool is_high = extract32(op_id, 2, 1);
3502 bool is_signed = false;
3507 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3509 case 0x42: /* SMADDL */
3510 case 0x43: /* SMSUBL */
3511 case 0x44: /* SMULH */
3514 case 0x0: /* MADD (32bit) */
3515 case 0x1: /* MSUB (32bit) */
3516 case 0x40: /* MADD (64bit) */
3517 case 0x41: /* MSUB (64bit) */
3518 case 0x4a: /* UMADDL */
3519 case 0x4b: /* UMSUBL */
3520 case 0x4c: /* UMULH */
3523 unallocated_encoding(s);
3528 TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */
3529 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3530 TCGv_i64 tcg_rn = cpu_reg(s, rn);
3531 TCGv_i64 tcg_rm = cpu_reg(s, rm);
3534 tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
3536 tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
3539 tcg_temp_free_i64(low_bits);
3543 tcg_op1 = tcg_temp_new_i64();
3544 tcg_op2 = tcg_temp_new_i64();
3545 tcg_tmp = tcg_temp_new_i64();
3548 tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn));
3549 tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm));
3552 tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn));
3553 tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm));
3555 tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn));
3556 tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm));
3560 if (ra == 31 && !is_sub) {
3561 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3562 tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2);
3564 tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2);
3566 tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
3568 tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
3573 tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd));
3576 tcg_temp_free_i64(tcg_op1);
3577 tcg_temp_free_i64(tcg_op2);
3578 tcg_temp_free_i64(tcg_tmp);
3581 /* C3.5.3 - Add/subtract (with carry)
3582 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3583 * +--+--+--+------------------------+------+---------+------+-----+
3584 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3585 * +--+--+--+------------------------+------+---------+------+-----+
3589 static void disas_adc_sbc(DisasContext *s, uint32_t insn)
3591 unsigned int sf, op, setflags, rm, rn, rd;
3592 TCGv_i64 tcg_y, tcg_rn, tcg_rd;
3594 if (extract32(insn, 10, 6) != 0) {
3595 unallocated_encoding(s);
3599 sf = extract32(insn, 31, 1);
3600 op = extract32(insn, 30, 1);
3601 setflags = extract32(insn, 29, 1);
3602 rm = extract32(insn, 16, 5);
3603 rn = extract32(insn, 5, 5);
3604 rd = extract32(insn, 0, 5);
3606 tcg_rd = cpu_reg(s, rd);
3607 tcg_rn = cpu_reg(s, rn);
3610 tcg_y = new_tmp_a64(s);
3611 tcg_gen_not_i64(tcg_y, cpu_reg(s, rm));
3613 tcg_y = cpu_reg(s, rm);
3617 gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y);
3619 gen_adc(sf, tcg_rd, tcg_rn, tcg_y);
3623 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3624 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3625 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3626 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3627 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3630 static void disas_cc(DisasContext *s, uint32_t insn)
3632 unsigned int sf, op, y, cond, rn, nzcv, is_imm;
3633 TCGv_i32 tcg_t0, tcg_t1, tcg_t2;
3634 TCGv_i64 tcg_tmp, tcg_y, tcg_rn;
3637 if (!extract32(insn, 29, 1)) {
3638 unallocated_encoding(s);
3641 if (insn & (1 << 10 | 1 << 4)) {
3642 unallocated_encoding(s);
3645 sf = extract32(insn, 31, 1);
3646 op = extract32(insn, 30, 1);
3647 is_imm = extract32(insn, 11, 1);
3648 y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */
3649 cond = extract32(insn, 12, 4);
3650 rn = extract32(insn, 5, 5);
3651 nzcv = extract32(insn, 0, 4);
3653 /* Set T0 = !COND. */
3654 tcg_t0 = tcg_temp_new_i32();
3655 arm_test_cc(&c, cond);
3656 tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0);
3659 /* Load the arguments for the new comparison. */
3661 tcg_y = new_tmp_a64(s);
3662 tcg_gen_movi_i64(tcg_y, y);
3664 tcg_y = cpu_reg(s, y);
3666 tcg_rn = cpu_reg(s, rn);
3668 /* Set the flags for the new comparison. */
3669 tcg_tmp = tcg_temp_new_i64();
3671 gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y);
3673 gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y);
3675 tcg_temp_free_i64(tcg_tmp);
3677 /* If COND was false, force the flags to #nzcv. Compute two masks
3678 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3679 * For tcg hosts that support ANDC, we can make do with just T1.
3680 * In either case, allow the tcg optimizer to delete any unused mask.
3682 tcg_t1 = tcg_temp_new_i32();
3683 tcg_t2 = tcg_temp_new_i32();
3684 tcg_gen_neg_i32(tcg_t1, tcg_t0);
3685 tcg_gen_subi_i32(tcg_t2, tcg_t0, 1);
3687 if (nzcv & 8) { /* N */
3688 tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1);
3690 if (TCG_TARGET_HAS_andc_i32) {
3691 tcg_gen_andc_i32(cpu_NF, cpu_NF, tcg_t1);
3693 tcg_gen_and_i32(cpu_NF, cpu_NF, tcg_t2);
3696 if (nzcv & 4) { /* Z */
3697 if (TCG_TARGET_HAS_andc_i32) {
3698 tcg_gen_andc_i32(cpu_ZF, cpu_ZF, tcg_t1);
3700 tcg_gen_and_i32(cpu_ZF, cpu_ZF, tcg_t2);
3703 tcg_gen_or_i32(cpu_ZF, cpu_ZF, tcg_t0);
3705 if (nzcv & 2) { /* C */
3706 tcg_gen_or_i32(cpu_CF, cpu_CF, tcg_t0);
3708 if (TCG_TARGET_HAS_andc_i32) {
3709 tcg_gen_andc_i32(cpu_CF, cpu_CF, tcg_t1);
3711 tcg_gen_and_i32(cpu_CF, cpu_CF, tcg_t2);
3714 if (nzcv & 1) { /* V */
3715 tcg_gen_or_i32(cpu_VF, cpu_VF, tcg_t1);
3717 if (TCG_TARGET_HAS_andc_i32) {
3718 tcg_gen_andc_i32(cpu_VF, cpu_VF, tcg_t1);
3720 tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2);
3723 tcg_temp_free_i32(tcg_t0);
3724 tcg_temp_free_i32(tcg_t1);
3725 tcg_temp_free_i32(tcg_t2);
3728 /* C3.5.6 Conditional select
3729 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3730 * +----+----+---+-----------------+------+------+-----+------+------+
3731 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3732 * +----+----+---+-----------------+------+------+-----+------+------+
3734 static void disas_cond_select(DisasContext *s, uint32_t insn)
3736 unsigned int sf, else_inv, rm, cond, else_inc, rn, rd;
3737 TCGv_i64 tcg_rd, zero;
3740 if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) {
3741 /* S == 1 or op2<1> == 1 */
3742 unallocated_encoding(s);
3745 sf = extract32(insn, 31, 1);
3746 else_inv = extract32(insn, 30, 1);
3747 rm = extract32(insn, 16, 5);
3748 cond = extract32(insn, 12, 4);
3749 else_inc = extract32(insn, 10, 1);
3750 rn = extract32(insn, 5, 5);
3751 rd = extract32(insn, 0, 5);
3753 tcg_rd = cpu_reg(s, rd);
3755 a64_test_cc(&c, cond);
3756 zero = tcg_const_i64(0);
3758 if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
3760 tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero);
3762 tcg_gen_neg_i64(tcg_rd, tcg_rd);
3765 TCGv_i64 t_true = cpu_reg(s, rn);
3766 TCGv_i64 t_false = read_cpu_reg(s, rm, 1);
3767 if (else_inv && else_inc) {
3768 tcg_gen_neg_i64(t_false, t_false);
3769 } else if (else_inv) {
3770 tcg_gen_not_i64(t_false, t_false);
3771 } else if (else_inc) {
3772 tcg_gen_addi_i64(t_false, t_false, 1);
3774 tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false);
3777 tcg_temp_free_i64(zero);
3781 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3785 static void handle_clz(DisasContext *s, unsigned int sf,
3786 unsigned int rn, unsigned int rd)
3788 TCGv_i64 tcg_rd, tcg_rn;
3789 tcg_rd = cpu_reg(s, rd);
3790 tcg_rn = cpu_reg(s, rn);
3793 gen_helper_clz64(tcg_rd, tcg_rn);
3795 TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
3796 tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn);
3797 gen_helper_clz(tcg_tmp32, tcg_tmp32);
3798 tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
3799 tcg_temp_free_i32(tcg_tmp32);
3803 static void handle_cls(DisasContext *s, unsigned int sf,
3804 unsigned int rn, unsigned int rd)
3806 TCGv_i64 tcg_rd, tcg_rn;
3807 tcg_rd = cpu_reg(s, rd);
3808 tcg_rn = cpu_reg(s, rn);
3811 gen_helper_cls64(tcg_rd, tcg_rn);
3813 TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
3814 tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn);
3815 gen_helper_cls32(tcg_tmp32, tcg_tmp32);
3816 tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
3817 tcg_temp_free_i32(tcg_tmp32);
3821 static void handle_rbit(DisasContext *s, unsigned int sf,
3822 unsigned int rn, unsigned int rd)
3824 TCGv_i64 tcg_rd, tcg_rn;
3825 tcg_rd = cpu_reg(s, rd);
3826 tcg_rn = cpu_reg(s, rn);
3829 gen_helper_rbit64(tcg_rd, tcg_rn);
3831 TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
3832 tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn);
3833 gen_helper_rbit(tcg_tmp32, tcg_tmp32);
3834 tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
3835 tcg_temp_free_i32(tcg_tmp32);
3839 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3840 static void handle_rev64(DisasContext *s, unsigned int sf,
3841 unsigned int rn, unsigned int rd)
3844 unallocated_encoding(s);
3847 tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
3850 /* C5.6.149 REV with sf==0, opcode==2
3851 * C5.6.151 REV32 (sf==1, opcode==2)
3853 static void handle_rev32(DisasContext *s, unsigned int sf,
3854 unsigned int rn, unsigned int rd)
3856 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3859 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
3860 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
3862 /* bswap32_i64 requires zero high word */
3863 tcg_gen_ext32u_i64(tcg_tmp, tcg_rn);
3864 tcg_gen_bswap32_i64(tcg_rd, tcg_tmp);
3865 tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
3866 tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
3867 tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp);
3869 tcg_temp_free_i64(tcg_tmp);
3871 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn));
3872 tcg_gen_bswap32_i64(tcg_rd, tcg_rd);
3876 /* C5.6.150 REV16 (opcode==1) */
3877 static void handle_rev16(DisasContext *s, unsigned int sf,
3878 unsigned int rn, unsigned int rd)
3880 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3881 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
3882 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
3884 tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff);
3885 tcg_gen_bswap16_i64(tcg_rd, tcg_tmp);
3887 tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16);
3888 tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
3889 tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
3890 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16);
3893 tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
3894 tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
3895 tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
3896 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16);
3898 tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48);
3899 tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
3900 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16);
3903 tcg_temp_free_i64(tcg_tmp);
3906 /* C3.5.7 Data-processing (1 source)
3907 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3908 * +----+---+---+-----------------+---------+--------+------+------+
3909 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3910 * +----+---+---+-----------------+---------+--------+------+------+
3912 static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
3914 unsigned int sf, opcode, rn, rd;
3916 if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) {
3917 unallocated_encoding(s);
3921 sf = extract32(insn, 31, 1);
3922 opcode = extract32(insn, 10, 6);
3923 rn = extract32(insn, 5, 5);
3924 rd = extract32(insn, 0, 5);
3928 handle_rbit(s, sf, rn, rd);
3931 handle_rev16(s, sf, rn, rd);
3934 handle_rev32(s, sf, rn, rd);
3937 handle_rev64(s, sf, rn, rd);
3940 handle_clz(s, sf, rn, rd);
3943 handle_cls(s, sf, rn, rd);
3948 static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
3949 unsigned int rm, unsigned int rn, unsigned int rd)
3951 TCGv_i64 tcg_n, tcg_m, tcg_rd;
3952 tcg_rd = cpu_reg(s, rd);
3954 if (!sf && is_signed) {
3955 tcg_n = new_tmp_a64(s);
3956 tcg_m = new_tmp_a64(s);
3957 tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn));
3958 tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm));
3960 tcg_n = read_cpu_reg(s, rn, sf);
3961 tcg_m = read_cpu_reg(s, rm, sf);
3965 gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m);
3967 gen_helper_udiv64(tcg_rd, tcg_n, tcg_m);
3970 if (!sf) { /* zero extend final result */
3971 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3975 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3976 static void handle_shift_reg(DisasContext *s,
3977 enum a64_shift_type shift_type, unsigned int sf,
3978 unsigned int rm, unsigned int rn, unsigned int rd)
3980 TCGv_i64 tcg_shift = tcg_temp_new_i64();
3981 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3982 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
3984 tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31);
3985 shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift);
3986 tcg_temp_free_i64(tcg_shift);
3989 /* CRC32[BHWX], CRC32C[BHWX] */
3990 static void handle_crc32(DisasContext *s,
3991 unsigned int sf, unsigned int sz, bool crc32c,
3992 unsigned int rm, unsigned int rn, unsigned int rd)
3994 TCGv_i64 tcg_acc, tcg_val;
3997 if (!arm_dc_feature(s, ARM_FEATURE_CRC)
3998 || (sf == 1 && sz != 3)
3999 || (sf == 0 && sz == 3)) {
4000 unallocated_encoding(s);
4005 tcg_val = cpu_reg(s, rm);
4019 g_assert_not_reached();
4021 tcg_val = new_tmp_a64(s);
4022 tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask);
4025 tcg_acc = cpu_reg(s, rn);
4026 tcg_bytes = tcg_const_i32(1 << sz);
4029 gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
4031 gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
4034 tcg_temp_free_i32(tcg_bytes);
4037 /* C3.5.8 Data-processing (2 source)
4038 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4039 * +----+---+---+-----------------+------+--------+------+------+
4040 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4041 * +----+---+---+-----------------+------+--------+------+------+
4043 static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
4045 unsigned int sf, rm, opcode, rn, rd;
4046 sf = extract32(insn, 31, 1);
4047 rm = extract32(insn, 16, 5);
4048 opcode = extract32(insn, 10, 6);
4049 rn = extract32(insn, 5, 5);
4050 rd = extract32(insn, 0, 5);
4052 if (extract32(insn, 29, 1)) {
4053 unallocated_encoding(s);
4059 handle_div(s, false, sf, rm, rn, rd);
4062 handle_div(s, true, sf, rm, rn, rd);
4065 handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
4068 handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd);
4071 handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd);
4074 handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd);
4083 case 23: /* CRC32 */
4085 int sz = extract32(opcode, 0, 2);
4086 bool crc32c = extract32(opcode, 2, 1);
4087 handle_crc32(s, sf, sz, crc32c, rm, rn, rd);
4091 unallocated_encoding(s);
4096 /* C3.5 Data processing - register */
4097 static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
4099 switch (extract32(insn, 24, 5)) {
4100 case 0x0a: /* Logical (shifted register) */
4101 disas_logic_reg(s, insn);
4103 case 0x0b: /* Add/subtract */
4104 if (insn & (1 << 21)) { /* (extended register) */
4105 disas_add_sub_ext_reg(s, insn);
4107 disas_add_sub_reg(s, insn);
4110 case 0x1b: /* Data-processing (3 source) */
4111 disas_data_proc_3src(s, insn);
4114 switch (extract32(insn, 21, 3)) {
4115 case 0x0: /* Add/subtract (with carry) */
4116 disas_adc_sbc(s, insn);
4118 case 0x2: /* Conditional compare */
4119 disas_cc(s, insn); /* both imm and reg forms */
4121 case 0x4: /* Conditional select */
4122 disas_cond_select(s, insn);
4124 case 0x6: /* Data-processing */
4125 if (insn & (1 << 30)) { /* (1 source) */
4126 disas_data_proc_1src(s, insn);
4127 } else { /* (2 source) */
4128 disas_data_proc_2src(s, insn);
4132 unallocated_encoding(s);
4137 unallocated_encoding(s);
4142 static void handle_fp_compare(DisasContext *s, bool is_double,
4143 unsigned int rn, unsigned int rm,
4144 bool cmp_with_zero, bool signal_all_nans)
4146 TCGv_i64 tcg_flags = tcg_temp_new_i64();
4147 TCGv_ptr fpst = get_fpstatus_ptr();
4150 TCGv_i64 tcg_vn, tcg_vm;
4152 tcg_vn = read_fp_dreg(s, rn);
4153 if (cmp_with_zero) {
4154 tcg_vm = tcg_const_i64(0);
4156 tcg_vm = read_fp_dreg(s, rm);
4158 if (signal_all_nans) {
4159 gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4161 gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4163 tcg_temp_free_i64(tcg_vn);
4164 tcg_temp_free_i64(tcg_vm);
4166 TCGv_i32 tcg_vn, tcg_vm;
4168 tcg_vn = read_fp_sreg(s, rn);
4169 if (cmp_with_zero) {
4170 tcg_vm = tcg_const_i32(0);
4172 tcg_vm = read_fp_sreg(s, rm);
4174 if (signal_all_nans) {
4175 gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4177 gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4179 tcg_temp_free_i32(tcg_vn);
4180 tcg_temp_free_i32(tcg_vm);
4183 tcg_temp_free_ptr(fpst);
4185 gen_set_nzcv(tcg_flags);
4187 tcg_temp_free_i64(tcg_flags);
4190 /* C3.6.22 Floating point compare
4191 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4192 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4193 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4194 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4196 static void disas_fp_compare(DisasContext *s, uint32_t insn)
4198 unsigned int mos, type, rm, op, rn, opc, op2r;
4200 mos = extract32(insn, 29, 3);
4201 type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
4202 rm = extract32(insn, 16, 5);
4203 op = extract32(insn, 14, 2);
4204 rn = extract32(insn, 5, 5);
4205 opc = extract32(insn, 3, 2);
4206 op2r = extract32(insn, 0, 3);
4208 if (mos || op || op2r || type > 1) {
4209 unallocated_encoding(s);
4213 if (!fp_access_check(s)) {
4217 handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
4220 /* C3.6.23 Floating point conditional compare
4221 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4222 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4223 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4224 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4226 static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
4228 unsigned int mos, type, rm, cond, rn, op, nzcv;
4230 TCGLabel *label_continue = NULL;
4232 mos = extract32(insn, 29, 3);
4233 type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
4234 rm = extract32(insn, 16, 5);
4235 cond = extract32(insn, 12, 4);
4236 rn = extract32(insn, 5, 5);
4237 op = extract32(insn, 4, 1);
4238 nzcv = extract32(insn, 0, 4);
4240 if (mos || type > 1) {
4241 unallocated_encoding(s);
4245 if (!fp_access_check(s)) {
4249 if (cond < 0x0e) { /* not always */
4250 TCGLabel *label_match = gen_new_label();
4251 label_continue = gen_new_label();
4252 arm_gen_test_cc(cond, label_match);
4254 tcg_flags = tcg_const_i64(nzcv << 28);
4255 gen_set_nzcv(tcg_flags);
4256 tcg_temp_free_i64(tcg_flags);
4257 tcg_gen_br(label_continue);
4258 gen_set_label(label_match);
4261 handle_fp_compare(s, type, rn, rm, false, op);
4264 gen_set_label(label_continue);
4268 /* C3.6.24 Floating point conditional select
4269 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4270 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4271 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4272 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4274 static void disas_fp_csel(DisasContext *s, uint32_t insn)
4276 unsigned int mos, type, rm, cond, rn, rd;
4277 TCGv_i64 t_true, t_false, t_zero;
4280 mos = extract32(insn, 29, 3);
4281 type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
4282 rm = extract32(insn, 16, 5);
4283 cond = extract32(insn, 12, 4);
4284 rn = extract32(insn, 5, 5);
4285 rd = extract32(insn, 0, 5);
4287 if (mos || type > 1) {
4288 unallocated_encoding(s);
4292 if (!fp_access_check(s)) {
4296 /* Zero extend sreg inputs to 64 bits now. */
4297 t_true = tcg_temp_new_i64();
4298 t_false = tcg_temp_new_i64();
4299 read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
4300 read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
4302 a64_test_cc(&c, cond);
4303 t_zero = tcg_const_i64(0);
4304 tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false);
4305 tcg_temp_free_i64(t_zero);
4306 tcg_temp_free_i64(t_false);
4309 /* Note that sregs write back zeros to the high bits,
4310 and we've already done the zero-extension. */
4311 write_fp_dreg(s, rd, t_true);
4312 tcg_temp_free_i64(t_true);
4315 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4316 static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
4322 fpst = get_fpstatus_ptr();
4323 tcg_op = read_fp_sreg(s, rn);
4324 tcg_res = tcg_temp_new_i32();
4327 case 0x0: /* FMOV */
4328 tcg_gen_mov_i32(tcg_res, tcg_op);
4330 case 0x1: /* FABS */
4331 gen_helper_vfp_abss(tcg_res, tcg_op);
4333 case 0x2: /* FNEG */
4334 gen_helper_vfp_negs(tcg_res, tcg_op);
4336 case 0x3: /* FSQRT */
4337 gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
4339 case 0x8: /* FRINTN */
4340 case 0x9: /* FRINTP */
4341 case 0xa: /* FRINTM */
4342 case 0xb: /* FRINTZ */
4343 case 0xc: /* FRINTA */
4345 TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
4347 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
4348 gen_helper_rints(tcg_res, tcg_op, fpst);
4350 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
4351 tcg_temp_free_i32(tcg_rmode);
4354 case 0xe: /* FRINTX */
4355 gen_helper_rints_exact(tcg_res, tcg_op, fpst);
4357 case 0xf: /* FRINTI */
4358 gen_helper_rints(tcg_res, tcg_op, fpst);
4364 write_fp_sreg(s, rd, tcg_res);
4366 tcg_temp_free_ptr(fpst);
4367 tcg_temp_free_i32(tcg_op);
4368 tcg_temp_free_i32(tcg_res);
4371 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4372 static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
4378 fpst = get_fpstatus_ptr();
4379 tcg_op = read_fp_dreg(s, rn);
4380 tcg_res = tcg_temp_new_i64();
4383 case 0x0: /* FMOV */
4384 tcg_gen_mov_i64(tcg_res, tcg_op);
4386 case 0x1: /* FABS */
4387 gen_helper_vfp_absd(tcg_res, tcg_op);
4389 case 0x2: /* FNEG */
4390 gen_helper_vfp_negd(tcg_res, tcg_op);
4392 case 0x3: /* FSQRT */
4393 gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env);
4395 case 0x8: /* FRINTN */
4396 case 0x9: /* FRINTP */
4397 case 0xa: /* FRINTM */
4398 case 0xb: /* FRINTZ */
4399 case 0xc: /* FRINTA */
4401 TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
4403 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
4404 gen_helper_rintd(tcg_res, tcg_op, fpst);
4406 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
4407 tcg_temp_free_i32(tcg_rmode);
4410 case 0xe: /* FRINTX */
4411 gen_helper_rintd_exact(tcg_res, tcg_op, fpst);
4413 case 0xf: /* FRINTI */
4414 gen_helper_rintd(tcg_res, tcg_op, fpst);
4420 write_fp_dreg(s, rd, tcg_res);
4422 tcg_temp_free_ptr(fpst);
4423 tcg_temp_free_i64(tcg_op);
4424 tcg_temp_free_i64(tcg_res);
4427 static void handle_fp_fcvt(DisasContext *s, int opcode,
4428 int rd, int rn, int dtype, int ntype)
4433 TCGv_i32 tcg_rn = read_fp_sreg(s, rn);
4435 /* Single to double */
4436 TCGv_i64 tcg_rd = tcg_temp_new_i64();
4437 gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env);
4438 write_fp_dreg(s, rd, tcg_rd);
4439 tcg_temp_free_i64(tcg_rd);
4441 /* Single to half */
4442 TCGv_i32 tcg_rd = tcg_temp_new_i32();
4443 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, cpu_env);
4444 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4445 write_fp_sreg(s, rd, tcg_rd);
4446 tcg_temp_free_i32(tcg_rd);
4448 tcg_temp_free_i32(tcg_rn);
4453 TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
4454 TCGv_i32 tcg_rd = tcg_temp_new_i32();
4456 /* Double to single */
4457 gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env);
4459 /* Double to half */
4460 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, cpu_env);
4461 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4463 write_fp_sreg(s, rd, tcg_rd);
4464 tcg_temp_free_i32(tcg_rd);
4465 tcg_temp_free_i64(tcg_rn);
4470 TCGv_i32 tcg_rn = read_fp_sreg(s, rn);
4471 tcg_gen_ext16u_i32(tcg_rn, tcg_rn);
4473 /* Half to single */
4474 TCGv_i32 tcg_rd = tcg_temp_new_i32();
4475 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, cpu_env);
4476 write_fp_sreg(s, rd, tcg_rd);
4477 tcg_temp_free_i32(tcg_rd);
4479 /* Half to double */
4480 TCGv_i64 tcg_rd = tcg_temp_new_i64();
4481 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, cpu_env);
4482 write_fp_dreg(s, rd, tcg_rd);
4483 tcg_temp_free_i64(tcg_rd);
4485 tcg_temp_free_i32(tcg_rn);
4493 /* C3.6.25 Floating point data-processing (1 source)
4494 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4495 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4496 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4497 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4499 static void disas_fp_1src(DisasContext *s, uint32_t insn)
4501 int type = extract32(insn, 22, 2);
4502 int opcode = extract32(insn, 15, 6);
4503 int rn = extract32(insn, 5, 5);
4504 int rd = extract32(insn, 0, 5);
4507 case 0x4: case 0x5: case 0x7:
4509 /* FCVT between half, single and double precision */
4510 int dtype = extract32(opcode, 0, 2);
4511 if (type == 2 || dtype == type) {
4512 unallocated_encoding(s);
4515 if (!fp_access_check(s)) {
4519 handle_fp_fcvt(s, opcode, rd, rn, dtype, type);
4525 /* 32-to-32 and 64-to-64 ops */
4528 if (!fp_access_check(s)) {
4532 handle_fp_1src_single(s, opcode, rd, rn);
4535 if (!fp_access_check(s)) {
4539 handle_fp_1src_double(s, opcode, rd, rn);
4542 unallocated_encoding(s);
4546 unallocated_encoding(s);
4551 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4552 static void handle_fp_2src_single(DisasContext *s, int opcode,
4553 int rd, int rn, int rm)
4560 tcg_res = tcg_temp_new_i32();
4561 fpst = get_fpstatus_ptr();
4562 tcg_op1 = read_fp_sreg(s, rn);
4563 tcg_op2 = read_fp_sreg(s, rm);
4566 case 0x0: /* FMUL */
4567 gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
4569 case 0x1: /* FDIV */
4570 gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst);
4572 case 0x2: /* FADD */
4573 gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
4575 case 0x3: /* FSUB */
4576 gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
4578 case 0x4: /* FMAX */
4579 gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
4581 case 0x5: /* FMIN */
4582 gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
4584 case 0x6: /* FMAXNM */
4585 gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
4587 case 0x7: /* FMINNM */
4588 gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
4590 case 0x8: /* FNMUL */
4591 gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
4592 gen_helper_vfp_negs(tcg_res, tcg_res);
4596 write_fp_sreg(s, rd, tcg_res);
4598 tcg_temp_free_ptr(fpst);
4599 tcg_temp_free_i32(tcg_op1);
4600 tcg_temp_free_i32(tcg_op2);
4601 tcg_temp_free_i32(tcg_res);
4604 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4605 static void handle_fp_2src_double(DisasContext *s, int opcode,
4606 int rd, int rn, int rm)
4613 tcg_res = tcg_temp_new_i64();
4614 fpst = get_fpstatus_ptr();
4615 tcg_op1 = read_fp_dreg(s, rn);
4616 tcg_op2 = read_fp_dreg(s, rm);
4619 case 0x0: /* FMUL */
4620 gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
4622 case 0x1: /* FDIV */
4623 gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
4625 case 0x2: /* FADD */
4626 gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
4628 case 0x3: /* FSUB */
4629 gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
4631 case 0x4: /* FMAX */
4632 gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
4634 case 0x5: /* FMIN */
4635 gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
4637 case 0x6: /* FMAXNM */
4638 gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
4640 case 0x7: /* FMINNM */
4641 gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
4643 case 0x8: /* FNMUL */
4644 gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
4645 gen_helper_vfp_negd(tcg_res, tcg_res);
4649 write_fp_dreg(s, rd, tcg_res);
4651 tcg_temp_free_ptr(fpst);
4652 tcg_temp_free_i64(tcg_op1);
4653 tcg_temp_free_i64(tcg_op2);
4654 tcg_temp_free_i64(tcg_res);
4657 /* C3.6.26 Floating point data-processing (2 source)
4658 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4659 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4660 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4661 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4663 static void disas_fp_2src(DisasContext *s, uint32_t insn)
4665 int type = extract32(insn, 22, 2);
4666 int rd = extract32(insn, 0, 5);
4667 int rn = extract32(insn, 5, 5);
4668 int rm = extract32(insn, 16, 5);
4669 int opcode = extract32(insn, 12, 4);
4672 unallocated_encoding(s);
4678 if (!fp_access_check(s)) {
4681 handle_fp_2src_single(s, opcode, rd, rn, rm);
4684 if (!fp_access_check(s)) {
4687 handle_fp_2src_double(s, opcode, rd, rn, rm);
4690 unallocated_encoding(s);
4694 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4695 static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
4696 int rd, int rn, int rm, int ra)
4698 TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
4699 TCGv_i32 tcg_res = tcg_temp_new_i32();
4700 TCGv_ptr fpst = get_fpstatus_ptr();
4702 tcg_op1 = read_fp_sreg(s, rn);
4703 tcg_op2 = read_fp_sreg(s, rm);
4704 tcg_op3 = read_fp_sreg(s, ra);
4706 /* These are fused multiply-add, and must be done as one
4707 * floating point operation with no rounding between the
4708 * multiplication and addition steps.
4709 * NB that doing the negations here as separate steps is
4710 * correct : an input NaN should come out with its sign bit
4711 * flipped if it is a negated-input.
4714 gen_helper_vfp_negs(tcg_op3, tcg_op3);
4718 gen_helper_vfp_negs(tcg_op1, tcg_op1);
4721 gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
4723 write_fp_sreg(s, rd, tcg_res);
4725 tcg_temp_free_ptr(fpst);
4726 tcg_temp_free_i32(tcg_op1);
4727 tcg_temp_free_i32(tcg_op2);
4728 tcg_temp_free_i32(tcg_op3);
4729 tcg_temp_free_i32(tcg_res);
4732 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4733 static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
4734 int rd, int rn, int rm, int ra)
4736 TCGv_i64 tcg_op1, tcg_op2, tcg_op3;
4737 TCGv_i64 tcg_res = tcg_temp_new_i64();
4738 TCGv_ptr fpst = get_fpstatus_ptr();
4740 tcg_op1 = read_fp_dreg(s, rn);
4741 tcg_op2 = read_fp_dreg(s, rm);
4742 tcg_op3 = read_fp_dreg(s, ra);
4744 /* These are fused multiply-add, and must be done as one
4745 * floating point operation with no rounding between the
4746 * multiplication and addition steps.
4747 * NB that doing the negations here as separate steps is
4748 * correct : an input NaN should come out with its sign bit
4749 * flipped if it is a negated-input.
4752 gen_helper_vfp_negd(tcg_op3, tcg_op3);
4756 gen_helper_vfp_negd(tcg_op1, tcg_op1);
4759 gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
4761 write_fp_dreg(s, rd, tcg_res);
4763 tcg_temp_free_ptr(fpst);
4764 tcg_temp_free_i64(tcg_op1);
4765 tcg_temp_free_i64(tcg_op2);
4766 tcg_temp_free_i64(tcg_op3);
4767 tcg_temp_free_i64(tcg_res);
4770 /* C3.6.27 Floating point data-processing (3 source)
4771 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4772 * +---+---+---+-----------+------+----+------+----+------+------+------+
4773 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4774 * +---+---+---+-----------+------+----+------+----+------+------+------+
4776 static void disas_fp_3src(DisasContext *s, uint32_t insn)
4778 int type = extract32(insn, 22, 2);
4779 int rd = extract32(insn, 0, 5);
4780 int rn = extract32(insn, 5, 5);
4781 int ra = extract32(insn, 10, 5);
4782 int rm = extract32(insn, 16, 5);
4783 bool o0 = extract32(insn, 15, 1);
4784 bool o1 = extract32(insn, 21, 1);
4788 if (!fp_access_check(s)) {
4791 handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra);
4794 if (!fp_access_check(s)) {
4797 handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
4800 unallocated_encoding(s);
4804 /* C3.6.28 Floating point immediate
4805 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4806 * +---+---+---+-----------+------+---+------------+-------+------+------+
4807 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4808 * +---+---+---+-----------+------+---+------------+-------+------+------+
4810 static void disas_fp_imm(DisasContext *s, uint32_t insn)
4812 int rd = extract32(insn, 0, 5);
4813 int imm8 = extract32(insn, 13, 8);
4814 int is_double = extract32(insn, 22, 2);
4818 if (is_double > 1) {
4819 unallocated_encoding(s);
4823 if (!fp_access_check(s)) {
4827 /* The imm8 encodes the sign bit, enough bits to represent
4828 * an exponent in the range 01....1xx to 10....0xx,
4829 * and the most significant 4 bits of the mantissa; see
4830 * VFPExpandImm() in the v8 ARM ARM.
4833 imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
4834 (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
4835 extract32(imm8, 0, 6);
4838 imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
4839 (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
4840 (extract32(imm8, 0, 6) << 3);
4844 tcg_res = tcg_const_i64(imm);
4845 write_fp_dreg(s, rd, tcg_res);
4846 tcg_temp_free_i64(tcg_res);
4849 /* Handle floating point <=> fixed point conversions. Note that we can
4850 * also deal with fp <=> integer conversions as a special case (scale == 64)
4851 * OPTME: consider handling that special case specially or at least skipping
4852 * the call to scalbn in the helpers for zero shifts.
4854 static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
4855 bool itof, int rmode, int scale, int sf, int type)
4857 bool is_signed = !(opcode & 1);
4858 bool is_double = type;
4859 TCGv_ptr tcg_fpstatus;
4862 tcg_fpstatus = get_fpstatus_ptr();
4864 tcg_shift = tcg_const_i32(64 - scale);
4867 TCGv_i64 tcg_int = cpu_reg(s, rn);
4869 TCGv_i64 tcg_extend = new_tmp_a64(s);
4872 tcg_gen_ext32s_i64(tcg_extend, tcg_int);
4874 tcg_gen_ext32u_i64(tcg_extend, tcg_int);
4877 tcg_int = tcg_extend;
4881 TCGv_i64 tcg_double = tcg_temp_new_i64();
4883 gen_helper_vfp_sqtod(tcg_double, tcg_int,
4884 tcg_shift, tcg_fpstatus);
4886 gen_helper_vfp_uqtod(tcg_double, tcg_int,
4887 tcg_shift, tcg_fpstatus);
4889 write_fp_dreg(s, rd, tcg_double);
4890 tcg_temp_free_i64(tcg_double);
4892 TCGv_i32 tcg_single = tcg_temp_new_i32();
4894 gen_helper_vfp_sqtos(tcg_single, tcg_int,
4895 tcg_shift, tcg_fpstatus);
4897 gen_helper_vfp_uqtos(tcg_single, tcg_int,
4898 tcg_shift, tcg_fpstatus);
4900 write_fp_sreg(s, rd, tcg_single);
4901 tcg_temp_free_i32(tcg_single);
4904 TCGv_i64 tcg_int = cpu_reg(s, rd);
4907 if (extract32(opcode, 2, 1)) {
4908 /* There are too many rounding modes to all fit into rmode,
4909 * so FCVTA[US] is a special case.
4911 rmode = FPROUNDING_TIEAWAY;
4914 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
4916 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
4919 TCGv_i64 tcg_double = read_fp_dreg(s, rn);
4922 gen_helper_vfp_tosld(tcg_int, tcg_double,
4923 tcg_shift, tcg_fpstatus);
4925 gen_helper_vfp_tosqd(tcg_int, tcg_double,
4926 tcg_shift, tcg_fpstatus);
4930 gen_helper_vfp_tould(tcg_int, tcg_double,
4931 tcg_shift, tcg_fpstatus);
4933 gen_helper_vfp_touqd(tcg_int, tcg_double,
4934 tcg_shift, tcg_fpstatus);
4937 tcg_temp_free_i64(tcg_double);
4939 TCGv_i32 tcg_single = read_fp_sreg(s, rn);
4942 gen_helper_vfp_tosqs(tcg_int, tcg_single,
4943 tcg_shift, tcg_fpstatus);
4945 gen_helper_vfp_touqs(tcg_int, tcg_single,
4946 tcg_shift, tcg_fpstatus);
4949 TCGv_i32 tcg_dest = tcg_temp_new_i32();
4951 gen_helper_vfp_tosls(tcg_dest, tcg_single,
4952 tcg_shift, tcg_fpstatus);
4954 gen_helper_vfp_touls(tcg_dest, tcg_single,
4955 tcg_shift, tcg_fpstatus);
4957 tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
4958 tcg_temp_free_i32(tcg_dest);
4960 tcg_temp_free_i32(tcg_single);
4963 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
4964 tcg_temp_free_i32(tcg_rmode);
4967 tcg_gen_ext32u_i64(tcg_int, tcg_int);
4971 tcg_temp_free_ptr(tcg_fpstatus);
4972 tcg_temp_free_i32(tcg_shift);
4975 /* C3.6.29 Floating point <-> fixed point conversions
4976 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4977 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4978 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4979 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4981 static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
4983 int rd = extract32(insn, 0, 5);
4984 int rn = extract32(insn, 5, 5);
4985 int scale = extract32(insn, 10, 6);
4986 int opcode = extract32(insn, 16, 3);
4987 int rmode = extract32(insn, 19, 2);
4988 int type = extract32(insn, 22, 2);
4989 bool sbit = extract32(insn, 29, 1);
4990 bool sf = extract32(insn, 31, 1);
4993 if (sbit || (type > 1)
4994 || (!sf && scale < 32)) {
4995 unallocated_encoding(s);
4999 switch ((rmode << 3) | opcode) {
5000 case 0x2: /* SCVTF */
5001 case 0x3: /* UCVTF */
5004 case 0x18: /* FCVTZS */
5005 case 0x19: /* FCVTZU */
5009 unallocated_encoding(s);
5013 if (!fp_access_check(s)) {
5017 handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type);
5020 static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
5022 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5023 * without conversion.
5027 TCGv_i64 tcg_rn = cpu_reg(s, rn);
5033 TCGv_i64 tmp = tcg_temp_new_i64();
5034 tcg_gen_ext32u_i64(tmp, tcg_rn);
5035 tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64));
5036 tcg_gen_movi_i64(tmp, 0);
5037 tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
5038 tcg_temp_free_i64(tmp);
5044 TCGv_i64 tmp = tcg_const_i64(0);
5045 tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64));
5046 tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
5047 tcg_temp_free_i64(tmp);
5051 /* 64 bit to top half. */
5052 tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
5056 TCGv_i64 tcg_rd = cpu_reg(s, rd);
5061 tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32));
5065 tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64));
5068 /* 64 bits from top half */
5069 tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
5075 /* C3.6.30 Floating point <-> integer conversions
5076 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5077 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5078 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5079 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5081 static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
5083 int rd = extract32(insn, 0, 5);
5084 int rn = extract32(insn, 5, 5);
5085 int opcode = extract32(insn, 16, 3);
5086 int rmode = extract32(insn, 19, 2);
5087 int type = extract32(insn, 22, 2);
5088 bool sbit = extract32(insn, 29, 1);
5089 bool sf = extract32(insn, 31, 1);
5092 unallocated_encoding(s);
5098 bool itof = opcode & 1;
5101 unallocated_encoding(s);
5105 switch (sf << 3 | type << 1 | rmode) {
5106 case 0x0: /* 32 bit */
5107 case 0xa: /* 64 bit */
5108 case 0xd: /* 64 bit to top half of quad */
5111 /* all other sf/type/rmode combinations are invalid */
5112 unallocated_encoding(s);
5116 if (!fp_access_check(s)) {
5119 handle_fmov(s, rd, rn, type, itof);
5121 /* actual FP conversions */
5122 bool itof = extract32(opcode, 1, 1);
5124 if (type > 1 || (rmode != 0 && opcode > 1)) {
5125 unallocated_encoding(s);
5129 if (!fp_access_check(s)) {
5132 handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
5136 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5137 * 31 30 29 28 25 24 0
5138 * +---+---+---+---------+-----------------------------+
5139 * | | 0 | | 1 1 1 1 | |
5140 * +---+---+---+---------+-----------------------------+
5142 static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
5144 if (extract32(insn, 24, 1)) {
5145 /* Floating point data-processing (3 source) */
5146 disas_fp_3src(s, insn);
5147 } else if (extract32(insn, 21, 1) == 0) {
5148 /* Floating point to fixed point conversions */
5149 disas_fp_fixed_conv(s, insn);
5151 switch (extract32(insn, 10, 2)) {
5153 /* Floating point conditional compare */
5154 disas_fp_ccomp(s, insn);
5157 /* Floating point data-processing (2 source) */
5158 disas_fp_2src(s, insn);
5161 /* Floating point conditional select */
5162 disas_fp_csel(s, insn);
5165 switch (ctz32(extract32(insn, 12, 4))) {
5166 case 0: /* [15:12] == xxx1 */
5167 /* Floating point immediate */
5168 disas_fp_imm(s, insn);
5170 case 1: /* [15:12] == xx10 */
5171 /* Floating point compare */
5172 disas_fp_compare(s, insn);
5174 case 2: /* [15:12] == x100 */
5175 /* Floating point data-processing (1 source) */
5176 disas_fp_1src(s, insn);
5178 case 3: /* [15:12] == 1000 */
5179 unallocated_encoding(s);
5181 default: /* [15:12] == 0000 */
5182 /* Floating point <-> integer conversions */
5183 disas_fp_int_conv(s, insn);
5191 static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right,
5194 /* Extract 64 bits from the middle of two concatenated 64 bit
5195 * vector register slices left:right. The extracted bits start
5196 * at 'pos' bits into the right (least significant) side.
5197 * We return the result in tcg_right, and guarantee not to
5200 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
5201 assert(pos > 0 && pos < 64);
5203 tcg_gen_shri_i64(tcg_right, tcg_right, pos);
5204 tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos);
5205 tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp);
5207 tcg_temp_free_i64(tcg_tmp);
5211 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5212 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5213 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5214 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5216 static void disas_simd_ext(DisasContext *s, uint32_t insn)
5218 int is_q = extract32(insn, 30, 1);
5219 int op2 = extract32(insn, 22, 2);
5220 int imm4 = extract32(insn, 11, 4);
5221 int rm = extract32(insn, 16, 5);
5222 int rn = extract32(insn, 5, 5);
5223 int rd = extract32(insn, 0, 5);
5224 int pos = imm4 << 3;
5225 TCGv_i64 tcg_resl, tcg_resh;
5227 if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) {
5228 unallocated_encoding(s);
5232 if (!fp_access_check(s)) {
5236 tcg_resh = tcg_temp_new_i64();
5237 tcg_resl = tcg_temp_new_i64();
5239 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5240 * either extracting 128 bits from a 128:128 concatenation, or
5241 * extracting 64 bits from a 64:64 concatenation.
5244 read_vec_element(s, tcg_resl, rn, 0, MO_64);
5246 read_vec_element(s, tcg_resh, rm, 0, MO_64);
5247 do_ext64(s, tcg_resh, tcg_resl, pos);
5249 tcg_gen_movi_i64(tcg_resh, 0);
5256 EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} };
5257 EltPosns *elt = eltposns;
5264 read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64);
5266 read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64);
5269 do_ext64(s, tcg_resh, tcg_resl, pos);
5270 tcg_hh = tcg_temp_new_i64();
5271 read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64);
5272 do_ext64(s, tcg_hh, tcg_resh, pos);
5273 tcg_temp_free_i64(tcg_hh);
5277 write_vec_element(s, tcg_resl, rd, 0, MO_64);
5278 tcg_temp_free_i64(tcg_resl);
5279 write_vec_element(s, tcg_resh, rd, 1, MO_64);
5280 tcg_temp_free_i64(tcg_resh);
5284 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5285 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5286 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5287 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5289 static void disas_simd_tb(DisasContext *s, uint32_t insn)
5291 int op2 = extract32(insn, 22, 2);
5292 int is_q = extract32(insn, 30, 1);
5293 int rm = extract32(insn, 16, 5);
5294 int rn = extract32(insn, 5, 5);
5295 int rd = extract32(insn, 0, 5);
5296 int is_tblx = extract32(insn, 12, 1);
5297 int len = extract32(insn, 13, 2);
5298 TCGv_i64 tcg_resl, tcg_resh, tcg_idx;
5299 TCGv_i32 tcg_regno, tcg_numregs;
5302 unallocated_encoding(s);
5306 if (!fp_access_check(s)) {
5310 /* This does a table lookup: for every byte element in the input
5311 * we index into a table formed from up to four vector registers,
5312 * and then the output is the result of the lookups. Our helper
5313 * function does the lookup operation for a single 64 bit part of
5316 tcg_resl = tcg_temp_new_i64();
5317 tcg_resh = tcg_temp_new_i64();
5320 read_vec_element(s, tcg_resl, rd, 0, MO_64);
5322 tcg_gen_movi_i64(tcg_resl, 0);
5324 if (is_tblx && is_q) {
5325 read_vec_element(s, tcg_resh, rd, 1, MO_64);
5327 tcg_gen_movi_i64(tcg_resh, 0);
5330 tcg_idx = tcg_temp_new_i64();
5331 tcg_regno = tcg_const_i32(rn);
5332 tcg_numregs = tcg_const_i32(len + 1);
5333 read_vec_element(s, tcg_idx, rm, 0, MO_64);
5334 gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx,
5335 tcg_regno, tcg_numregs);
5337 read_vec_element(s, tcg_idx, rm, 1, MO_64);
5338 gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx,
5339 tcg_regno, tcg_numregs);
5341 tcg_temp_free_i64(tcg_idx);
5342 tcg_temp_free_i32(tcg_regno);
5343 tcg_temp_free_i32(tcg_numregs);
5345 write_vec_element(s, tcg_resl, rd, 0, MO_64);
5346 tcg_temp_free_i64(tcg_resl);
5347 write_vec_element(s, tcg_resh, rd, 1, MO_64);
5348 tcg_temp_free_i64(tcg_resh);
5351 /* C3.6.3 ZIP/UZP/TRN
5352 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5353 * +---+---+-------------+------+---+------+---+------------------+------+
5354 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5355 * +---+---+-------------+------+---+------+---+------------------+------+
5357 static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
5359 int rd = extract32(insn, 0, 5);
5360 int rn = extract32(insn, 5, 5);
5361 int rm = extract32(insn, 16, 5);
5362 int size = extract32(insn, 22, 2);
5363 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5364 * bit 2 indicates 1 vs 2 variant of the insn.
5366 int opcode = extract32(insn, 12, 2);
5367 bool part = extract32(insn, 14, 1);
5368 bool is_q = extract32(insn, 30, 1);
5369 int esize = 8 << size;
5371 int datasize = is_q ? 128 : 64;
5372 int elements = datasize / esize;
5373 TCGv_i64 tcg_res, tcg_resl, tcg_resh;
5375 if (opcode == 0 || (size == 3 && !is_q)) {
5376 unallocated_encoding(s);
5380 if (!fp_access_check(s)) {
5384 tcg_resl = tcg_const_i64(0);
5385 tcg_resh = tcg_const_i64(0);
5386 tcg_res = tcg_temp_new_i64();
5388 for (i = 0; i < elements; i++) {
5390 case 1: /* UZP1/2 */
5392 int midpoint = elements / 2;
5394 read_vec_element(s, tcg_res, rn, 2 * i + part, size);
5396 read_vec_element(s, tcg_res, rm,
5397 2 * (i - midpoint) + part, size);
5401 case 2: /* TRN1/2 */
5403 read_vec_element(s, tcg_res, rm, (i & ~1) + part, size);
5405 read_vec_element(s, tcg_res, rn, (i & ~1) + part, size);
5408 case 3: /* ZIP1/2 */
5410 int base = part * elements / 2;
5412 read_vec_element(s, tcg_res, rm, base + (i >> 1), size);
5414 read_vec_element(s, tcg_res, rn, base + (i >> 1), size);
5419 g_assert_not_reached();
5424 tcg_gen_shli_i64(tcg_res, tcg_res, ofs);
5425 tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res);
5427 tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64);
5428 tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res);
5432 tcg_temp_free_i64(tcg_res);
5434 write_vec_element(s, tcg_resl, rd, 0, MO_64);
5435 tcg_temp_free_i64(tcg_resl);
5436 write_vec_element(s, tcg_resh, rd, 1, MO_64);
5437 tcg_temp_free_i64(tcg_resh);
5440 static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
5441 int opc, bool is_min, TCGv_ptr fpst)
5443 /* Helper function for disas_simd_across_lanes: do a single precision
5444 * min/max operation on the specified two inputs,
5445 * and return the result in tcg_elt1.
5449 gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
5451 gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
5456 gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
5458 gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
5463 /* C3.6.4 AdvSIMD across lanes
5464 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5465 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5466 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5467 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5469 static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
5471 int rd = extract32(insn, 0, 5);
5472 int rn = extract32(insn, 5, 5);
5473 int size = extract32(insn, 22, 2);
5474 int opcode = extract32(insn, 12, 5);
5475 bool is_q = extract32(insn, 30, 1);
5476 bool is_u = extract32(insn, 29, 1);
5478 bool is_min = false;
5482 TCGv_i64 tcg_res, tcg_elt;
5485 case 0x1b: /* ADDV */
5487 unallocated_encoding(s);
5491 case 0x3: /* SADDLV, UADDLV */
5492 case 0xa: /* SMAXV, UMAXV */
5493 case 0x1a: /* SMINV, UMINV */
5494 if (size == 3 || (size == 2 && !is_q)) {
5495 unallocated_encoding(s);
5499 case 0xc: /* FMAXNMV, FMINNMV */
5500 case 0xf: /* FMAXV, FMINV */
5501 if (!is_u || !is_q || extract32(size, 0, 1)) {
5502 unallocated_encoding(s);
5505 /* Bit 1 of size field encodes min vs max, and actual size is always
5506 * 32 bits: adjust the size variable so following code can rely on it
5508 is_min = extract32(size, 1, 1);
5513 unallocated_encoding(s);
5517 if (!fp_access_check(s)) {
5522 elements = (is_q ? 128 : 64) / esize;
5524 tcg_res = tcg_temp_new_i64();
5525 tcg_elt = tcg_temp_new_i64();
5527 /* These instructions operate across all lanes of a vector
5528 * to produce a single result. We can guarantee that a 64
5529 * bit intermediate is sufficient:
5530 * + for [US]ADDLV the maximum element size is 32 bits, and
5531 * the result type is 64 bits
5532 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5533 * same as the element size, which is 32 bits at most
5534 * For the integer operations we can choose to work at 64
5535 * or 32 bits and truncate at the end; for simplicity
5536 * we use 64 bits always. The floating point
5537 * ops do require 32 bit intermediates, though.
5540 read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN));
5542 for (i = 1; i < elements; i++) {
5543 read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN));
5546 case 0x03: /* SADDLV / UADDLV */
5547 case 0x1b: /* ADDV */
5548 tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt);
5550 case 0x0a: /* SMAXV / UMAXV */
5551 tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE,
5553 tcg_res, tcg_elt, tcg_res, tcg_elt);
5555 case 0x1a: /* SMINV / UMINV */
5556 tcg_gen_movcond_i64(is_u ? TCG_COND_LEU : TCG_COND_LE,
5558 tcg_res, tcg_elt, tcg_res, tcg_elt);
5562 g_assert_not_reached();
5567 /* Floating point ops which work on 32 bit (single) intermediates.
5568 * Note that correct NaN propagation requires that we do these
5569 * operations in exactly the order specified by the pseudocode.
5571 TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
5572 TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
5573 TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
5574 TCGv_ptr fpst = get_fpstatus_ptr();
5576 assert(esize == 32);
5577 assert(elements == 4);
5579 read_vec_element(s, tcg_elt, rn, 0, MO_32);
5580 tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt);
5581 read_vec_element(s, tcg_elt, rn, 1, MO_32);
5582 tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
5584 do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
5586 read_vec_element(s, tcg_elt, rn, 2, MO_32);
5587 tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
5588 read_vec_element(s, tcg_elt, rn, 3, MO_32);
5589 tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt);
5591 do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst);
5593 do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
5595 tcg_gen_extu_i32_i64(tcg_res, tcg_elt1);
5596 tcg_temp_free_i32(tcg_elt1);
5597 tcg_temp_free_i32(tcg_elt2);
5598 tcg_temp_free_i32(tcg_elt3);
5599 tcg_temp_free_ptr(fpst);
5602 tcg_temp_free_i64(tcg_elt);
5604 /* Now truncate the result to the width required for the final output */
5605 if (opcode == 0x03) {
5606 /* SADDLV, UADDLV: result is 2*esize */
5612 tcg_gen_ext8u_i64(tcg_res, tcg_res);
5615 tcg_gen_ext16u_i64(tcg_res, tcg_res);
5618 tcg_gen_ext32u_i64(tcg_res, tcg_res);
5623 g_assert_not_reached();
5626 write_fp_dreg(s, rd, tcg_res);
5627 tcg_temp_free_i64(tcg_res);
5630 /* C6.3.31 DUP (Element, Vector)
5632 * 31 30 29 21 20 16 15 10 9 5 4 0
5633 * +---+---+-------------------+--------+-------------+------+------+
5634 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5635 * +---+---+-------------------+--------+-------------+------+------+
5637 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5639 static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
5642 int size = ctz32(imm5);
5643 int esize = 8 << size;
5644 int elements = (is_q ? 128 : 64) / esize;
5648 if (size > 3 || (size == 3 && !is_q)) {
5649 unallocated_encoding(s);
5653 if (!fp_access_check(s)) {
5657 index = imm5 >> (size + 1);
5659 tmp = tcg_temp_new_i64();
5660 read_vec_element(s, tmp, rn, index, size);
5662 for (i = 0; i < elements; i++) {
5663 write_vec_element(s, tmp, rd, i, size);
5667 clear_vec_high(s, rd);
5670 tcg_temp_free_i64(tmp);
5673 /* C6.3.31 DUP (element, scalar)
5674 * 31 21 20 16 15 10 9 5 4 0
5675 * +-----------------------+--------+-------------+------+------+
5676 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5677 * +-----------------------+--------+-------------+------+------+
5679 static void handle_simd_dupes(DisasContext *s, int rd, int rn,
5682 int size = ctz32(imm5);
5687 unallocated_encoding(s);
5691 if (!fp_access_check(s)) {
5695 index = imm5 >> (size + 1);
5697 /* This instruction just extracts the specified element and
5698 * zero-extends it into the bottom of the destination register.
5700 tmp = tcg_temp_new_i64();
5701 read_vec_element(s, tmp, rn, index, size);
5702 write_fp_dreg(s, rd, tmp);
5703 tcg_temp_free_i64(tmp);
5706 /* C6.3.32 DUP (General)
5708 * 31 30 29 21 20 16 15 10 9 5 4 0
5709 * +---+---+-------------------+--------+-------------+------+------+
5710 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5711 * +---+---+-------------------+--------+-------------+------+------+
5713 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5715 static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
5718 int size = ctz32(imm5);
5719 int esize = 8 << size;
5720 int elements = (is_q ? 128 : 64)/esize;
5723 if (size > 3 || ((size == 3) && !is_q)) {
5724 unallocated_encoding(s);
5728 if (!fp_access_check(s)) {
5732 for (i = 0; i < elements; i++) {
5733 write_vec_element(s, cpu_reg(s, rn), rd, i, size);
5736 clear_vec_high(s, rd);
5740 /* C6.3.150 INS (Element)
5742 * 31 21 20 16 15 14 11 10 9 5 4 0
5743 * +-----------------------+--------+------------+---+------+------+
5744 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5745 * +-----------------------+--------+------------+---+------+------+
5747 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5748 * index: encoded in imm5<4:size+1>
5750 static void handle_simd_inse(DisasContext *s, int rd, int rn,
5753 int size = ctz32(imm5);
5754 int src_index, dst_index;
5758 unallocated_encoding(s);
5762 if (!fp_access_check(s)) {
5766 dst_index = extract32(imm5, 1+size, 5);
5767 src_index = extract32(imm4, size, 4);
5769 tmp = tcg_temp_new_i64();
5771 read_vec_element(s, tmp, rn, src_index, size);
5772 write_vec_element(s, tmp, rd, dst_index, size);
5774 tcg_temp_free_i64(tmp);
5778 /* C6.3.151 INS (General)
5780 * 31 21 20 16 15 10 9 5 4 0
5781 * +-----------------------+--------+-------------+------+------+
5782 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5783 * +-----------------------+--------+-------------+------+------+
5785 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5786 * index: encoded in imm5<4:size+1>
5788 static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
5790 int size = ctz32(imm5);
5794 unallocated_encoding(s);
5798 if (!fp_access_check(s)) {
5802 idx = extract32(imm5, 1 + size, 4 - size);
5803 write_vec_element(s, cpu_reg(s, rn), rd, idx, size);
5807 * C6.3.321 UMOV (General)
5808 * C6.3.237 SMOV (General)
5810 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5811 * +---+---+-------------------+--------+-------------+------+------+
5812 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5813 * +---+---+-------------------+--------+-------------+------+------+
5815 * U: unsigned when set
5816 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5818 static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed,
5819 int rn, int rd, int imm5)
5821 int size = ctz32(imm5);
5825 /* Check for UnallocatedEncodings */
5827 if (size > 2 || (size == 2 && !is_q)) {
5828 unallocated_encoding(s);
5833 || (size < 3 && is_q)
5834 || (size == 3 && !is_q)) {
5835 unallocated_encoding(s);
5840 if (!fp_access_check(s)) {
5844 element = extract32(imm5, 1+size, 4);
5846 tcg_rd = cpu_reg(s, rd);
5847 read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0));
5848 if (is_signed && !is_q) {
5849 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
5853 /* C3.6.5 AdvSIMD copy
5854 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5855 * +---+---+----+-----------------+------+---+------+---+------+------+
5856 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5857 * +---+---+----+-----------------+------+---+------+---+------+------+
5859 static void disas_simd_copy(DisasContext *s, uint32_t insn)
5861 int rd = extract32(insn, 0, 5);
5862 int rn = extract32(insn, 5, 5);
5863 int imm4 = extract32(insn, 11, 4);
5864 int op = extract32(insn, 29, 1);
5865 int is_q = extract32(insn, 30, 1);
5866 int imm5 = extract32(insn, 16, 5);
5871 handle_simd_inse(s, rd, rn, imm4, imm5);
5873 unallocated_encoding(s);
5878 /* DUP (element - vector) */
5879 handle_simd_dupe(s, is_q, rd, rn, imm5);
5883 handle_simd_dupg(s, is_q, rd, rn, imm5);
5888 handle_simd_insg(s, rd, rn, imm5);
5890 unallocated_encoding(s);
5895 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5896 handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5);
5899 unallocated_encoding(s);
5905 /* C3.6.6 AdvSIMD modified immediate
5906 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5907 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5908 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5909 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5911 * There are a number of operations that can be carried out here:
5912 * MOVI - move (shifted) imm into register
5913 * MVNI - move inverted (shifted) imm into register
5914 * ORR - bitwise OR of (shifted) imm with register
5915 * BIC - bitwise clear of (shifted) imm with register
5917 static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
5919 int rd = extract32(insn, 0, 5);
5920 int cmode = extract32(insn, 12, 4);
5921 int cmode_3_1 = extract32(cmode, 1, 3);
5922 int cmode_0 = extract32(cmode, 0, 1);
5923 int o2 = extract32(insn, 11, 1);
5924 uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
5925 bool is_neg = extract32(insn, 29, 1);
5926 bool is_q = extract32(insn, 30, 1);
5928 TCGv_i64 tcg_rd, tcg_imm;
5931 if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
5932 unallocated_encoding(s);
5936 if (!fp_access_check(s)) {
5940 /* See AdvSIMDExpandImm() in ARM ARM */
5941 switch (cmode_3_1) {
5942 case 0: /* Replicate(Zeros(24):imm8, 2) */
5943 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5944 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5945 case 3: /* Replicate(imm8:Zeros(24), 2) */
5947 int shift = cmode_3_1 * 8;
5948 imm = bitfield_replicate(abcdefgh << shift, 32);
5951 case 4: /* Replicate(Zeros(8):imm8, 4) */
5952 case 5: /* Replicate(imm8:Zeros(8), 4) */
5954 int shift = (cmode_3_1 & 0x1) * 8;
5955 imm = bitfield_replicate(abcdefgh << shift, 16);
5960 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5961 imm = (abcdefgh << 16) | 0xffff;
5963 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5964 imm = (abcdefgh << 8) | 0xff;
5966 imm = bitfield_replicate(imm, 32);
5969 if (!cmode_0 && !is_neg) {
5970 imm = bitfield_replicate(abcdefgh, 8);
5971 } else if (!cmode_0 && is_neg) {
5974 for (i = 0; i < 8; i++) {
5975 if ((abcdefgh) & (1 << i)) {
5976 imm |= 0xffULL << (i * 8);
5979 } else if (cmode_0) {
5981 imm = (abcdefgh & 0x3f) << 48;
5982 if (abcdefgh & 0x80) {
5983 imm |= 0x8000000000000000ULL;
5985 if (abcdefgh & 0x40) {
5986 imm |= 0x3fc0000000000000ULL;
5988 imm |= 0x4000000000000000ULL;
5991 imm = (abcdefgh & 0x3f) << 19;
5992 if (abcdefgh & 0x80) {
5995 if (abcdefgh & 0x40) {
6006 if (cmode_3_1 != 7 && is_neg) {
6010 tcg_imm = tcg_const_i64(imm);
6011 tcg_rd = new_tmp_a64(s);
6013 for (i = 0; i < 2; i++) {
6014 int foffs = i ? fp_reg_hi_offset(s, rd) : fp_reg_offset(s, rd, MO_64);
6016 if (i == 1 && !is_q) {
6017 /* non-quad ops clear high half of vector */
6018 tcg_gen_movi_i64(tcg_rd, 0);
6019 } else if ((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9) {
6020 tcg_gen_ld_i64(tcg_rd, cpu_env, foffs);
6023 tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm);
6026 tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm);
6030 tcg_gen_mov_i64(tcg_rd, tcg_imm);
6032 tcg_gen_st_i64(tcg_rd, cpu_env, foffs);
6035 tcg_temp_free_i64(tcg_imm);
6038 /* C3.6.7 AdvSIMD scalar copy
6039 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6040 * +-----+----+-----------------+------+---+------+---+------+------+
6041 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6042 * +-----+----+-----------------+------+---+------+---+------+------+
6044 static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
6046 int rd = extract32(insn, 0, 5);
6047 int rn = extract32(insn, 5, 5);
6048 int imm4 = extract32(insn, 11, 4);
6049 int imm5 = extract32(insn, 16, 5);
6050 int op = extract32(insn, 29, 1);
6052 if (op != 0 || imm4 != 0) {
6053 unallocated_encoding(s);
6057 /* DUP (element, scalar) */
6058 handle_simd_dupes(s, rd, rn, imm5);
6061 /* C3.6.8 AdvSIMD scalar pairwise
6062 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6063 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6064 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6065 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6067 static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
6069 int u = extract32(insn, 29, 1);
6070 int size = extract32(insn, 22, 2);
6071 int opcode = extract32(insn, 12, 5);
6072 int rn = extract32(insn, 5, 5);
6073 int rd = extract32(insn, 0, 5);
6076 /* For some ops (the FP ones), size[1] is part of the encoding.
6077 * For ADDP strictly it is not but size[1] is always 1 for valid
6080 opcode |= (extract32(size, 1, 1) << 5);
6083 case 0x3b: /* ADDP */
6084 if (u || size != 3) {
6085 unallocated_encoding(s);
6088 if (!fp_access_check(s)) {
6092 TCGV_UNUSED_PTR(fpst);
6094 case 0xc: /* FMAXNMP */
6095 case 0xd: /* FADDP */
6096 case 0xf: /* FMAXP */
6097 case 0x2c: /* FMINNMP */
6098 case 0x2f: /* FMINP */
6099 /* FP op, size[0] is 32 or 64 bit */
6101 unallocated_encoding(s);
6104 if (!fp_access_check(s)) {
6108 size = extract32(size, 0, 1) ? 3 : 2;
6109 fpst = get_fpstatus_ptr();
6112 unallocated_encoding(s);
6117 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
6118 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
6119 TCGv_i64 tcg_res = tcg_temp_new_i64();
6121 read_vec_element(s, tcg_op1, rn, 0, MO_64);
6122 read_vec_element(s, tcg_op2, rn, 1, MO_64);
6125 case 0x3b: /* ADDP */
6126 tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2);
6128 case 0xc: /* FMAXNMP */
6129 gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
6131 case 0xd: /* FADDP */
6132 gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
6134 case 0xf: /* FMAXP */
6135 gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
6137 case 0x2c: /* FMINNMP */
6138 gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
6140 case 0x2f: /* FMINP */
6141 gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
6144 g_assert_not_reached();
6147 write_fp_dreg(s, rd, tcg_res);
6149 tcg_temp_free_i64(tcg_op1);
6150 tcg_temp_free_i64(tcg_op2);
6151 tcg_temp_free_i64(tcg_res);
6153 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
6154 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
6155 TCGv_i32 tcg_res = tcg_temp_new_i32();
6157 read_vec_element_i32(s, tcg_op1, rn, 0, MO_32);
6158 read_vec_element_i32(s, tcg_op2, rn, 1, MO_32);
6161 case 0xc: /* FMAXNMP */
6162 gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
6164 case 0xd: /* FADDP */
6165 gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
6167 case 0xf: /* FMAXP */
6168 gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
6170 case 0x2c: /* FMINNMP */
6171 gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
6173 case 0x2f: /* FMINP */
6174 gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
6177 g_assert_not_reached();
6180 write_fp_sreg(s, rd, tcg_res);
6182 tcg_temp_free_i32(tcg_op1);
6183 tcg_temp_free_i32(tcg_op2);
6184 tcg_temp_free_i32(tcg_res);
6187 if (!TCGV_IS_UNUSED_PTR(fpst)) {
6188 tcg_temp_free_ptr(fpst);
6193 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6195 * This code is handles the common shifting code and is used by both
6196 * the vector and scalar code.
6198 static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
6199 TCGv_i64 tcg_rnd, bool accumulate,
6200 bool is_u, int size, int shift)
6202 bool extended_result = false;
6203 bool round = !TCGV_IS_UNUSED_I64(tcg_rnd);
6205 TCGv_i64 tcg_src_hi;
6207 if (round && size == 3) {
6208 extended_result = true;
6209 ext_lshift = 64 - shift;
6210 tcg_src_hi = tcg_temp_new_i64();
6211 } else if (shift == 64) {
6212 if (!accumulate && is_u) {
6213 /* result is zero */
6214 tcg_gen_movi_i64(tcg_res, 0);
6219 /* Deal with the rounding step */
6221 if (extended_result) {
6222 TCGv_i64 tcg_zero = tcg_const_i64(0);
6224 /* take care of sign extending tcg_res */
6225 tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63);
6226 tcg_gen_add2_i64(tcg_src, tcg_src_hi,
6227 tcg_src, tcg_src_hi,
6230 tcg_gen_add2_i64(tcg_src, tcg_src_hi,
6234 tcg_temp_free_i64(tcg_zero);
6236 tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd);
6240 /* Now do the shift right */
6241 if (round && extended_result) {
6242 /* extended case, >64 bit precision required */
6243 if (ext_lshift == 0) {
6244 /* special case, only high bits matter */
6245 tcg_gen_mov_i64(tcg_src, tcg_src_hi);
6247 tcg_gen_shri_i64(tcg_src, tcg_src, shift);
6248 tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift);
6249 tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi);
6254 /* essentially shifting in 64 zeros */
6255 tcg_gen_movi_i64(tcg_src, 0);
6257 tcg_gen_shri_i64(tcg_src, tcg_src, shift);
6261 /* effectively extending the sign-bit */
6262 tcg_gen_sari_i64(tcg_src, tcg_src, 63);
6264 tcg_gen_sari_i64(tcg_src, tcg_src, shift);
6270 tcg_gen_add_i64(tcg_res, tcg_res, tcg_src);
6272 tcg_gen_mov_i64(tcg_res, tcg_src);
6275 if (extended_result) {
6276 tcg_temp_free_i64(tcg_src_hi);
6280 /* Common SHL/SLI - Shift left with an optional insert */
6281 static void handle_shli_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
6282 bool insert, int shift)
6284 if (insert) { /* SLI */
6285 tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, shift, 64 - shift);
6287 tcg_gen_shli_i64(tcg_res, tcg_src, shift);
6291 /* SRI: shift right with insert */
6292 static void handle_shri_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
6293 int size, int shift)
6295 int esize = 8 << size;
6297 /* shift count same as element size is valid but does nothing;
6298 * special case to avoid potential shift by 64.
6300 if (shift != esize) {
6301 tcg_gen_shri_i64(tcg_src, tcg_src, shift);
6302 tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, 0, esize - shift);
6306 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6307 static void handle_scalar_simd_shri(DisasContext *s,
6308 bool is_u, int immh, int immb,
6309 int opcode, int rn, int rd)
6312 int immhb = immh << 3 | immb;
6313 int shift = 2 * (8 << size) - immhb;
6314 bool accumulate = false;
6316 bool insert = false;
6321 if (!extract32(immh, 3, 1)) {
6322 unallocated_encoding(s);
6326 if (!fp_access_check(s)) {
6331 case 0x02: /* SSRA / USRA (accumulate) */
6334 case 0x04: /* SRSHR / URSHR (rounding) */
6337 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6338 accumulate = round = true;
6340 case 0x08: /* SRI */
6346 uint64_t round_const = 1ULL << (shift - 1);
6347 tcg_round = tcg_const_i64(round_const);
6349 TCGV_UNUSED_I64(tcg_round);
6352 tcg_rn = read_fp_dreg(s, rn);
6353 tcg_rd = (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new_i64();
6356 handle_shri_with_ins(tcg_rd, tcg_rn, size, shift);
6358 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
6359 accumulate, is_u, size, shift);
6362 write_fp_dreg(s, rd, tcg_rd);
6364 tcg_temp_free_i64(tcg_rn);
6365 tcg_temp_free_i64(tcg_rd);
6367 tcg_temp_free_i64(tcg_round);
6371 /* SHL/SLI - Scalar shift left */
6372 static void handle_scalar_simd_shli(DisasContext *s, bool insert,
6373 int immh, int immb, int opcode,
6376 int size = 32 - clz32(immh) - 1;
6377 int immhb = immh << 3 | immb;
6378 int shift = immhb - (8 << size);
6379 TCGv_i64 tcg_rn = new_tmp_a64(s);
6380 TCGv_i64 tcg_rd = new_tmp_a64(s);
6382 if (!extract32(immh, 3, 1)) {
6383 unallocated_encoding(s);
6387 if (!fp_access_check(s)) {
6391 tcg_rn = read_fp_dreg(s, rn);
6392 tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64();
6394 handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift);
6396 write_fp_dreg(s, rd, tcg_rd);
6398 tcg_temp_free_i64(tcg_rn);
6399 tcg_temp_free_i64(tcg_rd);
6402 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6403 * (signed/unsigned) narrowing */
6404 static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
6405 bool is_u_shift, bool is_u_narrow,
6406 int immh, int immb, int opcode,
6409 int immhb = immh << 3 | immb;
6410 int size = 32 - clz32(immh) - 1;
6411 int esize = 8 << size;
6412 int shift = (2 * esize) - immhb;
6413 int elements = is_scalar ? 1 : (64 / esize);
6414 bool round = extract32(opcode, 0, 1);
6415 TCGMemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN);
6416 TCGv_i64 tcg_rn, tcg_rd, tcg_round;
6417 TCGv_i32 tcg_rd_narrowed;
6420 static NeonGenNarrowEnvFn * const signed_narrow_fns[4][2] = {
6421 { gen_helper_neon_narrow_sat_s8,
6422 gen_helper_neon_unarrow_sat8 },
6423 { gen_helper_neon_narrow_sat_s16,
6424 gen_helper_neon_unarrow_sat16 },
6425 { gen_helper_neon_narrow_sat_s32,
6426 gen_helper_neon_unarrow_sat32 },
6429 static NeonGenNarrowEnvFn * const unsigned_narrow_fns[4] = {
6430 gen_helper_neon_narrow_sat_u8,
6431 gen_helper_neon_narrow_sat_u16,
6432 gen_helper_neon_narrow_sat_u32,
6435 NeonGenNarrowEnvFn *narrowfn;
6441 if (extract32(immh, 3, 1)) {
6442 unallocated_encoding(s);
6446 if (!fp_access_check(s)) {
6451 narrowfn = unsigned_narrow_fns[size];
6453 narrowfn = signed_narrow_fns[size][is_u_narrow ? 1 : 0];
6456 tcg_rn = tcg_temp_new_i64();
6457 tcg_rd = tcg_temp_new_i64();
6458 tcg_rd_narrowed = tcg_temp_new_i32();
6459 tcg_final = tcg_const_i64(0);
6462 uint64_t round_const = 1ULL << (shift - 1);
6463 tcg_round = tcg_const_i64(round_const);
6465 TCGV_UNUSED_I64(tcg_round);
6468 for (i = 0; i < elements; i++) {
6469 read_vec_element(s, tcg_rn, rn, i, ldop);
6470 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
6471 false, is_u_shift, size+1, shift);
6472 narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd);
6473 tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed);
6474 tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
6478 clear_vec_high(s, rd);
6479 write_vec_element(s, tcg_final, rd, 0, MO_64);
6481 write_vec_element(s, tcg_final, rd, 1, MO_64);
6485 tcg_temp_free_i64(tcg_round);
6487 tcg_temp_free_i64(tcg_rn);
6488 tcg_temp_free_i64(tcg_rd);
6489 tcg_temp_free_i32(tcg_rd_narrowed);
6490 tcg_temp_free_i64(tcg_final);
6494 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6495 static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
6496 bool src_unsigned, bool dst_unsigned,
6497 int immh, int immb, int rn, int rd)
6499 int immhb = immh << 3 | immb;
6500 int size = 32 - clz32(immh) - 1;
6501 int shift = immhb - (8 << size);
6505 assert(!(scalar && is_q));
6508 if (!is_q && extract32(immh, 3, 1)) {
6509 unallocated_encoding(s);
6513 /* Since we use the variable-shift helpers we must
6514 * replicate the shift count into each element of
6515 * the tcg_shift value.
6519 shift |= shift << 8;
6522 shift |= shift << 16;
6528 g_assert_not_reached();
6532 if (!fp_access_check(s)) {
6537 TCGv_i64 tcg_shift = tcg_const_i64(shift);
6538 static NeonGenTwo64OpEnvFn * const fns[2][2] = {
6539 { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 },
6540 { NULL, gen_helper_neon_qshl_u64 },
6542 NeonGenTwo64OpEnvFn *genfn = fns[src_unsigned][dst_unsigned];
6543 int maxpass = is_q ? 2 : 1;
6545 for (pass = 0; pass < maxpass; pass++) {
6546 TCGv_i64 tcg_op = tcg_temp_new_i64();
6548 read_vec_element(s, tcg_op, rn, pass, MO_64);
6549 genfn(tcg_op, cpu_env, tcg_op, tcg_shift);
6550 write_vec_element(s, tcg_op, rd, pass, MO_64);
6552 tcg_temp_free_i64(tcg_op);
6554 tcg_temp_free_i64(tcg_shift);
6557 clear_vec_high(s, rd);
6560 TCGv_i32 tcg_shift = tcg_const_i32(shift);
6561 static NeonGenTwoOpEnvFn * const fns[2][2][3] = {
6563 { gen_helper_neon_qshl_s8,
6564 gen_helper_neon_qshl_s16,
6565 gen_helper_neon_qshl_s32 },
6566 { gen_helper_neon_qshlu_s8,
6567 gen_helper_neon_qshlu_s16,
6568 gen_helper_neon_qshlu_s32 }
6570 { NULL, NULL, NULL },
6571 { gen_helper_neon_qshl_u8,
6572 gen_helper_neon_qshl_u16,
6573 gen_helper_neon_qshl_u32 }
6576 NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size];
6577 TCGMemOp memop = scalar ? size : MO_32;
6578 int maxpass = scalar ? 1 : is_q ? 4 : 2;
6580 for (pass = 0; pass < maxpass; pass++) {
6581 TCGv_i32 tcg_op = tcg_temp_new_i32();
6583 read_vec_element_i32(s, tcg_op, rn, pass, memop);
6584 genfn(tcg_op, cpu_env, tcg_op, tcg_shift);
6588 tcg_gen_ext8u_i32(tcg_op, tcg_op);
6591 tcg_gen_ext16u_i32(tcg_op, tcg_op);
6596 g_assert_not_reached();
6598 write_fp_sreg(s, rd, tcg_op);
6600 write_vec_element_i32(s, tcg_op, rd, pass, MO_32);
6603 tcg_temp_free_i32(tcg_op);
6605 tcg_temp_free_i32(tcg_shift);
6607 if (!is_q && !scalar) {
6608 clear_vec_high(s, rd);
6613 /* Common vector code for handling integer to FP conversion */
6614 static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
6615 int elements, int is_signed,
6616 int fracbits, int size)
6618 bool is_double = size == 3 ? true : false;
6619 TCGv_ptr tcg_fpst = get_fpstatus_ptr();
6620 TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
6621 TCGv_i64 tcg_int = tcg_temp_new_i64();
6622 TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
6625 for (pass = 0; pass < elements; pass++) {
6626 read_vec_element(s, tcg_int, rn, pass, mop);
6629 TCGv_i64 tcg_double = tcg_temp_new_i64();
6631 gen_helper_vfp_sqtod(tcg_double, tcg_int,
6632 tcg_shift, tcg_fpst);
6634 gen_helper_vfp_uqtod(tcg_double, tcg_int,
6635 tcg_shift, tcg_fpst);
6637 if (elements == 1) {
6638 write_fp_dreg(s, rd, tcg_double);
6640 write_vec_element(s, tcg_double, rd, pass, MO_64);
6642 tcg_temp_free_i64(tcg_double);
6644 TCGv_i32 tcg_single = tcg_temp_new_i32();
6646 gen_helper_vfp_sqtos(tcg_single, tcg_int,
6647 tcg_shift, tcg_fpst);
6649 gen_helper_vfp_uqtos(tcg_single, tcg_int,
6650 tcg_shift, tcg_fpst);
6652 if (elements == 1) {
6653 write_fp_sreg(s, rd, tcg_single);
6655 write_vec_element_i32(s, tcg_single, rd, pass, MO_32);
6657 tcg_temp_free_i32(tcg_single);
6661 if (!is_double && elements == 2) {
6662 clear_vec_high(s, rd);
6665 tcg_temp_free_i64(tcg_int);
6666 tcg_temp_free_ptr(tcg_fpst);
6667 tcg_temp_free_i32(tcg_shift);
6670 /* UCVTF/SCVTF - Integer to FP conversion */
6671 static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,
6672 bool is_q, bool is_u,
6673 int immh, int immb, int opcode,
6676 bool is_double = extract32(immh, 3, 1);
6677 int size = is_double ? MO_64 : MO_32;
6679 int immhb = immh << 3 | immb;
6680 int fracbits = (is_double ? 128 : 64) - immhb;
6682 if (!extract32(immh, 2, 2)) {
6683 unallocated_encoding(s);
6690 elements = is_double ? 2 : is_q ? 4 : 2;
6691 if (is_double && !is_q) {
6692 unallocated_encoding(s);
6697 if (!fp_access_check(s)) {
6701 /* immh == 0 would be a failure of the decode logic */
6704 handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size);
6707 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6708 static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
6709 bool is_q, bool is_u,
6710 int immh, int immb, int rn, int rd)
6712 bool is_double = extract32(immh, 3, 1);
6713 int immhb = immh << 3 | immb;
6714 int fracbits = (is_double ? 128 : 64) - immhb;
6716 TCGv_ptr tcg_fpstatus;
6717 TCGv_i32 tcg_rmode, tcg_shift;
6719 if (!extract32(immh, 2, 2)) {
6720 unallocated_encoding(s);
6724 if (!is_scalar && !is_q && is_double) {
6725 unallocated_encoding(s);
6729 if (!fp_access_check(s)) {
6733 assert(!(is_scalar && is_q));
6735 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
6736 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
6737 tcg_fpstatus = get_fpstatus_ptr();
6738 tcg_shift = tcg_const_i32(fracbits);
6741 int maxpass = is_scalar ? 1 : 2;
6743 for (pass = 0; pass < maxpass; pass++) {
6744 TCGv_i64 tcg_op = tcg_temp_new_i64();
6746 read_vec_element(s, tcg_op, rn, pass, MO_64);
6748 gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
6750 gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
6752 write_vec_element(s, tcg_op, rd, pass, MO_64);
6753 tcg_temp_free_i64(tcg_op);
6756 clear_vec_high(s, rd);
6759 int maxpass = is_scalar ? 1 : is_q ? 4 : 2;
6760 for (pass = 0; pass < maxpass; pass++) {
6761 TCGv_i32 tcg_op = tcg_temp_new_i32();
6763 read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
6765 gen_helper_vfp_touls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
6767 gen_helper_vfp_tosls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
6770 write_fp_sreg(s, rd, tcg_op);
6772 write_vec_element_i32(s, tcg_op, rd, pass, MO_32);
6774 tcg_temp_free_i32(tcg_op);
6776 if (!is_q && !is_scalar) {
6777 clear_vec_high(s, rd);
6781 tcg_temp_free_ptr(tcg_fpstatus);
6782 tcg_temp_free_i32(tcg_shift);
6783 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
6784 tcg_temp_free_i32(tcg_rmode);
6787 /* C3.6.9 AdvSIMD scalar shift by immediate
6788 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6789 * +-----+---+-------------+------+------+--------+---+------+------+
6790 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6791 * +-----+---+-------------+------+------+--------+---+------+------+
6793 * This is the scalar version so it works on a fixed sized registers
6795 static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
6797 int rd = extract32(insn, 0, 5);
6798 int rn = extract32(insn, 5, 5);
6799 int opcode = extract32(insn, 11, 5);
6800 int immb = extract32(insn, 16, 3);
6801 int immh = extract32(insn, 19, 4);
6802 bool is_u = extract32(insn, 29, 1);
6805 unallocated_encoding(s);
6810 case 0x08: /* SRI */
6812 unallocated_encoding(s);
6816 case 0x00: /* SSHR / USHR */
6817 case 0x02: /* SSRA / USRA */
6818 case 0x04: /* SRSHR / URSHR */
6819 case 0x06: /* SRSRA / URSRA */
6820 handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd);
6822 case 0x0a: /* SHL / SLI */
6823 handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd);
6825 case 0x1c: /* SCVTF, UCVTF */
6826 handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb,
6829 case 0x10: /* SQSHRUN, SQSHRUN2 */
6830 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6832 unallocated_encoding(s);
6835 handle_vec_simd_sqshrn(s, true, false, false, true,
6836 immh, immb, opcode, rn, rd);
6838 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6839 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6840 handle_vec_simd_sqshrn(s, true, false, is_u, is_u,
6841 immh, immb, opcode, rn, rd);
6843 case 0xc: /* SQSHLU */
6845 unallocated_encoding(s);
6848 handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd);
6850 case 0xe: /* SQSHL, UQSHL */
6851 handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd);
6853 case 0x1f: /* FCVTZS, FCVTZU */
6854 handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd);
6857 unallocated_encoding(s);
6862 /* C3.6.10 AdvSIMD scalar three different
6863 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6864 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6865 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
6866 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6868 static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
6870 bool is_u = extract32(insn, 29, 1);
6871 int size = extract32(insn, 22, 2);
6872 int opcode = extract32(insn, 12, 4);
6873 int rm = extract32(insn, 16, 5);
6874 int rn = extract32(insn, 5, 5);
6875 int rd = extract32(insn, 0, 5);
6878 unallocated_encoding(s);
6883 case 0x9: /* SQDMLAL, SQDMLAL2 */
6884 case 0xb: /* SQDMLSL, SQDMLSL2 */
6885 case 0xd: /* SQDMULL, SQDMULL2 */
6886 if (size == 0 || size == 3) {
6887 unallocated_encoding(s);
6892 unallocated_encoding(s);
6896 if (!fp_access_check(s)) {
6901 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
6902 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
6903 TCGv_i64 tcg_res = tcg_temp_new_i64();
6905 read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN);
6906 read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN);
6908 tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2);
6909 gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res);
6912 case 0xd: /* SQDMULL, SQDMULL2 */
6914 case 0xb: /* SQDMLSL, SQDMLSL2 */
6915 tcg_gen_neg_i64(tcg_res, tcg_res);
6917 case 0x9: /* SQDMLAL, SQDMLAL2 */
6918 read_vec_element(s, tcg_op1, rd, 0, MO_64);
6919 gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env,
6923 g_assert_not_reached();
6926 write_fp_dreg(s, rd, tcg_res);
6928 tcg_temp_free_i64(tcg_op1);
6929 tcg_temp_free_i64(tcg_op2);
6930 tcg_temp_free_i64(tcg_res);
6932 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
6933 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
6934 TCGv_i64 tcg_res = tcg_temp_new_i64();
6936 read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
6937 read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
6939 gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
6940 gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
6943 case 0xd: /* SQDMULL, SQDMULL2 */
6945 case 0xb: /* SQDMLSL, SQDMLSL2 */
6946 gen_helper_neon_negl_u32(tcg_res, tcg_res);
6948 case 0x9: /* SQDMLAL, SQDMLAL2 */
6950 TCGv_i64 tcg_op3 = tcg_temp_new_i64();
6951 read_vec_element(s, tcg_op3, rd, 0, MO_32);
6952 gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env,
6954 tcg_temp_free_i64(tcg_op3);
6958 g_assert_not_reached();
6961 tcg_gen_ext32u_i64(tcg_res, tcg_res);
6962 write_fp_dreg(s, rd, tcg_res);
6964 tcg_temp_free_i32(tcg_op1);
6965 tcg_temp_free_i32(tcg_op2);
6966 tcg_temp_free_i64(tcg_res);
6970 static void handle_3same_64(DisasContext *s, int opcode, bool u,
6971 TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm)
6973 /* Handle 64x64->64 opcodes which are shared between the scalar
6974 * and vector 3-same groups. We cover every opcode where size == 3
6975 * is valid in either the three-reg-same (integer, not pairwise)
6976 * or scalar-three-reg-same groups. (Some opcodes are not yet
6982 case 0x1: /* SQADD */
6984 gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
6986 gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
6989 case 0x5: /* SQSUB */
6991 gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
6993 gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
6996 case 0x6: /* CMGT, CMHI */
6997 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
6998 * We implement this using setcond (test) and then negating.
7000 cond = u ? TCG_COND_GTU : TCG_COND_GT;
7002 tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm);
7003 tcg_gen_neg_i64(tcg_rd, tcg_rd);
7005 case 0x7: /* CMGE, CMHS */
7006 cond = u ? TCG_COND_GEU : TCG_COND_GE;
7008 case 0x11: /* CMTST, CMEQ */
7013 /* CMTST : test is "if (X & Y != 0)". */
7014 tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
7015 tcg_gen_setcondi_i64(TCG_COND_NE, tcg_rd, tcg_rd, 0);
7016 tcg_gen_neg_i64(tcg_rd, tcg_rd);
7018 case 0x8: /* SSHL, USHL */
7020 gen_helper_neon_shl_u64(tcg_rd, tcg_rn, tcg_rm);
7022 gen_helper_neon_shl_s64(tcg_rd, tcg_rn, tcg_rm);
7025 case 0x9: /* SQSHL, UQSHL */
7027 gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
7029 gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
7032 case 0xa: /* SRSHL, URSHL */
7034 gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm);
7036 gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm);
7039 case 0xb: /* SQRSHL, UQRSHL */
7041 gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
7043 gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
7046 case 0x10: /* ADD, SUB */
7048 tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm);
7050 tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm);
7054 g_assert_not_reached();
7058 /* Handle the 3-same-operands float operations; shared by the scalar
7059 * and vector encodings. The caller must filter out any encodings
7060 * not allocated for the encoding it is dealing with.
7062 static void handle_3same_float(DisasContext *s, int size, int elements,
7063 int fpopcode, int rd, int rn, int rm)
7066 TCGv_ptr fpst = get_fpstatus_ptr();
7068 for (pass = 0; pass < elements; pass++) {
7071 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
7072 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
7073 TCGv_i64 tcg_res = tcg_temp_new_i64();
7075 read_vec_element(s, tcg_op1, rn, pass, MO_64);
7076 read_vec_element(s, tcg_op2, rm, pass, MO_64);
7079 case 0x39: /* FMLS */
7080 /* As usual for ARM, separate negation for fused multiply-add */
7081 gen_helper_vfp_negd(tcg_op1, tcg_op1);
7083 case 0x19: /* FMLA */
7084 read_vec_element(s, tcg_res, rd, pass, MO_64);
7085 gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2,
7088 case 0x18: /* FMAXNM */
7089 gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
7091 case 0x1a: /* FADD */
7092 gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
7094 case 0x1b: /* FMULX */
7095 gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst);
7097 case 0x1c: /* FCMEQ */
7098 gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst);
7100 case 0x1e: /* FMAX */
7101 gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
7103 case 0x1f: /* FRECPS */
7104 gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst);
7106 case 0x38: /* FMINNM */
7107 gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
7109 case 0x3a: /* FSUB */
7110 gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
7112 case 0x3e: /* FMIN */
7113 gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
7115 case 0x3f: /* FRSQRTS */
7116 gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst);
7118 case 0x5b: /* FMUL */
7119 gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
7121 case 0x5c: /* FCMGE */
7122 gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst);
7124 case 0x5d: /* FACGE */
7125 gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst);
7127 case 0x5f: /* FDIV */
7128 gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
7130 case 0x7a: /* FABD */
7131 gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
7132 gen_helper_vfp_absd(tcg_res, tcg_res);
7134 case 0x7c: /* FCMGT */
7135 gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst);
7137 case 0x7d: /* FACGT */
7138 gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst);
7141 g_assert_not_reached();
7144 write_vec_element(s, tcg_res, rd, pass, MO_64);
7146 tcg_temp_free_i64(tcg_res);
7147 tcg_temp_free_i64(tcg_op1);
7148 tcg_temp_free_i64(tcg_op2);
7151 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
7152 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
7153 TCGv_i32 tcg_res = tcg_temp_new_i32();
7155 read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
7156 read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
7159 case 0x39: /* FMLS */
7160 /* As usual for ARM, separate negation for fused multiply-add */
7161 gen_helper_vfp_negs(tcg_op1, tcg_op1);
7163 case 0x19: /* FMLA */
7164 read_vec_element_i32(s, tcg_res, rd, pass, MO_32);
7165 gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2,
7168 case 0x1a: /* FADD */
7169 gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
7171 case 0x1b: /* FMULX */
7172 gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst);
7174 case 0x1c: /* FCMEQ */
7175 gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7177 case 0x1e: /* FMAX */
7178 gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
7180 case 0x1f: /* FRECPS */
7181 gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7183 case 0x18: /* FMAXNM */
7184 gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
7186 case 0x38: /* FMINNM */
7187 gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
7189 case 0x3a: /* FSUB */
7190 gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
7192 case 0x3e: /* FMIN */
7193 gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
7195 case 0x3f: /* FRSQRTS */
7196 gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7198 case 0x5b: /* FMUL */
7199 gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
7201 case 0x5c: /* FCMGE */
7202 gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7204 case 0x5d: /* FACGE */
7205 gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7207 case 0x5f: /* FDIV */
7208 gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst);
7210 case 0x7a: /* FABD */
7211 gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
7212 gen_helper_vfp_abss(tcg_res, tcg_res);
7214 case 0x7c: /* FCMGT */
7215 gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7217 case 0x7d: /* FACGT */
7218 gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7221 g_assert_not_reached();
7224 if (elements == 1) {
7225 /* scalar single so clear high part */
7226 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
7228 tcg_gen_extu_i32_i64(tcg_tmp, tcg_res);
7229 write_vec_element(s, tcg_tmp, rd, pass, MO_64);
7230 tcg_temp_free_i64(tcg_tmp);
7232 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
7235 tcg_temp_free_i32(tcg_res);
7236 tcg_temp_free_i32(tcg_op1);
7237 tcg_temp_free_i32(tcg_op2);
7241 tcg_temp_free_ptr(fpst);
7243 if ((elements << size) < 4) {
7244 /* scalar, or non-quad vector op */
7245 clear_vec_high(s, rd);
7249 /* C3.6.11 AdvSIMD scalar three same
7250 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7251 * +-----+---+-----------+------+---+------+--------+---+------+------+
7252 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7253 * +-----+---+-----------+------+---+------+--------+---+------+------+
7255 static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
7257 int rd = extract32(insn, 0, 5);
7258 int rn = extract32(insn, 5, 5);
7259 int opcode = extract32(insn, 11, 5);
7260 int rm = extract32(insn, 16, 5);
7261 int size = extract32(insn, 22, 2);
7262 bool u = extract32(insn, 29, 1);
7265 if (opcode >= 0x18) {
7266 /* Floating point: U, size[1] and opcode indicate operation */
7267 int fpopcode = opcode | (extract32(size, 1, 1) << 5) | (u << 6);
7269 case 0x1b: /* FMULX */
7270 case 0x1f: /* FRECPS */
7271 case 0x3f: /* FRSQRTS */
7272 case 0x5d: /* FACGE */
7273 case 0x7d: /* FACGT */
7274 case 0x1c: /* FCMEQ */
7275 case 0x5c: /* FCMGE */
7276 case 0x7c: /* FCMGT */
7277 case 0x7a: /* FABD */
7280 unallocated_encoding(s);
7284 if (!fp_access_check(s)) {
7288 handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm);
7293 case 0x1: /* SQADD, UQADD */
7294 case 0x5: /* SQSUB, UQSUB */
7295 case 0x9: /* SQSHL, UQSHL */
7296 case 0xb: /* SQRSHL, UQRSHL */
7298 case 0x8: /* SSHL, USHL */
7299 case 0xa: /* SRSHL, URSHL */
7300 case 0x6: /* CMGT, CMHI */
7301 case 0x7: /* CMGE, CMHS */
7302 case 0x11: /* CMTST, CMEQ */
7303 case 0x10: /* ADD, SUB (vector) */
7305 unallocated_encoding(s);
7309 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7310 if (size != 1 && size != 2) {
7311 unallocated_encoding(s);
7316 unallocated_encoding(s);
7320 if (!fp_access_check(s)) {
7324 tcg_rd = tcg_temp_new_i64();
7327 TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
7328 TCGv_i64 tcg_rm = read_fp_dreg(s, rm);
7330 handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm);
7331 tcg_temp_free_i64(tcg_rn);
7332 tcg_temp_free_i64(tcg_rm);
7334 /* Do a single operation on the lowest element in the vector.
7335 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7336 * no side effects for all these operations.
7337 * OPTME: special-purpose helpers would avoid doing some
7338 * unnecessary work in the helper for the 8 and 16 bit cases.
7340 NeonGenTwoOpEnvFn *genenvfn;
7341 TCGv_i32 tcg_rn = tcg_temp_new_i32();
7342 TCGv_i32 tcg_rm = tcg_temp_new_i32();
7343 TCGv_i32 tcg_rd32 = tcg_temp_new_i32();
7345 read_vec_element_i32(s, tcg_rn, rn, 0, size);
7346 read_vec_element_i32(s, tcg_rm, rm, 0, size);
7349 case 0x1: /* SQADD, UQADD */
7351 static NeonGenTwoOpEnvFn * const fns[3][2] = {
7352 { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 },
7353 { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 },
7354 { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 },
7356 genenvfn = fns[size][u];
7359 case 0x5: /* SQSUB, UQSUB */
7361 static NeonGenTwoOpEnvFn * const fns[3][2] = {
7362 { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 },
7363 { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 },
7364 { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 },
7366 genenvfn = fns[size][u];
7369 case 0x9: /* SQSHL, UQSHL */
7371 static NeonGenTwoOpEnvFn * const fns[3][2] = {
7372 { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 },
7373 { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 },
7374 { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 },
7376 genenvfn = fns[size][u];
7379 case 0xb: /* SQRSHL, UQRSHL */
7381 static NeonGenTwoOpEnvFn * const fns[3][2] = {
7382 { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 },
7383 { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 },
7384 { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 },
7386 genenvfn = fns[size][u];
7389 case 0x16: /* SQDMULH, SQRDMULH */
7391 static NeonGenTwoOpEnvFn * const fns[2][2] = {
7392 { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 },
7393 { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 },
7395 assert(size == 1 || size == 2);
7396 genenvfn = fns[size - 1][u];
7400 g_assert_not_reached();
7403 genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm);
7404 tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32);
7405 tcg_temp_free_i32(tcg_rd32);
7406 tcg_temp_free_i32(tcg_rn);
7407 tcg_temp_free_i32(tcg_rm);
7410 write_fp_dreg(s, rd, tcg_rd);
7412 tcg_temp_free_i64(tcg_rd);
7415 static void handle_2misc_64(DisasContext *s, int opcode, bool u,
7416 TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
7417 TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
7419 /* Handle 64->64 opcodes which are shared between the scalar and
7420 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7421 * is valid in either group and also the double-precision fp ops.
7422 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7428 case 0x4: /* CLS, CLZ */
7430 gen_helper_clz64(tcg_rd, tcg_rn);
7432 gen_helper_cls64(tcg_rd, tcg_rn);
7436 /* This opcode is shared with CNT and RBIT but we have earlier
7437 * enforced that size == 3 if and only if this is the NOT insn.
7439 tcg_gen_not_i64(tcg_rd, tcg_rn);
7441 case 0x7: /* SQABS, SQNEG */
7443 gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn);
7445 gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn);
7448 case 0xa: /* CMLT */
7449 /* 64 bit integer comparison against zero, result is
7450 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7455 tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0);
7456 tcg_gen_neg_i64(tcg_rd, tcg_rd);
7458 case 0x8: /* CMGT, CMGE */
7459 cond = u ? TCG_COND_GE : TCG_COND_GT;
7461 case 0x9: /* CMEQ, CMLE */
7462 cond = u ? TCG_COND_LE : TCG_COND_EQ;
7464 case 0xb: /* ABS, NEG */
7466 tcg_gen_neg_i64(tcg_rd, tcg_rn);
7468 TCGv_i64 tcg_zero = tcg_const_i64(0);
7469 tcg_gen_neg_i64(tcg_rd, tcg_rn);
7470 tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero,
7472 tcg_temp_free_i64(tcg_zero);
7475 case 0x2f: /* FABS */
7476 gen_helper_vfp_absd(tcg_rd, tcg_rn);
7478 case 0x6f: /* FNEG */
7479 gen_helper_vfp_negd(tcg_rd, tcg_rn);
7481 case 0x7f: /* FSQRT */
7482 gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env);
7484 case 0x1a: /* FCVTNS */
7485 case 0x1b: /* FCVTMS */
7486 case 0x1c: /* FCVTAS */
7487 case 0x3a: /* FCVTPS */
7488 case 0x3b: /* FCVTZS */
7490 TCGv_i32 tcg_shift = tcg_const_i32(0);
7491 gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
7492 tcg_temp_free_i32(tcg_shift);
7495 case 0x5a: /* FCVTNU */
7496 case 0x5b: /* FCVTMU */
7497 case 0x5c: /* FCVTAU */
7498 case 0x7a: /* FCVTPU */
7499 case 0x7b: /* FCVTZU */
7501 TCGv_i32 tcg_shift = tcg_const_i32(0);
7502 gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
7503 tcg_temp_free_i32(tcg_shift);
7506 case 0x18: /* FRINTN */
7507 case 0x19: /* FRINTM */
7508 case 0x38: /* FRINTP */
7509 case 0x39: /* FRINTZ */
7510 case 0x58: /* FRINTA */
7511 case 0x79: /* FRINTI */
7512 gen_helper_rintd(tcg_rd, tcg_rn, tcg_fpstatus);
7514 case 0x59: /* FRINTX */
7515 gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus);
7518 g_assert_not_reached();
7522 static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
7523 bool is_scalar, bool is_u, bool is_q,
7524 int size, int rn, int rd)
7526 bool is_double = (size == 3);
7529 if (!fp_access_check(s)) {
7533 fpst = get_fpstatus_ptr();
7536 TCGv_i64 tcg_op = tcg_temp_new_i64();
7537 TCGv_i64 tcg_zero = tcg_const_i64(0);
7538 TCGv_i64 tcg_res = tcg_temp_new_i64();
7539 NeonGenTwoDoubleOPFn *genfn;
7544 case 0x2e: /* FCMLT (zero) */
7547 case 0x2c: /* FCMGT (zero) */
7548 genfn = gen_helper_neon_cgt_f64;
7550 case 0x2d: /* FCMEQ (zero) */
7551 genfn = gen_helper_neon_ceq_f64;
7553 case 0x6d: /* FCMLE (zero) */
7556 case 0x6c: /* FCMGE (zero) */
7557 genfn = gen_helper_neon_cge_f64;
7560 g_assert_not_reached();
7563 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
7564 read_vec_element(s, tcg_op, rn, pass, MO_64);
7566 genfn(tcg_res, tcg_zero, tcg_op, fpst);
7568 genfn(tcg_res, tcg_op, tcg_zero, fpst);
7570 write_vec_element(s, tcg_res, rd, pass, MO_64);
7573 clear_vec_high(s, rd);
7576 tcg_temp_free_i64(tcg_res);
7577 tcg_temp_free_i64(tcg_zero);
7578 tcg_temp_free_i64(tcg_op);
7580 TCGv_i32 tcg_op = tcg_temp_new_i32();
7581 TCGv_i32 tcg_zero = tcg_const_i32(0);
7582 TCGv_i32 tcg_res = tcg_temp_new_i32();
7583 NeonGenTwoSingleOPFn *genfn;
7585 int pass, maxpasses;
7588 case 0x2e: /* FCMLT (zero) */
7591 case 0x2c: /* FCMGT (zero) */
7592 genfn = gen_helper_neon_cgt_f32;
7594 case 0x2d: /* FCMEQ (zero) */
7595 genfn = gen_helper_neon_ceq_f32;
7597 case 0x6d: /* FCMLE (zero) */
7600 case 0x6c: /* FCMGE (zero) */
7601 genfn = gen_helper_neon_cge_f32;
7604 g_assert_not_reached();
7610 maxpasses = is_q ? 4 : 2;
7613 for (pass = 0; pass < maxpasses; pass++) {
7614 read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
7616 genfn(tcg_res, tcg_zero, tcg_op, fpst);
7618 genfn(tcg_res, tcg_op, tcg_zero, fpst);
7621 write_fp_sreg(s, rd, tcg_res);
7623 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
7626 tcg_temp_free_i32(tcg_res);
7627 tcg_temp_free_i32(tcg_zero);
7628 tcg_temp_free_i32(tcg_op);
7629 if (!is_q && !is_scalar) {
7630 clear_vec_high(s, rd);
7634 tcg_temp_free_ptr(fpst);
7637 static void handle_2misc_reciprocal(DisasContext *s, int opcode,
7638 bool is_scalar, bool is_u, bool is_q,
7639 int size, int rn, int rd)
7641 bool is_double = (size == 3);
7642 TCGv_ptr fpst = get_fpstatus_ptr();
7645 TCGv_i64 tcg_op = tcg_temp_new_i64();
7646 TCGv_i64 tcg_res = tcg_temp_new_i64();
7649 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
7650 read_vec_element(s, tcg_op, rn, pass, MO_64);
7652 case 0x3d: /* FRECPE */
7653 gen_helper_recpe_f64(tcg_res, tcg_op, fpst);
7655 case 0x3f: /* FRECPX */
7656 gen_helper_frecpx_f64(tcg_res, tcg_op, fpst);
7658 case 0x7d: /* FRSQRTE */
7659 gen_helper_rsqrte_f64(tcg_res, tcg_op, fpst);
7662 g_assert_not_reached();
7664 write_vec_element(s, tcg_res, rd, pass, MO_64);
7667 clear_vec_high(s, rd);
7670 tcg_temp_free_i64(tcg_res);
7671 tcg_temp_free_i64(tcg_op);
7673 TCGv_i32 tcg_op = tcg_temp_new_i32();
7674 TCGv_i32 tcg_res = tcg_temp_new_i32();
7675 int pass, maxpasses;
7680 maxpasses = is_q ? 4 : 2;
7683 for (pass = 0; pass < maxpasses; pass++) {
7684 read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
7687 case 0x3c: /* URECPE */
7688 gen_helper_recpe_u32(tcg_res, tcg_op, fpst);
7690 case 0x3d: /* FRECPE */
7691 gen_helper_recpe_f32(tcg_res, tcg_op, fpst);
7693 case 0x3f: /* FRECPX */
7694 gen_helper_frecpx_f32(tcg_res, tcg_op, fpst);
7696 case 0x7d: /* FRSQRTE */
7697 gen_helper_rsqrte_f32(tcg_res, tcg_op, fpst);
7700 g_assert_not_reached();
7704 write_fp_sreg(s, rd, tcg_res);
7706 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
7709 tcg_temp_free_i32(tcg_res);
7710 tcg_temp_free_i32(tcg_op);
7711 if (!is_q && !is_scalar) {
7712 clear_vec_high(s, rd);
7715 tcg_temp_free_ptr(fpst);
7718 static void handle_2misc_narrow(DisasContext *s, bool scalar,
7719 int opcode, bool u, bool is_q,
7720 int size, int rn, int rd)
7722 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7723 * in the source becomes a size element in the destination).
7726 TCGv_i32 tcg_res[2];
7727 int destelt = is_q ? 2 : 0;
7728 int passes = scalar ? 1 : 2;
7731 tcg_res[1] = tcg_const_i32(0);
7734 for (pass = 0; pass < passes; pass++) {
7735 TCGv_i64 tcg_op = tcg_temp_new_i64();
7736 NeonGenNarrowFn *genfn = NULL;
7737 NeonGenNarrowEnvFn *genenvfn = NULL;
7740 read_vec_element(s, tcg_op, rn, pass, size + 1);
7742 read_vec_element(s, tcg_op, rn, pass, MO_64);
7744 tcg_res[pass] = tcg_temp_new_i32();
7747 case 0x12: /* XTN, SQXTUN */
7749 static NeonGenNarrowFn * const xtnfns[3] = {
7750 gen_helper_neon_narrow_u8,
7751 gen_helper_neon_narrow_u16,
7752 tcg_gen_extrl_i64_i32,
7754 static NeonGenNarrowEnvFn * const sqxtunfns[3] = {
7755 gen_helper_neon_unarrow_sat8,
7756 gen_helper_neon_unarrow_sat16,
7757 gen_helper_neon_unarrow_sat32,
7760 genenvfn = sqxtunfns[size];
7762 genfn = xtnfns[size];
7766 case 0x14: /* SQXTN, UQXTN */
7768 static NeonGenNarrowEnvFn * const fns[3][2] = {
7769 { gen_helper_neon_narrow_sat_s8,
7770 gen_helper_neon_narrow_sat_u8 },
7771 { gen_helper_neon_narrow_sat_s16,
7772 gen_helper_neon_narrow_sat_u16 },
7773 { gen_helper_neon_narrow_sat_s32,
7774 gen_helper_neon_narrow_sat_u32 },
7776 genenvfn = fns[size][u];
7779 case 0x16: /* FCVTN, FCVTN2 */
7780 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7782 gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env);
7784 TCGv_i32 tcg_lo = tcg_temp_new_i32();
7785 TCGv_i32 tcg_hi = tcg_temp_new_i32();
7786 tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op);
7787 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env);
7788 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env);
7789 tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16);
7790 tcg_temp_free_i32(tcg_lo);
7791 tcg_temp_free_i32(tcg_hi);
7794 case 0x56: /* FCVTXN, FCVTXN2 */
7795 /* 64 bit to 32 bit float conversion
7796 * with von Neumann rounding (round to odd)
7799 gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env);
7802 g_assert_not_reached();
7806 genfn(tcg_res[pass], tcg_op);
7807 } else if (genenvfn) {
7808 genenvfn(tcg_res[pass], cpu_env, tcg_op);
7811 tcg_temp_free_i64(tcg_op);
7814 for (pass = 0; pass < 2; pass++) {
7815 write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32);
7816 tcg_temp_free_i32(tcg_res[pass]);
7819 clear_vec_high(s, rd);
7823 /* Remaining saturating accumulating ops */
7824 static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
7825 bool is_q, int size, int rn, int rd)
7827 bool is_double = (size == 3);
7830 TCGv_i64 tcg_rn = tcg_temp_new_i64();
7831 TCGv_i64 tcg_rd = tcg_temp_new_i64();
7834 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
7835 read_vec_element(s, tcg_rn, rn, pass, MO_64);
7836 read_vec_element(s, tcg_rd, rd, pass, MO_64);
7838 if (is_u) { /* USQADD */
7839 gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7840 } else { /* SUQADD */
7841 gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7843 write_vec_element(s, tcg_rd, rd, pass, MO_64);
7846 clear_vec_high(s, rd);
7849 tcg_temp_free_i64(tcg_rd);
7850 tcg_temp_free_i64(tcg_rn);
7852 TCGv_i32 tcg_rn = tcg_temp_new_i32();
7853 TCGv_i32 tcg_rd = tcg_temp_new_i32();
7854 int pass, maxpasses;
7859 maxpasses = is_q ? 4 : 2;
7862 for (pass = 0; pass < maxpasses; pass++) {
7864 read_vec_element_i32(s, tcg_rn, rn, pass, size);
7865 read_vec_element_i32(s, tcg_rd, rd, pass, size);
7867 read_vec_element_i32(s, tcg_rn, rn, pass, MO_32);
7868 read_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
7871 if (is_u) { /* USQADD */
7874 gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7877 gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7880 gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7883 g_assert_not_reached();
7885 } else { /* SUQADD */
7888 gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7891 gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7894 gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7897 g_assert_not_reached();
7902 TCGv_i64 tcg_zero = tcg_const_i64(0);
7903 write_vec_element(s, tcg_zero, rd, 0, MO_64);
7904 tcg_temp_free_i64(tcg_zero);
7906 write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
7910 clear_vec_high(s, rd);
7913 tcg_temp_free_i32(tcg_rd);
7914 tcg_temp_free_i32(tcg_rn);
7918 /* C3.6.12 AdvSIMD scalar two reg misc
7919 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7920 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7921 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
7922 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7924 static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
7926 int rd = extract32(insn, 0, 5);
7927 int rn = extract32(insn, 5, 5);
7928 int opcode = extract32(insn, 12, 5);
7929 int size = extract32(insn, 22, 2);
7930 bool u = extract32(insn, 29, 1);
7931 bool is_fcvt = false;
7934 TCGv_ptr tcg_fpstatus;
7937 case 0x3: /* USQADD / SUQADD*/
7938 if (!fp_access_check(s)) {
7941 handle_2misc_satacc(s, true, u, false, size, rn, rd);
7943 case 0x7: /* SQABS / SQNEG */
7945 case 0xa: /* CMLT */
7947 unallocated_encoding(s);
7951 case 0x8: /* CMGT, CMGE */
7952 case 0x9: /* CMEQ, CMLE */
7953 case 0xb: /* ABS, NEG */
7955 unallocated_encoding(s);
7959 case 0x12: /* SQXTUN */
7961 unallocated_encoding(s);
7965 case 0x14: /* SQXTN, UQXTN */
7967 unallocated_encoding(s);
7970 if (!fp_access_check(s)) {
7973 handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd);
7978 /* Floating point: U, size[1] and opcode indicate operation;
7979 * size[0] indicates single or double precision.
7981 opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
7982 size = extract32(size, 0, 1) ? 3 : 2;
7984 case 0x2c: /* FCMGT (zero) */
7985 case 0x2d: /* FCMEQ (zero) */
7986 case 0x2e: /* FCMLT (zero) */
7987 case 0x6c: /* FCMGE (zero) */
7988 case 0x6d: /* FCMLE (zero) */
7989 handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd);
7991 case 0x1d: /* SCVTF */
7992 case 0x5d: /* UCVTF */
7994 bool is_signed = (opcode == 0x1d);
7995 if (!fp_access_check(s)) {
7998 handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size);
8001 case 0x3d: /* FRECPE */
8002 case 0x3f: /* FRECPX */
8003 case 0x7d: /* FRSQRTE */
8004 if (!fp_access_check(s)) {
8007 handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd);
8009 case 0x1a: /* FCVTNS */
8010 case 0x1b: /* FCVTMS */
8011 case 0x3a: /* FCVTPS */
8012 case 0x3b: /* FCVTZS */
8013 case 0x5a: /* FCVTNU */
8014 case 0x5b: /* FCVTMU */
8015 case 0x7a: /* FCVTPU */
8016 case 0x7b: /* FCVTZU */
8018 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
8020 case 0x1c: /* FCVTAS */
8021 case 0x5c: /* FCVTAU */
8022 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8024 rmode = FPROUNDING_TIEAWAY;
8026 case 0x56: /* FCVTXN, FCVTXN2 */
8028 unallocated_encoding(s);
8031 if (!fp_access_check(s)) {
8034 handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd);
8037 unallocated_encoding(s);
8042 unallocated_encoding(s);
8046 if (!fp_access_check(s)) {
8051 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
8052 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
8053 tcg_fpstatus = get_fpstatus_ptr();
8055 TCGV_UNUSED_I32(tcg_rmode);
8056 TCGV_UNUSED_PTR(tcg_fpstatus);
8060 TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
8061 TCGv_i64 tcg_rd = tcg_temp_new_i64();
8063 handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus);
8064 write_fp_dreg(s, rd, tcg_rd);
8065 tcg_temp_free_i64(tcg_rd);
8066 tcg_temp_free_i64(tcg_rn);
8068 TCGv_i32 tcg_rn = tcg_temp_new_i32();
8069 TCGv_i32 tcg_rd = tcg_temp_new_i32();
8071 read_vec_element_i32(s, tcg_rn, rn, 0, size);
8074 case 0x7: /* SQABS, SQNEG */
8076 NeonGenOneOpEnvFn *genfn;
8077 static NeonGenOneOpEnvFn * const fns[3][2] = {
8078 { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
8079 { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
8080 { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 },
8082 genfn = fns[size][u];
8083 genfn(tcg_rd, cpu_env, tcg_rn);
8086 case 0x1a: /* FCVTNS */
8087 case 0x1b: /* FCVTMS */
8088 case 0x1c: /* FCVTAS */
8089 case 0x3a: /* FCVTPS */
8090 case 0x3b: /* FCVTZS */
8092 TCGv_i32 tcg_shift = tcg_const_i32(0);
8093 gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
8094 tcg_temp_free_i32(tcg_shift);
8097 case 0x5a: /* FCVTNU */
8098 case 0x5b: /* FCVTMU */
8099 case 0x5c: /* FCVTAU */
8100 case 0x7a: /* FCVTPU */
8101 case 0x7b: /* FCVTZU */
8103 TCGv_i32 tcg_shift = tcg_const_i32(0);
8104 gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
8105 tcg_temp_free_i32(tcg_shift);
8109 g_assert_not_reached();
8112 write_fp_sreg(s, rd, tcg_rd);
8113 tcg_temp_free_i32(tcg_rd);
8114 tcg_temp_free_i32(tcg_rn);
8118 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
8119 tcg_temp_free_i32(tcg_rmode);
8120 tcg_temp_free_ptr(tcg_fpstatus);
8124 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8125 static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
8126 int immh, int immb, int opcode, int rn, int rd)
8128 int size = 32 - clz32(immh) - 1;
8129 int immhb = immh << 3 | immb;
8130 int shift = 2 * (8 << size) - immhb;
8131 bool accumulate = false;
8133 bool insert = false;
8134 int dsize = is_q ? 128 : 64;
8135 int esize = 8 << size;
8136 int elements = dsize/esize;
8137 TCGMemOp memop = size | (is_u ? 0 : MO_SIGN);
8138 TCGv_i64 tcg_rn = new_tmp_a64(s);
8139 TCGv_i64 tcg_rd = new_tmp_a64(s);
8143 if (extract32(immh, 3, 1) && !is_q) {
8144 unallocated_encoding(s);
8148 if (size > 3 && !is_q) {
8149 unallocated_encoding(s);
8153 if (!fp_access_check(s)) {
8158 case 0x02: /* SSRA / USRA (accumulate) */
8161 case 0x04: /* SRSHR / URSHR (rounding) */
8164 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8165 accumulate = round = true;
8167 case 0x08: /* SRI */
8173 uint64_t round_const = 1ULL << (shift - 1);
8174 tcg_round = tcg_const_i64(round_const);
8176 TCGV_UNUSED_I64(tcg_round);
8179 for (i = 0; i < elements; i++) {
8180 read_vec_element(s, tcg_rn, rn, i, memop);
8181 if (accumulate || insert) {
8182 read_vec_element(s, tcg_rd, rd, i, memop);
8186 handle_shri_with_ins(tcg_rd, tcg_rn, size, shift);
8188 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
8189 accumulate, is_u, size, shift);
8192 write_vec_element(s, tcg_rd, rd, i, size);
8196 clear_vec_high(s, rd);
8200 tcg_temp_free_i64(tcg_round);
8204 /* SHL/SLI - Vector shift left */
8205 static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
8206 int immh, int immb, int opcode, int rn, int rd)
8208 int size = 32 - clz32(immh) - 1;
8209 int immhb = immh << 3 | immb;
8210 int shift = immhb - (8 << size);
8211 int dsize = is_q ? 128 : 64;
8212 int esize = 8 << size;
8213 int elements = dsize/esize;
8214 TCGv_i64 tcg_rn = new_tmp_a64(s);
8215 TCGv_i64 tcg_rd = new_tmp_a64(s);
8218 if (extract32(immh, 3, 1) && !is_q) {
8219 unallocated_encoding(s);
8223 if (size > 3 && !is_q) {
8224 unallocated_encoding(s);
8228 if (!fp_access_check(s)) {
8232 for (i = 0; i < elements; i++) {
8233 read_vec_element(s, tcg_rn, rn, i, size);
8235 read_vec_element(s, tcg_rd, rd, i, size);
8238 handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift);
8240 write_vec_element(s, tcg_rd, rd, i, size);
8244 clear_vec_high(s, rd);
8248 /* USHLL/SHLL - Vector shift left with widening */
8249 static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,
8250 int immh, int immb, int opcode, int rn, int rd)
8252 int size = 32 - clz32(immh) - 1;
8253 int immhb = immh << 3 | immb;
8254 int shift = immhb - (8 << size);
8256 int esize = 8 << size;
8257 int elements = dsize/esize;
8258 TCGv_i64 tcg_rn = new_tmp_a64(s);
8259 TCGv_i64 tcg_rd = new_tmp_a64(s);
8263 unallocated_encoding(s);
8267 if (!fp_access_check(s)) {
8271 /* For the LL variants the store is larger than the load,
8272 * so if rd == rn we would overwrite parts of our input.
8273 * So load everything right now and use shifts in the main loop.
8275 read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64);
8277 for (i = 0; i < elements; i++) {
8278 tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize);
8279 ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0);
8280 tcg_gen_shli_i64(tcg_rd, tcg_rd, shift);
8281 write_vec_element(s, tcg_rd, rd, i, size + 1);
8285 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8286 static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
8287 int immh, int immb, int opcode, int rn, int rd)
8289 int immhb = immh << 3 | immb;
8290 int size = 32 - clz32(immh) - 1;
8292 int esize = 8 << size;
8293 int elements = dsize/esize;
8294 int shift = (2 * esize) - immhb;
8295 bool round = extract32(opcode, 0, 1);
8296 TCGv_i64 tcg_rn, tcg_rd, tcg_final;
8300 if (extract32(immh, 3, 1)) {
8301 unallocated_encoding(s);
8305 if (!fp_access_check(s)) {
8309 tcg_rn = tcg_temp_new_i64();
8310 tcg_rd = tcg_temp_new_i64();
8311 tcg_final = tcg_temp_new_i64();
8312 read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64);
8315 uint64_t round_const = 1ULL << (shift - 1);
8316 tcg_round = tcg_const_i64(round_const);
8318 TCGV_UNUSED_I64(tcg_round);
8321 for (i = 0; i < elements; i++) {
8322 read_vec_element(s, tcg_rn, rn, i, size+1);
8323 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
8324 false, true, size+1, shift);
8326 tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
8330 clear_vec_high(s, rd);
8331 write_vec_element(s, tcg_final, rd, 0, MO_64);
8333 write_vec_element(s, tcg_final, rd, 1, MO_64);
8337 tcg_temp_free_i64(tcg_round);
8339 tcg_temp_free_i64(tcg_rn);
8340 tcg_temp_free_i64(tcg_rd);
8341 tcg_temp_free_i64(tcg_final);
8346 /* C3.6.14 AdvSIMD shift by immediate
8347 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8348 * +---+---+---+-------------+------+------+--------+---+------+------+
8349 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8350 * +---+---+---+-------------+------+------+--------+---+------+------+
8352 static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
8354 int rd = extract32(insn, 0, 5);
8355 int rn = extract32(insn, 5, 5);
8356 int opcode = extract32(insn, 11, 5);
8357 int immb = extract32(insn, 16, 3);
8358 int immh = extract32(insn, 19, 4);
8359 bool is_u = extract32(insn, 29, 1);
8360 bool is_q = extract32(insn, 30, 1);
8363 case 0x08: /* SRI */
8365 unallocated_encoding(s);
8369 case 0x00: /* SSHR / USHR */
8370 case 0x02: /* SSRA / USRA (accumulate) */
8371 case 0x04: /* SRSHR / URSHR (rounding) */
8372 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8373 handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd);
8375 case 0x0a: /* SHL / SLI */
8376 handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd);
8378 case 0x10: /* SHRN */
8379 case 0x11: /* RSHRN / SQRSHRUN */
8381 handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb,
8384 handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd);
8387 case 0x12: /* SQSHRN / UQSHRN */
8388 case 0x13: /* SQRSHRN / UQRSHRN */
8389 handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb,
8392 case 0x14: /* SSHLL / USHLL */
8393 handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd);
8395 case 0x1c: /* SCVTF / UCVTF */
8396 handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,
8399 case 0xc: /* SQSHLU */
8401 unallocated_encoding(s);
8404 handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd);
8406 case 0xe: /* SQSHL, UQSHL */
8407 handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd);
8409 case 0x1f: /* FCVTZS/ FCVTZU */
8410 handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd);
8413 unallocated_encoding(s);
8418 /* Generate code to do a "long" addition or subtraction, ie one done in
8419 * TCGv_i64 on vector lanes twice the width specified by size.
8421 static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res,
8422 TCGv_i64 tcg_op1, TCGv_i64 tcg_op2)
8424 static NeonGenTwo64OpFn * const fns[3][2] = {
8425 { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 },
8426 { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 },
8427 { tcg_gen_add_i64, tcg_gen_sub_i64 },
8429 NeonGenTwo64OpFn *genfn;
8432 genfn = fns[size][is_sub];
8433 genfn(tcg_res, tcg_op1, tcg_op2);
8436 static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
8437 int opcode, int rd, int rn, int rm)
8439 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8440 TCGv_i64 tcg_res[2];
8443 tcg_res[0] = tcg_temp_new_i64();
8444 tcg_res[1] = tcg_temp_new_i64();
8446 /* Does this op do an adding accumulate, a subtracting accumulate,
8447 * or no accumulate at all?
8465 read_vec_element(s, tcg_res[0], rd, 0, MO_64);
8466 read_vec_element(s, tcg_res[1], rd, 1, MO_64);
8469 /* size == 2 means two 32x32->64 operations; this is worth special
8470 * casing because we can generally handle it inline.
8473 for (pass = 0; pass < 2; pass++) {
8474 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
8475 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
8476 TCGv_i64 tcg_passres;
8477 TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);
8479 int elt = pass + is_q * 2;
8481 read_vec_element(s, tcg_op1, rn, elt, memop);
8482 read_vec_element(s, tcg_op2, rm, elt, memop);
8485 tcg_passres = tcg_res[pass];
8487 tcg_passres = tcg_temp_new_i64();
8491 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8492 tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2);
8494 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8495 tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2);
8497 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8498 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8500 TCGv_i64 tcg_tmp1 = tcg_temp_new_i64();
8501 TCGv_i64 tcg_tmp2 = tcg_temp_new_i64();
8503 tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2);
8504 tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1);
8505 tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE,
8507 tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2);
8508 tcg_temp_free_i64(tcg_tmp1);
8509 tcg_temp_free_i64(tcg_tmp2);
8512 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8513 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8514 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8515 tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
8517 case 9: /* SQDMLAL, SQDMLAL2 */
8518 case 11: /* SQDMLSL, SQDMLSL2 */
8519 case 13: /* SQDMULL, SQDMULL2 */
8520 tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
8521 gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env,
8522 tcg_passres, tcg_passres);
8525 g_assert_not_reached();
8528 if (opcode == 9 || opcode == 11) {
8529 /* saturating accumulate ops */
8531 tcg_gen_neg_i64(tcg_passres, tcg_passres);
8533 gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env,
8534 tcg_res[pass], tcg_passres);
8535 } else if (accop > 0) {
8536 tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
8537 } else if (accop < 0) {
8538 tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
8542 tcg_temp_free_i64(tcg_passres);
8545 tcg_temp_free_i64(tcg_op1);
8546 tcg_temp_free_i64(tcg_op2);
8549 /* size 0 or 1, generally helper functions */
8550 for (pass = 0; pass < 2; pass++) {
8551 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
8552 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
8553 TCGv_i64 tcg_passres;
8554 int elt = pass + is_q * 2;
8556 read_vec_element_i32(s, tcg_op1, rn, elt, MO_32);
8557 read_vec_element_i32(s, tcg_op2, rm, elt, MO_32);
8560 tcg_passres = tcg_res[pass];
8562 tcg_passres = tcg_temp_new_i64();
8566 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8567 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8569 TCGv_i64 tcg_op2_64 = tcg_temp_new_i64();
8570 static NeonGenWidenFn * const widenfns[2][2] = {
8571 { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 },
8572 { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 },
8574 NeonGenWidenFn *widenfn = widenfns[size][is_u];
8576 widenfn(tcg_op2_64, tcg_op2);
8577 widenfn(tcg_passres, tcg_op1);
8578 gen_neon_addl(size, (opcode == 2), tcg_passres,
8579 tcg_passres, tcg_op2_64);
8580 tcg_temp_free_i64(tcg_op2_64);
8583 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8584 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8587 gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2);
8589 gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2);
8593 gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2);
8595 gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2);
8599 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8600 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8601 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8604 gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2);
8606 gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2);
8610 gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2);
8612 gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2);
8616 case 9: /* SQDMLAL, SQDMLAL2 */
8617 case 11: /* SQDMLSL, SQDMLSL2 */
8618 case 13: /* SQDMULL, SQDMULL2 */
8620 gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2);
8621 gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env,
8622 tcg_passres, tcg_passres);
8624 case 14: /* PMULL */
8626 gen_helper_neon_mull_p8(tcg_passres, tcg_op1, tcg_op2);
8629 g_assert_not_reached();
8631 tcg_temp_free_i32(tcg_op1);
8632 tcg_temp_free_i32(tcg_op2);
8635 if (opcode == 9 || opcode == 11) {
8636 /* saturating accumulate ops */
8638 gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
8640 gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env,
8644 gen_neon_addl(size, (accop < 0), tcg_res[pass],
8645 tcg_res[pass], tcg_passres);
8647 tcg_temp_free_i64(tcg_passres);
8652 write_vec_element(s, tcg_res[0], rd, 0, MO_64);
8653 write_vec_element(s, tcg_res[1], rd, 1, MO_64);
8654 tcg_temp_free_i64(tcg_res[0]);
8655 tcg_temp_free_i64(tcg_res[1]);
8658 static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,
8659 int opcode, int rd, int rn, int rm)
8661 TCGv_i64 tcg_res[2];
8662 int part = is_q ? 2 : 0;
8665 for (pass = 0; pass < 2; pass++) {
8666 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
8667 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
8668 TCGv_i64 tcg_op2_wide = tcg_temp_new_i64();
8669 static NeonGenWidenFn * const widenfns[3][2] = {
8670 { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 },
8671 { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 },
8672 { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 },
8674 NeonGenWidenFn *widenfn = widenfns[size][is_u];
8676 read_vec_element(s, tcg_op1, rn, pass, MO_64);
8677 read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32);
8678 widenfn(tcg_op2_wide, tcg_op2);
8679 tcg_temp_free_i32(tcg_op2);
8680 tcg_res[pass] = tcg_temp_new_i64();
8681 gen_neon_addl(size, (opcode == 3),
8682 tcg_res[pass], tcg_op1, tcg_op2_wide);
8683 tcg_temp_free_i64(tcg_op1);
8684 tcg_temp_free_i64(tcg_op2_wide);
8687 for (pass = 0; pass < 2; pass++) {
8688 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
8689 tcg_temp_free_i64(tcg_res[pass]);
8693 static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in)
8695 tcg_gen_addi_i64(in, in, 1U << 31);
8696 tcg_gen_extrh_i64_i32(res, in);
8699 static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
8700 int opcode, int rd, int rn, int rm)
8702 TCGv_i32 tcg_res[2];
8703 int part = is_q ? 2 : 0;
8706 for (pass = 0; pass < 2; pass++) {
8707 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
8708 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
8709 TCGv_i64 tcg_wideres = tcg_temp_new_i64();
8710 static NeonGenNarrowFn * const narrowfns[3][2] = {
8711 { gen_helper_neon_narrow_high_u8,
8712 gen_helper_neon_narrow_round_high_u8 },
8713 { gen_helper_neon_narrow_high_u16,
8714 gen_helper_neon_narrow_round_high_u16 },
8715 { tcg_gen_extrh_i64_i32, do_narrow_round_high_u32 },
8717 NeonGenNarrowFn *gennarrow = narrowfns[size][is_u];
8719 read_vec_element(s, tcg_op1, rn, pass, MO_64);
8720 read_vec_element(s, tcg_op2, rm, pass, MO_64);
8722 gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2);
8724 tcg_temp_free_i64(tcg_op1);
8725 tcg_temp_free_i64(tcg_op2);
8727 tcg_res[pass] = tcg_temp_new_i32();
8728 gennarrow(tcg_res[pass], tcg_wideres);
8729 tcg_temp_free_i64(tcg_wideres);
8732 for (pass = 0; pass < 2; pass++) {
8733 write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32);
8734 tcg_temp_free_i32(tcg_res[pass]);
8737 clear_vec_high(s, rd);
8741 static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)
8743 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8744 * is the only three-reg-diff instruction which produces a
8745 * 128-bit wide result from a single operation. However since
8746 * it's possible to calculate the two halves more or less
8747 * separately we just use two helper calls.
8749 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
8750 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
8751 TCGv_i64 tcg_res = tcg_temp_new_i64();
8753 read_vec_element(s, tcg_op1, rn, is_q, MO_64);
8754 read_vec_element(s, tcg_op2, rm, is_q, MO_64);
8755 gen_helper_neon_pmull_64_lo(tcg_res, tcg_op1, tcg_op2);
8756 write_vec_element(s, tcg_res, rd, 0, MO_64);
8757 gen_helper_neon_pmull_64_hi(tcg_res, tcg_op1, tcg_op2);
8758 write_vec_element(s, tcg_res, rd, 1, MO_64);
8760 tcg_temp_free_i64(tcg_op1);
8761 tcg_temp_free_i64(tcg_op2);
8762 tcg_temp_free_i64(tcg_res);
8765 /* C3.6.15 AdvSIMD three different
8766 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8767 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8768 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8769 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8771 static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
8773 /* Instructions in this group fall into three basic classes
8774 * (in each case with the operation working on each element in
8775 * the input vectors):
8776 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8778 * (2) wide 64 x 128 -> 128
8779 * (3) narrowing 128 x 128 -> 64
8780 * Here we do initial decode, catch unallocated cases and
8781 * dispatch to separate functions for each class.
8783 int is_q = extract32(insn, 30, 1);
8784 int is_u = extract32(insn, 29, 1);
8785 int size = extract32(insn, 22, 2);
8786 int opcode = extract32(insn, 12, 4);
8787 int rm = extract32(insn, 16, 5);
8788 int rn = extract32(insn, 5, 5);
8789 int rd = extract32(insn, 0, 5);
8792 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8793 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8794 /* 64 x 128 -> 128 */
8796 unallocated_encoding(s);
8799 if (!fp_access_check(s)) {
8802 handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm);
8804 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8805 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8806 /* 128 x 128 -> 64 */
8808 unallocated_encoding(s);
8811 if (!fp_access_check(s)) {
8814 handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm);
8816 case 14: /* PMULL, PMULL2 */
8817 if (is_u || size == 1 || size == 2) {
8818 unallocated_encoding(s);
8822 if (!arm_dc_feature(s, ARM_FEATURE_V8_PMULL)) {
8823 unallocated_encoding(s);
8826 if (!fp_access_check(s)) {
8829 handle_pmull_64(s, is_q, rd, rn, rm);
8833 case 9: /* SQDMLAL, SQDMLAL2 */
8834 case 11: /* SQDMLSL, SQDMLSL2 */
8835 case 13: /* SQDMULL, SQDMULL2 */
8836 if (is_u || size == 0) {
8837 unallocated_encoding(s);
8841 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8842 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8843 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8844 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8845 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8846 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8847 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
8848 /* 64 x 64 -> 128 */
8850 unallocated_encoding(s);
8854 if (!fp_access_check(s)) {
8858 handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm);
8861 /* opcode 15 not allocated */
8862 unallocated_encoding(s);
8867 /* Logic op (opcode == 3) subgroup of C3.6.16. */
8868 static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
8870 int rd = extract32(insn, 0, 5);
8871 int rn = extract32(insn, 5, 5);
8872 int rm = extract32(insn, 16, 5);
8873 int size = extract32(insn, 22, 2);
8874 bool is_u = extract32(insn, 29, 1);
8875 bool is_q = extract32(insn, 30, 1);
8876 TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
8879 if (!fp_access_check(s)) {
8883 tcg_op1 = tcg_temp_new_i64();
8884 tcg_op2 = tcg_temp_new_i64();
8885 tcg_res[0] = tcg_temp_new_i64();
8886 tcg_res[1] = tcg_temp_new_i64();
8888 for (pass = 0; pass < (is_q ? 2 : 1); pass++) {
8889 read_vec_element(s, tcg_op1, rn, pass, MO_64);
8890 read_vec_element(s, tcg_op2, rm, pass, MO_64);
8895 tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2);
8898 tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2);
8901 tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2);
8904 tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2);
8909 /* B* ops need res loaded to operate on */
8910 read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
8915 tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2);
8917 case 1: /* BSL bitwise select */
8918 tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2);
8919 tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]);
8920 tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1);
8922 case 2: /* BIT, bitwise insert if true */
8923 tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]);
8924 tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2);
8925 tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
8927 case 3: /* BIF, bitwise insert if false */
8928 tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]);
8929 tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2);
8930 tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
8936 write_vec_element(s, tcg_res[0], rd, 0, MO_64);
8938 tcg_gen_movi_i64(tcg_res[1], 0);
8940 write_vec_element(s, tcg_res[1], rd, 1, MO_64);
8942 tcg_temp_free_i64(tcg_op1);
8943 tcg_temp_free_i64(tcg_op2);
8944 tcg_temp_free_i64(tcg_res[0]);
8945 tcg_temp_free_i64(tcg_res[1]);
8948 /* Helper functions for 32 bit comparisons */
8949 static void gen_max_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
8951 tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2);
8954 static void gen_max_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
8956 tcg_gen_movcond_i32(TCG_COND_GEU, res, op1, op2, op1, op2);
8959 static void gen_min_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
8961 tcg_gen_movcond_i32(TCG_COND_LE, res, op1, op2, op1, op2);
8964 static void gen_min_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
8966 tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2);
8969 /* Pairwise op subgroup of C3.6.16.
8971 * This is called directly or via the handle_3same_float for float pairwise
8972 * operations where the opcode and size are calculated differently.
8974 static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
8975 int size, int rn, int rm, int rd)
8980 /* Floating point operations need fpst */
8981 if (opcode >= 0x58) {
8982 fpst = get_fpstatus_ptr();
8984 TCGV_UNUSED_PTR(fpst);
8987 if (!fp_access_check(s)) {
8991 /* These operations work on the concatenated rm:rn, with each pair of
8992 * adjacent elements being operated on to produce an element in the result.
8995 TCGv_i64 tcg_res[2];
8997 for (pass = 0; pass < 2; pass++) {
8998 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
8999 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
9000 int passreg = (pass == 0) ? rn : rm;
9002 read_vec_element(s, tcg_op1, passreg, 0, MO_64);
9003 read_vec_element(s, tcg_op2, passreg, 1, MO_64);
9004 tcg_res[pass] = tcg_temp_new_i64();
9007 case 0x17: /* ADDP */
9008 tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);
9010 case 0x58: /* FMAXNMP */
9011 gen_helper_vfp_maxnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
9013 case 0x5a: /* FADDP */
9014 gen_helper_vfp_addd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
9016 case 0x5e: /* FMAXP */
9017 gen_helper_vfp_maxd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
9019 case 0x78: /* FMINNMP */
9020 gen_helper_vfp_minnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
9022 case 0x7e: /* FMINP */
9023 gen_helper_vfp_mind(tcg_res[pass], tcg_op1, tcg_op2, fpst);
9026 g_assert_not_reached();
9029 tcg_temp_free_i64(tcg_op1);
9030 tcg_temp_free_i64(tcg_op2);
9033 for (pass = 0; pass < 2; pass++) {
9034 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
9035 tcg_temp_free_i64(tcg_res[pass]);
9038 int maxpass = is_q ? 4 : 2;
9039 TCGv_i32 tcg_res[4];
9041 for (pass = 0; pass < maxpass; pass++) {
9042 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
9043 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
9044 NeonGenTwoOpFn *genfn = NULL;
9045 int passreg = pass < (maxpass / 2) ? rn : rm;
9046 int passelt = (is_q && (pass & 1)) ? 2 : 0;
9048 read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32);
9049 read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32);
9050 tcg_res[pass] = tcg_temp_new_i32();
9053 case 0x17: /* ADDP */
9055 static NeonGenTwoOpFn * const fns[3] = {
9056 gen_helper_neon_padd_u8,
9057 gen_helper_neon_padd_u16,
9063 case 0x14: /* SMAXP, UMAXP */
9065 static NeonGenTwoOpFn * const fns[3][2] = {
9066 { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 },
9067 { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 },
9068 { gen_max_s32, gen_max_u32 },
9070 genfn = fns[size][u];
9073 case 0x15: /* SMINP, UMINP */
9075 static NeonGenTwoOpFn * const fns[3][2] = {
9076 { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 },
9077 { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 },
9078 { gen_min_s32, gen_min_u32 },
9080 genfn = fns[size][u];
9083 /* The FP operations are all on single floats (32 bit) */
9084 case 0x58: /* FMAXNMP */
9085 gen_helper_vfp_maxnums(tcg_res[pass], tcg_op1, tcg_op2, fpst);
9087 case 0x5a: /* FADDP */
9088 gen_helper_vfp_adds(tcg_res[pass], tcg_op1, tcg_op2, fpst);
9090 case 0x5e: /* FMAXP */
9091 gen_helper_vfp_maxs(tcg_res[pass], tcg_op1, tcg_op2, fpst);
9093 case 0x78: /* FMINNMP */
9094 gen_helper_vfp_minnums(tcg_res[pass], tcg_op1, tcg_op2, fpst);
9096 case 0x7e: /* FMINP */
9097 gen_helper_vfp_mins(tcg_res[pass], tcg_op1, tcg_op2, fpst);
9100 g_assert_not_reached();
9103 /* FP ops called directly, otherwise call now */
9105 genfn(tcg_res[pass], tcg_op1, tcg_op2);
9108 tcg_temp_free_i32(tcg_op1);
9109 tcg_temp_free_i32(tcg_op2);
9112 for (pass = 0; pass < maxpass; pass++) {
9113 write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);
9114 tcg_temp_free_i32(tcg_res[pass]);
9117 clear_vec_high(s, rd);
9121 if (!TCGV_IS_UNUSED_PTR(fpst)) {
9122 tcg_temp_free_ptr(fpst);
9126 /* Floating point op subgroup of C3.6.16. */
9127 static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
9129 /* For floating point ops, the U, size[1] and opcode bits
9130 * together indicate the operation. size[0] indicates single
9133 int fpopcode = extract32(insn, 11, 5)
9134 | (extract32(insn, 23, 1) << 5)
9135 | (extract32(insn, 29, 1) << 6);
9136 int is_q = extract32(insn, 30, 1);
9137 int size = extract32(insn, 22, 1);
9138 int rm = extract32(insn, 16, 5);
9139 int rn = extract32(insn, 5, 5);
9140 int rd = extract32(insn, 0, 5);
9142 int datasize = is_q ? 128 : 64;
9143 int esize = 32 << size;
9144 int elements = datasize / esize;
9146 if (size == 1 && !is_q) {
9147 unallocated_encoding(s);
9152 case 0x58: /* FMAXNMP */
9153 case 0x5a: /* FADDP */
9154 case 0x5e: /* FMAXP */
9155 case 0x78: /* FMINNMP */
9156 case 0x7e: /* FMINP */
9157 if (size && !is_q) {
9158 unallocated_encoding(s);
9161 handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32,
9164 case 0x1b: /* FMULX */
9165 case 0x1f: /* FRECPS */
9166 case 0x3f: /* FRSQRTS */
9167 case 0x5d: /* FACGE */
9168 case 0x7d: /* FACGT */
9169 case 0x19: /* FMLA */
9170 case 0x39: /* FMLS */
9171 case 0x18: /* FMAXNM */
9172 case 0x1a: /* FADD */
9173 case 0x1c: /* FCMEQ */
9174 case 0x1e: /* FMAX */
9175 case 0x38: /* FMINNM */
9176 case 0x3a: /* FSUB */
9177 case 0x3e: /* FMIN */
9178 case 0x5b: /* FMUL */
9179 case 0x5c: /* FCMGE */
9180 case 0x5f: /* FDIV */
9181 case 0x7a: /* FABD */
9182 case 0x7c: /* FCMGT */
9183 if (!fp_access_check(s)) {
9187 handle_3same_float(s, size, elements, fpopcode, rd, rn, rm);
9190 unallocated_encoding(s);
9195 /* Integer op subgroup of C3.6.16. */
9196 static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
9198 int is_q = extract32(insn, 30, 1);
9199 int u = extract32(insn, 29, 1);
9200 int size = extract32(insn, 22, 2);
9201 int opcode = extract32(insn, 11, 5);
9202 int rm = extract32(insn, 16, 5);
9203 int rn = extract32(insn, 5, 5);
9204 int rd = extract32(insn, 0, 5);
9208 case 0x13: /* MUL, PMUL */
9209 if (u && size != 0) {
9210 unallocated_encoding(s);
9214 case 0x0: /* SHADD, UHADD */
9215 case 0x2: /* SRHADD, URHADD */
9216 case 0x4: /* SHSUB, UHSUB */
9217 case 0xc: /* SMAX, UMAX */
9218 case 0xd: /* SMIN, UMIN */
9219 case 0xe: /* SABD, UABD */
9220 case 0xf: /* SABA, UABA */
9221 case 0x12: /* MLA, MLS */
9223 unallocated_encoding(s);
9227 case 0x16: /* SQDMULH, SQRDMULH */
9228 if (size == 0 || size == 3) {
9229 unallocated_encoding(s);
9234 if (size == 3 && !is_q) {
9235 unallocated_encoding(s);
9241 if (!fp_access_check(s)) {
9247 for (pass = 0; pass < 2; pass++) {
9248 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
9249 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
9250 TCGv_i64 tcg_res = tcg_temp_new_i64();
9252 read_vec_element(s, tcg_op1, rn, pass, MO_64);
9253 read_vec_element(s, tcg_op2, rm, pass, MO_64);
9255 handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2);
9257 write_vec_element(s, tcg_res, rd, pass, MO_64);
9259 tcg_temp_free_i64(tcg_res);
9260 tcg_temp_free_i64(tcg_op1);
9261 tcg_temp_free_i64(tcg_op2);
9264 for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
9265 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
9266 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
9267 TCGv_i32 tcg_res = tcg_temp_new_i32();
9268 NeonGenTwoOpFn *genfn = NULL;
9269 NeonGenTwoOpEnvFn *genenvfn = NULL;
9271 read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
9272 read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
9275 case 0x0: /* SHADD, UHADD */
9277 static NeonGenTwoOpFn * const fns[3][2] = {
9278 { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 },
9279 { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 },
9280 { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 },
9282 genfn = fns[size][u];
9285 case 0x1: /* SQADD, UQADD */
9287 static NeonGenTwoOpEnvFn * const fns[3][2] = {
9288 { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 },
9289 { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 },
9290 { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 },
9292 genenvfn = fns[size][u];
9295 case 0x2: /* SRHADD, URHADD */
9297 static NeonGenTwoOpFn * const fns[3][2] = {
9298 { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 },
9299 { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 },
9300 { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 },
9302 genfn = fns[size][u];
9305 case 0x4: /* SHSUB, UHSUB */
9307 static NeonGenTwoOpFn * const fns[3][2] = {
9308 { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 },
9309 { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 },
9310 { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 },
9312 genfn = fns[size][u];
9315 case 0x5: /* SQSUB, UQSUB */
9317 static NeonGenTwoOpEnvFn * const fns[3][2] = {
9318 { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 },
9319 { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 },
9320 { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 },
9322 genenvfn = fns[size][u];
9325 case 0x6: /* CMGT, CMHI */
9327 static NeonGenTwoOpFn * const fns[3][2] = {
9328 { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_u8 },
9329 { gen_helper_neon_cgt_s16, gen_helper_neon_cgt_u16 },
9330 { gen_helper_neon_cgt_s32, gen_helper_neon_cgt_u32 },
9332 genfn = fns[size][u];
9335 case 0x7: /* CMGE, CMHS */
9337 static NeonGenTwoOpFn * const fns[3][2] = {
9338 { gen_helper_neon_cge_s8, gen_helper_neon_cge_u8 },
9339 { gen_helper_neon_cge_s16, gen_helper_neon_cge_u16 },
9340 { gen_helper_neon_cge_s32, gen_helper_neon_cge_u32 },
9342 genfn = fns[size][u];
9345 case 0x8: /* SSHL, USHL */
9347 static NeonGenTwoOpFn * const fns[3][2] = {
9348 { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 },
9349 { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 },
9350 { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 },
9352 genfn = fns[size][u];
9355 case 0x9: /* SQSHL, UQSHL */
9357 static NeonGenTwoOpEnvFn * const fns[3][2] = {
9358 { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 },
9359 { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 },
9360 { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 },
9362 genenvfn = fns[size][u];
9365 case 0xa: /* SRSHL, URSHL */
9367 static NeonGenTwoOpFn * const fns[3][2] = {
9368 { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 },
9369 { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 },
9370 { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 },
9372 genfn = fns[size][u];
9375 case 0xb: /* SQRSHL, UQRSHL */
9377 static NeonGenTwoOpEnvFn * const fns[3][2] = {
9378 { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 },
9379 { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 },
9380 { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 },
9382 genenvfn = fns[size][u];
9385 case 0xc: /* SMAX, UMAX */
9387 static NeonGenTwoOpFn * const fns[3][2] = {
9388 { gen_helper_neon_max_s8, gen_helper_neon_max_u8 },
9389 { gen_helper_neon_max_s16, gen_helper_neon_max_u16 },
9390 { gen_max_s32, gen_max_u32 },
9392 genfn = fns[size][u];
9396 case 0xd: /* SMIN, UMIN */
9398 static NeonGenTwoOpFn * const fns[3][2] = {
9399 { gen_helper_neon_min_s8, gen_helper_neon_min_u8 },
9400 { gen_helper_neon_min_s16, gen_helper_neon_min_u16 },
9401 { gen_min_s32, gen_min_u32 },
9403 genfn = fns[size][u];
9406 case 0xe: /* SABD, UABD */
9407 case 0xf: /* SABA, UABA */
9409 static NeonGenTwoOpFn * const fns[3][2] = {
9410 { gen_helper_neon_abd_s8, gen_helper_neon_abd_u8 },
9411 { gen_helper_neon_abd_s16, gen_helper_neon_abd_u16 },
9412 { gen_helper_neon_abd_s32, gen_helper_neon_abd_u32 },
9414 genfn = fns[size][u];
9417 case 0x10: /* ADD, SUB */
9419 static NeonGenTwoOpFn * const fns[3][2] = {
9420 { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },
9421 { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
9422 { tcg_gen_add_i32, tcg_gen_sub_i32 },
9424 genfn = fns[size][u];
9427 case 0x11: /* CMTST, CMEQ */
9429 static NeonGenTwoOpFn * const fns[3][2] = {
9430 { gen_helper_neon_tst_u8, gen_helper_neon_ceq_u8 },
9431 { gen_helper_neon_tst_u16, gen_helper_neon_ceq_u16 },
9432 { gen_helper_neon_tst_u32, gen_helper_neon_ceq_u32 },
9434 genfn = fns[size][u];
9437 case 0x13: /* MUL, PMUL */
9441 genfn = gen_helper_neon_mul_p8;
9444 /* fall through : MUL */
9445 case 0x12: /* MLA, MLS */
9447 static NeonGenTwoOpFn * const fns[3] = {
9448 gen_helper_neon_mul_u8,
9449 gen_helper_neon_mul_u16,
9455 case 0x16: /* SQDMULH, SQRDMULH */
9457 static NeonGenTwoOpEnvFn * const fns[2][2] = {
9458 { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 },
9459 { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 },
9461 assert(size == 1 || size == 2);
9462 genenvfn = fns[size - 1][u];
9466 g_assert_not_reached();
9470 genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2);
9472 genfn(tcg_res, tcg_op1, tcg_op2);
9475 if (opcode == 0xf || opcode == 0x12) {
9476 /* SABA, UABA, MLA, MLS: accumulating ops */
9477 static NeonGenTwoOpFn * const fns[3][2] = {
9478 { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },
9479 { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
9480 { tcg_gen_add_i32, tcg_gen_sub_i32 },
9482 bool is_sub = (opcode == 0x12 && u); /* MLS */
9484 genfn = fns[size][is_sub];
9485 read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
9486 genfn(tcg_res, tcg_op1, tcg_res);
9489 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
9491 tcg_temp_free_i32(tcg_res);
9492 tcg_temp_free_i32(tcg_op1);
9493 tcg_temp_free_i32(tcg_op2);
9498 clear_vec_high(s, rd);
9502 /* C3.6.16 AdvSIMD three same
9503 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9504 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9505 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9506 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9508 static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
9510 int opcode = extract32(insn, 11, 5);
9513 case 0x3: /* logic ops */
9514 disas_simd_3same_logic(s, insn);
9516 case 0x17: /* ADDP */
9517 case 0x14: /* SMAXP, UMAXP */
9518 case 0x15: /* SMINP, UMINP */
9520 /* Pairwise operations */
9521 int is_q = extract32(insn, 30, 1);
9522 int u = extract32(insn, 29, 1);
9523 int size = extract32(insn, 22, 2);
9524 int rm = extract32(insn, 16, 5);
9525 int rn = extract32(insn, 5, 5);
9526 int rd = extract32(insn, 0, 5);
9527 if (opcode == 0x17) {
9528 if (u || (size == 3 && !is_q)) {
9529 unallocated_encoding(s);
9534 unallocated_encoding(s);
9538 handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd);
9542 /* floating point ops, sz[1] and U are part of opcode */
9543 disas_simd_3same_float(s, insn);
9546 disas_simd_3same_int(s, insn);
9551 static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
9552 int size, int rn, int rd)
9554 /* Handle 2-reg-misc ops which are widening (so each size element
9555 * in the source becomes a 2*size element in the destination.
9556 * The only instruction like this is FCVTL.
9561 /* 32 -> 64 bit fp conversion */
9562 TCGv_i64 tcg_res[2];
9563 int srcelt = is_q ? 2 : 0;
9565 for (pass = 0; pass < 2; pass++) {
9566 TCGv_i32 tcg_op = tcg_temp_new_i32();
9567 tcg_res[pass] = tcg_temp_new_i64();
9569 read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32);
9570 gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env);
9571 tcg_temp_free_i32(tcg_op);
9573 for (pass = 0; pass < 2; pass++) {
9574 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
9575 tcg_temp_free_i64(tcg_res[pass]);
9578 /* 16 -> 32 bit fp conversion */
9579 int srcelt = is_q ? 4 : 0;
9580 TCGv_i32 tcg_res[4];
9582 for (pass = 0; pass < 4; pass++) {
9583 tcg_res[pass] = tcg_temp_new_i32();
9585 read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16);
9586 gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass],
9589 for (pass = 0; pass < 4; pass++) {
9590 write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);
9591 tcg_temp_free_i32(tcg_res[pass]);
9596 static void handle_rev(DisasContext *s, int opcode, bool u,
9597 bool is_q, int size, int rn, int rd)
9599 int op = (opcode << 1) | u;
9600 int opsz = op + size;
9601 int grp_size = 3 - opsz;
9602 int dsize = is_q ? 128 : 64;
9606 unallocated_encoding(s);
9610 if (!fp_access_check(s)) {
9615 /* Special case bytes, use bswap op on each group of elements */
9616 int groups = dsize / (8 << grp_size);
9618 for (i = 0; i < groups; i++) {
9619 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
9621 read_vec_element(s, tcg_tmp, rn, i, grp_size);
9624 tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
9627 tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
9630 tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp);
9633 g_assert_not_reached();
9635 write_vec_element(s, tcg_tmp, rd, i, grp_size);
9636 tcg_temp_free_i64(tcg_tmp);
9639 clear_vec_high(s, rd);
9642 int revmask = (1 << grp_size) - 1;
9643 int esize = 8 << size;
9644 int elements = dsize / esize;
9645 TCGv_i64 tcg_rn = tcg_temp_new_i64();
9646 TCGv_i64 tcg_rd = tcg_const_i64(0);
9647 TCGv_i64 tcg_rd_hi = tcg_const_i64(0);
9649 for (i = 0; i < elements; i++) {
9650 int e_rev = (i & 0xf) ^ revmask;
9651 int off = e_rev * esize;
9652 read_vec_element(s, tcg_rn, rn, i, size);
9654 tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi,
9655 tcg_rn, off - 64, esize);
9657 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize);
9660 write_vec_element(s, tcg_rd, rd, 0, MO_64);
9661 write_vec_element(s, tcg_rd_hi, rd, 1, MO_64);
9663 tcg_temp_free_i64(tcg_rd_hi);
9664 tcg_temp_free_i64(tcg_rd);
9665 tcg_temp_free_i64(tcg_rn);
9669 static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
9670 bool is_q, int size, int rn, int rd)
9672 /* Implement the pairwise operations from 2-misc:
9673 * SADDLP, UADDLP, SADALP, UADALP.
9674 * These all add pairs of elements in the input to produce a
9675 * double-width result element in the output (possibly accumulating).
9677 bool accum = (opcode == 0x6);
9678 int maxpass = is_q ? 2 : 1;
9680 TCGv_i64 tcg_res[2];
9683 /* 32 + 32 -> 64 op */
9684 TCGMemOp memop = size + (u ? 0 : MO_SIGN);
9686 for (pass = 0; pass < maxpass; pass++) {
9687 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
9688 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
9690 tcg_res[pass] = tcg_temp_new_i64();
9692 read_vec_element(s, tcg_op1, rn, pass * 2, memop);
9693 read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop);
9694 tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);
9696 read_vec_element(s, tcg_op1, rd, pass, MO_64);
9697 tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
9700 tcg_temp_free_i64(tcg_op1);
9701 tcg_temp_free_i64(tcg_op2);
9704 for (pass = 0; pass < maxpass; pass++) {
9705 TCGv_i64 tcg_op = tcg_temp_new_i64();
9706 NeonGenOneOpFn *genfn;
9707 static NeonGenOneOpFn * const fns[2][2] = {
9708 { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 },
9709 { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 },
9712 genfn = fns[size][u];
9714 tcg_res[pass] = tcg_temp_new_i64();
9716 read_vec_element(s, tcg_op, rn, pass, MO_64);
9717 genfn(tcg_res[pass], tcg_op);
9720 read_vec_element(s, tcg_op, rd, pass, MO_64);
9722 gen_helper_neon_addl_u16(tcg_res[pass],
9723 tcg_res[pass], tcg_op);
9725 gen_helper_neon_addl_u32(tcg_res[pass],
9726 tcg_res[pass], tcg_op);
9729 tcg_temp_free_i64(tcg_op);
9733 tcg_res[1] = tcg_const_i64(0);
9735 for (pass = 0; pass < 2; pass++) {
9736 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
9737 tcg_temp_free_i64(tcg_res[pass]);
9741 static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
9743 /* Implement SHLL and SHLL2 */
9745 int part = is_q ? 2 : 0;
9746 TCGv_i64 tcg_res[2];
9748 for (pass = 0; pass < 2; pass++) {
9749 static NeonGenWidenFn * const widenfns[3] = {
9750 gen_helper_neon_widen_u8,
9751 gen_helper_neon_widen_u16,
9752 tcg_gen_extu_i32_i64,
9754 NeonGenWidenFn *widenfn = widenfns[size];
9755 TCGv_i32 tcg_op = tcg_temp_new_i32();
9757 read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32);
9758 tcg_res[pass] = tcg_temp_new_i64();
9759 widenfn(tcg_res[pass], tcg_op);
9760 tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size);
9762 tcg_temp_free_i32(tcg_op);
9765 for (pass = 0; pass < 2; pass++) {
9766 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
9767 tcg_temp_free_i64(tcg_res[pass]);
9771 /* C3.6.17 AdvSIMD two reg misc
9772 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9773 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9774 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9775 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9777 static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
9779 int size = extract32(insn, 22, 2);
9780 int opcode = extract32(insn, 12, 5);
9781 bool u = extract32(insn, 29, 1);
9782 bool is_q = extract32(insn, 30, 1);
9783 int rn = extract32(insn, 5, 5);
9784 int rd = extract32(insn, 0, 5);
9785 bool need_fpstatus = false;
9786 bool need_rmode = false;
9789 TCGv_ptr tcg_fpstatus;
9792 case 0x0: /* REV64, REV32 */
9793 case 0x1: /* REV16 */
9794 handle_rev(s, opcode, u, is_q, size, rn, rd);
9796 case 0x5: /* CNT, NOT, RBIT */
9797 if (u && size == 0) {
9798 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9801 } else if (u && size == 1) {
9804 } else if (!u && size == 0) {
9808 unallocated_encoding(s);
9810 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9811 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9813 unallocated_encoding(s);
9816 if (!fp_access_check(s)) {
9820 handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd);
9822 case 0x4: /* CLS, CLZ */
9824 unallocated_encoding(s);
9828 case 0x2: /* SADDLP, UADDLP */
9829 case 0x6: /* SADALP, UADALP */
9831 unallocated_encoding(s);
9834 if (!fp_access_check(s)) {
9837 handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd);
9839 case 0x13: /* SHLL, SHLL2 */
9840 if (u == 0 || size == 3) {
9841 unallocated_encoding(s);
9844 if (!fp_access_check(s)) {
9847 handle_shll(s, is_q, size, rn, rd);
9849 case 0xa: /* CMLT */
9851 unallocated_encoding(s);
9855 case 0x8: /* CMGT, CMGE */
9856 case 0x9: /* CMEQ, CMLE */
9857 case 0xb: /* ABS, NEG */
9858 if (size == 3 && !is_q) {
9859 unallocated_encoding(s);
9863 case 0x3: /* SUQADD, USQADD */
9864 if (size == 3 && !is_q) {
9865 unallocated_encoding(s);
9868 if (!fp_access_check(s)) {
9871 handle_2misc_satacc(s, false, u, is_q, size, rn, rd);
9873 case 0x7: /* SQABS, SQNEG */
9874 if (size == 3 && !is_q) {
9875 unallocated_encoding(s);
9883 /* Floating point: U, size[1] and opcode indicate operation;
9884 * size[0] indicates single or double precision.
9886 int is_double = extract32(size, 0, 1);
9887 opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
9888 size = is_double ? 3 : 2;
9890 case 0x2f: /* FABS */
9891 case 0x6f: /* FNEG */
9892 if (size == 3 && !is_q) {
9893 unallocated_encoding(s);
9897 case 0x1d: /* SCVTF */
9898 case 0x5d: /* UCVTF */
9900 bool is_signed = (opcode == 0x1d) ? true : false;
9901 int elements = is_double ? 2 : is_q ? 4 : 2;
9902 if (is_double && !is_q) {
9903 unallocated_encoding(s);
9906 if (!fp_access_check(s)) {
9909 handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size);
9912 case 0x2c: /* FCMGT (zero) */
9913 case 0x2d: /* FCMEQ (zero) */
9914 case 0x2e: /* FCMLT (zero) */
9915 case 0x6c: /* FCMGE (zero) */
9916 case 0x6d: /* FCMLE (zero) */
9917 if (size == 3 && !is_q) {
9918 unallocated_encoding(s);
9921 handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
9923 case 0x7f: /* FSQRT */
9924 if (size == 3 && !is_q) {
9925 unallocated_encoding(s);
9929 case 0x1a: /* FCVTNS */
9930 case 0x1b: /* FCVTMS */
9931 case 0x3a: /* FCVTPS */
9932 case 0x3b: /* FCVTZS */
9933 case 0x5a: /* FCVTNU */
9934 case 0x5b: /* FCVTMU */
9935 case 0x7a: /* FCVTPU */
9936 case 0x7b: /* FCVTZU */
9937 need_fpstatus = true;
9939 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
9940 if (size == 3 && !is_q) {
9941 unallocated_encoding(s);
9945 case 0x5c: /* FCVTAU */
9946 case 0x1c: /* FCVTAS */
9947 need_fpstatus = true;
9949 rmode = FPROUNDING_TIEAWAY;
9950 if (size == 3 && !is_q) {
9951 unallocated_encoding(s);
9955 case 0x3c: /* URECPE */
9957 unallocated_encoding(s);
9961 case 0x3d: /* FRECPE */
9962 case 0x7d: /* FRSQRTE */
9963 if (size == 3 && !is_q) {
9964 unallocated_encoding(s);
9967 if (!fp_access_check(s)) {
9970 handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd);
9972 case 0x56: /* FCVTXN, FCVTXN2 */
9974 unallocated_encoding(s);
9978 case 0x16: /* FCVTN, FCVTN2 */
9979 /* handle_2misc_narrow does a 2*size -> size operation, but these
9980 * instructions encode the source size rather than dest size.
9982 if (!fp_access_check(s)) {
9985 handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd);
9987 case 0x17: /* FCVTL, FCVTL2 */
9988 if (!fp_access_check(s)) {
9991 handle_2misc_widening(s, opcode, is_q, size, rn, rd);
9993 case 0x18: /* FRINTN */
9994 case 0x19: /* FRINTM */
9995 case 0x38: /* FRINTP */
9996 case 0x39: /* FRINTZ */
9998 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
10000 case 0x59: /* FRINTX */
10001 case 0x79: /* FRINTI */
10002 need_fpstatus = true;
10003 if (size == 3 && !is_q) {
10004 unallocated_encoding(s);
10008 case 0x58: /* FRINTA */
10010 rmode = FPROUNDING_TIEAWAY;
10011 need_fpstatus = true;
10012 if (size == 3 && !is_q) {
10013 unallocated_encoding(s);
10017 case 0x7c: /* URSQRTE */
10019 unallocated_encoding(s);
10022 need_fpstatus = true;
10025 unallocated_encoding(s);
10031 unallocated_encoding(s);
10035 if (!fp_access_check(s)) {
10039 if (need_fpstatus) {
10040 tcg_fpstatus = get_fpstatus_ptr();
10042 TCGV_UNUSED_PTR(tcg_fpstatus);
10045 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
10046 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
10048 TCGV_UNUSED_I32(tcg_rmode);
10052 /* All 64-bit element operations can be shared with scalar 2misc */
10055 for (pass = 0; pass < (is_q ? 2 : 1); pass++) {
10056 TCGv_i64 tcg_op = tcg_temp_new_i64();
10057 TCGv_i64 tcg_res = tcg_temp_new_i64();
10059 read_vec_element(s, tcg_op, rn, pass, MO_64);
10061 handle_2misc_64(s, opcode, u, tcg_res, tcg_op,
10062 tcg_rmode, tcg_fpstatus);
10064 write_vec_element(s, tcg_res, rd, pass, MO_64);
10066 tcg_temp_free_i64(tcg_res);
10067 tcg_temp_free_i64(tcg_op);
10072 for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
10073 TCGv_i32 tcg_op = tcg_temp_new_i32();
10074 TCGv_i32 tcg_res = tcg_temp_new_i32();
10077 read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
10080 /* Special cases for 32 bit elements */
10082 case 0xa: /* CMLT */
10083 /* 32 bit integer comparison against zero, result is
10084 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10087 cond = TCG_COND_LT;
10089 tcg_gen_setcondi_i32(cond, tcg_res, tcg_op, 0);
10090 tcg_gen_neg_i32(tcg_res, tcg_res);
10092 case 0x8: /* CMGT, CMGE */
10093 cond = u ? TCG_COND_GE : TCG_COND_GT;
10095 case 0x9: /* CMEQ, CMLE */
10096 cond = u ? TCG_COND_LE : TCG_COND_EQ;
10098 case 0x4: /* CLS */
10100 gen_helper_clz32(tcg_res, tcg_op);
10102 gen_helper_cls32(tcg_res, tcg_op);
10105 case 0x7: /* SQABS, SQNEG */
10107 gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op);
10109 gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op);
10112 case 0xb: /* ABS, NEG */
10114 tcg_gen_neg_i32(tcg_res, tcg_op);
10116 TCGv_i32 tcg_zero = tcg_const_i32(0);
10117 tcg_gen_neg_i32(tcg_res, tcg_op);
10118 tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op,
10119 tcg_zero, tcg_op, tcg_res);
10120 tcg_temp_free_i32(tcg_zero);
10123 case 0x2f: /* FABS */
10124 gen_helper_vfp_abss(tcg_res, tcg_op);
10126 case 0x6f: /* FNEG */
10127 gen_helper_vfp_negs(tcg_res, tcg_op);
10129 case 0x7f: /* FSQRT */
10130 gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
10132 case 0x1a: /* FCVTNS */
10133 case 0x1b: /* FCVTMS */
10134 case 0x1c: /* FCVTAS */
10135 case 0x3a: /* FCVTPS */
10136 case 0x3b: /* FCVTZS */
10138 TCGv_i32 tcg_shift = tcg_const_i32(0);
10139 gen_helper_vfp_tosls(tcg_res, tcg_op,
10140 tcg_shift, tcg_fpstatus);
10141 tcg_temp_free_i32(tcg_shift);
10144 case 0x5a: /* FCVTNU */
10145 case 0x5b: /* FCVTMU */
10146 case 0x5c: /* FCVTAU */
10147 case 0x7a: /* FCVTPU */
10148 case 0x7b: /* FCVTZU */
10150 TCGv_i32 tcg_shift = tcg_const_i32(0);
10151 gen_helper_vfp_touls(tcg_res, tcg_op,
10152 tcg_shift, tcg_fpstatus);
10153 tcg_temp_free_i32(tcg_shift);
10156 case 0x18: /* FRINTN */
10157 case 0x19: /* FRINTM */
10158 case 0x38: /* FRINTP */
10159 case 0x39: /* FRINTZ */
10160 case 0x58: /* FRINTA */
10161 case 0x79: /* FRINTI */
10162 gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus);
10164 case 0x59: /* FRINTX */
10165 gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus);
10167 case 0x7c: /* URSQRTE */
10168 gen_helper_rsqrte_u32(tcg_res, tcg_op, tcg_fpstatus);
10171 g_assert_not_reached();
10174 /* Use helpers for 8 and 16 bit elements */
10176 case 0x5: /* CNT, RBIT */
10177 /* For these two insns size is part of the opcode specifier
10178 * (handled earlier); they always operate on byte elements.
10181 gen_helper_neon_rbit_u8(tcg_res, tcg_op);
10183 gen_helper_neon_cnt_u8(tcg_res, tcg_op);
10186 case 0x7: /* SQABS, SQNEG */
10188 NeonGenOneOpEnvFn *genfn;
10189 static NeonGenOneOpEnvFn * const fns[2][2] = {
10190 { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
10191 { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
10193 genfn = fns[size][u];
10194 genfn(tcg_res, cpu_env, tcg_op);
10197 case 0x8: /* CMGT, CMGE */
10198 case 0x9: /* CMEQ, CMLE */
10199 case 0xa: /* CMLT */
10201 static NeonGenTwoOpFn * const fns[3][2] = {
10202 { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_s16 },
10203 { gen_helper_neon_cge_s8, gen_helper_neon_cge_s16 },
10204 { gen_helper_neon_ceq_u8, gen_helper_neon_ceq_u16 },
10206 NeonGenTwoOpFn *genfn;
10209 TCGv_i32 tcg_zero = tcg_const_i32(0);
10211 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10212 comp = (opcode - 0x8) * 2 + u;
10213 /* ...but LE, LT are implemented as reverse GE, GT */
10214 reverse = (comp > 2);
10218 genfn = fns[comp][size];
10220 genfn(tcg_res, tcg_zero, tcg_op);
10222 genfn(tcg_res, tcg_op, tcg_zero);
10224 tcg_temp_free_i32(tcg_zero);
10227 case 0xb: /* ABS, NEG */
10229 TCGv_i32 tcg_zero = tcg_const_i32(0);
10231 gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg_op);
10233 gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_op);
10235 tcg_temp_free_i32(tcg_zero);
10238 gen_helper_neon_abs_s16(tcg_res, tcg_op);
10240 gen_helper_neon_abs_s8(tcg_res, tcg_op);
10244 case 0x4: /* CLS, CLZ */
10247 gen_helper_neon_clz_u8(tcg_res, tcg_op);
10249 gen_helper_neon_clz_u16(tcg_res, tcg_op);
10253 gen_helper_neon_cls_s8(tcg_res, tcg_op);
10255 gen_helper_neon_cls_s16(tcg_res, tcg_op);
10260 g_assert_not_reached();
10264 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
10266 tcg_temp_free_i32(tcg_res);
10267 tcg_temp_free_i32(tcg_op);
10271 clear_vec_high(s, rd);
10275 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
10276 tcg_temp_free_i32(tcg_rmode);
10278 if (need_fpstatus) {
10279 tcg_temp_free_ptr(tcg_fpstatus);
10283 /* C3.6.13 AdvSIMD scalar x indexed element
10284 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10285 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10286 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10287 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10288 * C3.6.18 AdvSIMD vector x indexed element
10289 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10290 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10291 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10292 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10294 static void disas_simd_indexed(DisasContext *s, uint32_t insn)
10296 /* This encoding has two kinds of instruction:
10297 * normal, where we perform elt x idxelt => elt for each
10298 * element in the vector
10299 * long, where we perform elt x idxelt and generate a result of
10300 * double the width of the input element
10301 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10303 bool is_scalar = extract32(insn, 28, 1);
10304 bool is_q = extract32(insn, 30, 1);
10305 bool u = extract32(insn, 29, 1);
10306 int size = extract32(insn, 22, 2);
10307 int l = extract32(insn, 21, 1);
10308 int m = extract32(insn, 20, 1);
10309 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10310 int rm = extract32(insn, 16, 4);
10311 int opcode = extract32(insn, 12, 4);
10312 int h = extract32(insn, 11, 1);
10313 int rn = extract32(insn, 5, 5);
10314 int rd = extract32(insn, 0, 5);
10315 bool is_long = false;
10316 bool is_fp = false;
10321 case 0x0: /* MLA */
10322 case 0x4: /* MLS */
10323 if (!u || is_scalar) {
10324 unallocated_encoding(s);
10328 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10329 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10330 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10332 unallocated_encoding(s);
10337 case 0x3: /* SQDMLAL, SQDMLAL2 */
10338 case 0x7: /* SQDMLSL, SQDMLSL2 */
10339 case 0xb: /* SQDMULL, SQDMULL2 */
10342 case 0xc: /* SQDMULH */
10343 case 0xd: /* SQRDMULH */
10345 unallocated_encoding(s);
10349 case 0x8: /* MUL */
10350 if (u || is_scalar) {
10351 unallocated_encoding(s);
10355 case 0x1: /* FMLA */
10356 case 0x5: /* FMLS */
10358 unallocated_encoding(s);
10362 case 0x9: /* FMUL, FMULX */
10363 if (!extract32(size, 1, 1)) {
10364 unallocated_encoding(s);
10370 unallocated_encoding(s);
10375 /* low bit of size indicates single/double */
10376 size = extract32(size, 0, 1) ? 3 : 2;
10378 index = h << 1 | l;
10381 unallocated_encoding(s);
10390 index = h << 2 | l << 1 | m;
10393 index = h << 1 | l;
10397 unallocated_encoding(s);
10402 if (!fp_access_check(s)) {
10407 fpst = get_fpstatus_ptr();
10409 TCGV_UNUSED_PTR(fpst);
10413 TCGv_i64 tcg_idx = tcg_temp_new_i64();
10416 assert(is_fp && is_q && !is_long);
10418 read_vec_element(s, tcg_idx, rm, index, MO_64);
10420 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
10421 TCGv_i64 tcg_op = tcg_temp_new_i64();
10422 TCGv_i64 tcg_res = tcg_temp_new_i64();
10424 read_vec_element(s, tcg_op, rn, pass, MO_64);
10427 case 0x5: /* FMLS */
10428 /* As usual for ARM, separate negation for fused multiply-add */
10429 gen_helper_vfp_negd(tcg_op, tcg_op);
10431 case 0x1: /* FMLA */
10432 read_vec_element(s, tcg_res, rd, pass, MO_64);
10433 gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
10435 case 0x9: /* FMUL, FMULX */
10437 gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst);
10439 gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst);
10443 g_assert_not_reached();
10446 write_vec_element(s, tcg_res, rd, pass, MO_64);
10447 tcg_temp_free_i64(tcg_op);
10448 tcg_temp_free_i64(tcg_res);
10452 clear_vec_high(s, rd);
10455 tcg_temp_free_i64(tcg_idx);
10456 } else if (!is_long) {
10457 /* 32 bit floating point, or 16 or 32 bit integer.
10458 * For the 16 bit scalar case we use the usual Neon helpers and
10459 * rely on the fact that 0 op 0 == 0 with no side effects.
10461 TCGv_i32 tcg_idx = tcg_temp_new_i32();
10462 int pass, maxpasses;
10467 maxpasses = is_q ? 4 : 2;
10470 read_vec_element_i32(s, tcg_idx, rm, index, size);
10472 if (size == 1 && !is_scalar) {
10473 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10474 * the index into both halves of the 32 bit tcg_idx and then use
10475 * the usual Neon helpers.
10477 tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
10480 for (pass = 0; pass < maxpasses; pass++) {
10481 TCGv_i32 tcg_op = tcg_temp_new_i32();
10482 TCGv_i32 tcg_res = tcg_temp_new_i32();
10484 read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32);
10487 case 0x0: /* MLA */
10488 case 0x4: /* MLS */
10489 case 0x8: /* MUL */
10491 static NeonGenTwoOpFn * const fns[2][2] = {
10492 { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
10493 { tcg_gen_add_i32, tcg_gen_sub_i32 },
10495 NeonGenTwoOpFn *genfn;
10496 bool is_sub = opcode == 0x4;
10499 gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx);
10501 tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx);
10503 if (opcode == 0x8) {
10506 read_vec_element_i32(s, tcg_op, rd, pass, MO_32);
10507 genfn = fns[size - 1][is_sub];
10508 genfn(tcg_res, tcg_op, tcg_res);
10511 case 0x5: /* FMLS */
10512 /* As usual for ARM, separate negation for fused multiply-add */
10513 gen_helper_vfp_negs(tcg_op, tcg_op);
10515 case 0x1: /* FMLA */
10516 read_vec_element_i32(s, tcg_res, rd, pass, MO_32);
10517 gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
10519 case 0x9: /* FMUL, FMULX */
10521 gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
10523 gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
10526 case 0xc: /* SQDMULH */
10528 gen_helper_neon_qdmulh_s16(tcg_res, cpu_env,
10531 gen_helper_neon_qdmulh_s32(tcg_res, cpu_env,
10535 case 0xd: /* SQRDMULH */
10537 gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env,
10540 gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env,
10545 g_assert_not_reached();
10549 write_fp_sreg(s, rd, tcg_res);
10551 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
10554 tcg_temp_free_i32(tcg_op);
10555 tcg_temp_free_i32(tcg_res);
10558 tcg_temp_free_i32(tcg_idx);
10561 clear_vec_high(s, rd);
10564 /* long ops: 16x16->32 or 32x32->64 */
10565 TCGv_i64 tcg_res[2];
10567 bool satop = extract32(opcode, 0, 1);
10568 TCGMemOp memop = MO_32;
10575 TCGv_i64 tcg_idx = tcg_temp_new_i64();
10577 read_vec_element(s, tcg_idx, rm, index, memop);
10579 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
10580 TCGv_i64 tcg_op = tcg_temp_new_i64();
10581 TCGv_i64 tcg_passres;
10587 passelt = pass + (is_q * 2);
10590 read_vec_element(s, tcg_op, rn, passelt, memop);
10592 tcg_res[pass] = tcg_temp_new_i64();
10594 if (opcode == 0xa || opcode == 0xb) {
10595 /* Non-accumulating ops */
10596 tcg_passres = tcg_res[pass];
10598 tcg_passres = tcg_temp_new_i64();
10601 tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx);
10602 tcg_temp_free_i64(tcg_op);
10605 /* saturating, doubling */
10606 gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env,
10607 tcg_passres, tcg_passres);
10610 if (opcode == 0xa || opcode == 0xb) {
10614 /* Accumulating op: handle accumulate step */
10615 read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
10618 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10619 tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
10621 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10622 tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
10624 case 0x7: /* SQDMLSL, SQDMLSL2 */
10625 tcg_gen_neg_i64(tcg_passres, tcg_passres);
10627 case 0x3: /* SQDMLAL, SQDMLAL2 */
10628 gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env,
10633 g_assert_not_reached();
10635 tcg_temp_free_i64(tcg_passres);
10637 tcg_temp_free_i64(tcg_idx);
10640 clear_vec_high(s, rd);
10643 TCGv_i32 tcg_idx = tcg_temp_new_i32();
10646 read_vec_element_i32(s, tcg_idx, rm, index, size);
10649 /* The simplest way to handle the 16x16 indexed ops is to
10650 * duplicate the index into both halves of the 32 bit tcg_idx
10651 * and then use the usual Neon helpers.
10653 tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
10656 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
10657 TCGv_i32 tcg_op = tcg_temp_new_i32();
10658 TCGv_i64 tcg_passres;
10661 read_vec_element_i32(s, tcg_op, rn, pass, size);
10663 read_vec_element_i32(s, tcg_op, rn,
10664 pass + (is_q * 2), MO_32);
10667 tcg_res[pass] = tcg_temp_new_i64();
10669 if (opcode == 0xa || opcode == 0xb) {
10670 /* Non-accumulating ops */
10671 tcg_passres = tcg_res[pass];
10673 tcg_passres = tcg_temp_new_i64();
10676 if (memop & MO_SIGN) {
10677 gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx);
10679 gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx);
10682 gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env,
10683 tcg_passres, tcg_passres);
10685 tcg_temp_free_i32(tcg_op);
10687 if (opcode == 0xa || opcode == 0xb) {
10691 /* Accumulating op: handle accumulate step */
10692 read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
10695 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10696 gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass],
10699 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10700 gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass],
10703 case 0x7: /* SQDMLSL, SQDMLSL2 */
10704 gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
10706 case 0x3: /* SQDMLAL, SQDMLAL2 */
10707 gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env,
10712 g_assert_not_reached();
10714 tcg_temp_free_i64(tcg_passres);
10716 tcg_temp_free_i32(tcg_idx);
10719 tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]);
10724 tcg_res[1] = tcg_const_i64(0);
10727 for (pass = 0; pass < 2; pass++) {
10728 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
10729 tcg_temp_free_i64(tcg_res[pass]);
10733 if (!TCGV_IS_UNUSED_PTR(fpst)) {
10734 tcg_temp_free_ptr(fpst);
10738 /* C3.6.19 Crypto AES
10739 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10740 * +-----------------+------+-----------+--------+-----+------+------+
10741 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10742 * +-----------------+------+-----------+--------+-----+------+------+
10744 static void disas_crypto_aes(DisasContext *s, uint32_t insn)
10746 int size = extract32(insn, 22, 2);
10747 int opcode = extract32(insn, 12, 5);
10748 int rn = extract32(insn, 5, 5);
10749 int rd = extract32(insn, 0, 5);
10751 TCGv_i32 tcg_rd_regno, tcg_rn_regno, tcg_decrypt;
10752 CryptoThreeOpEnvFn *genfn;
10754 if (!arm_dc_feature(s, ARM_FEATURE_V8_AES)
10756 unallocated_encoding(s);
10761 case 0x4: /* AESE */
10763 genfn = gen_helper_crypto_aese;
10765 case 0x6: /* AESMC */
10767 genfn = gen_helper_crypto_aesmc;
10769 case 0x5: /* AESD */
10771 genfn = gen_helper_crypto_aese;
10773 case 0x7: /* AESIMC */
10775 genfn = gen_helper_crypto_aesmc;
10778 unallocated_encoding(s);
10782 /* Note that we convert the Vx register indexes into the
10783 * index within the vfp.regs[] array, so we can share the
10784 * helper with the AArch32 instructions.
10786 tcg_rd_regno = tcg_const_i32(rd << 1);
10787 tcg_rn_regno = tcg_const_i32(rn << 1);
10788 tcg_decrypt = tcg_const_i32(decrypt);
10790 genfn(cpu_env, tcg_rd_regno, tcg_rn_regno, tcg_decrypt);
10792 tcg_temp_free_i32(tcg_rd_regno);
10793 tcg_temp_free_i32(tcg_rn_regno);
10794 tcg_temp_free_i32(tcg_decrypt);
10797 /* C3.6.20 Crypto three-reg SHA
10798 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10799 * +-----------------+------+---+------+---+--------+-----+------+------+
10800 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10801 * +-----------------+------+---+------+---+--------+-----+------+------+
10803 static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
10805 int size = extract32(insn, 22, 2);
10806 int opcode = extract32(insn, 12, 3);
10807 int rm = extract32(insn, 16, 5);
10808 int rn = extract32(insn, 5, 5);
10809 int rd = extract32(insn, 0, 5);
10810 CryptoThreeOpEnvFn *genfn;
10811 TCGv_i32 tcg_rd_regno, tcg_rn_regno, tcg_rm_regno;
10812 int feature = ARM_FEATURE_V8_SHA256;
10815 unallocated_encoding(s);
10820 case 0: /* SHA1C */
10821 case 1: /* SHA1P */
10822 case 2: /* SHA1M */
10823 case 3: /* SHA1SU0 */
10825 feature = ARM_FEATURE_V8_SHA1;
10827 case 4: /* SHA256H */
10828 genfn = gen_helper_crypto_sha256h;
10830 case 5: /* SHA256H2 */
10831 genfn = gen_helper_crypto_sha256h2;
10833 case 6: /* SHA256SU1 */
10834 genfn = gen_helper_crypto_sha256su1;
10837 unallocated_encoding(s);
10841 if (!arm_dc_feature(s, feature)) {
10842 unallocated_encoding(s);
10846 tcg_rd_regno = tcg_const_i32(rd << 1);
10847 tcg_rn_regno = tcg_const_i32(rn << 1);
10848 tcg_rm_regno = tcg_const_i32(rm << 1);
10851 genfn(cpu_env, tcg_rd_regno, tcg_rn_regno, tcg_rm_regno);
10853 TCGv_i32 tcg_opcode = tcg_const_i32(opcode);
10855 gen_helper_crypto_sha1_3reg(cpu_env, tcg_rd_regno,
10856 tcg_rn_regno, tcg_rm_regno, tcg_opcode);
10857 tcg_temp_free_i32(tcg_opcode);
10860 tcg_temp_free_i32(tcg_rd_regno);
10861 tcg_temp_free_i32(tcg_rn_regno);
10862 tcg_temp_free_i32(tcg_rm_regno);
10865 /* C3.6.21 Crypto two-reg SHA
10866 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10867 * +-----------------+------+-----------+--------+-----+------+------+
10868 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10869 * +-----------------+------+-----------+--------+-----+------+------+
10871 static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
10873 int size = extract32(insn, 22, 2);
10874 int opcode = extract32(insn, 12, 5);
10875 int rn = extract32(insn, 5, 5);
10876 int rd = extract32(insn, 0, 5);
10877 CryptoTwoOpEnvFn *genfn;
10879 TCGv_i32 tcg_rd_regno, tcg_rn_regno;
10882 unallocated_encoding(s);
10887 case 0: /* SHA1H */
10888 feature = ARM_FEATURE_V8_SHA1;
10889 genfn = gen_helper_crypto_sha1h;
10891 case 1: /* SHA1SU1 */
10892 feature = ARM_FEATURE_V8_SHA1;
10893 genfn = gen_helper_crypto_sha1su1;
10895 case 2: /* SHA256SU0 */
10896 feature = ARM_FEATURE_V8_SHA256;
10897 genfn = gen_helper_crypto_sha256su0;
10900 unallocated_encoding(s);
10904 if (!arm_dc_feature(s, feature)) {
10905 unallocated_encoding(s);
10909 tcg_rd_regno = tcg_const_i32(rd << 1);
10910 tcg_rn_regno = tcg_const_i32(rn << 1);
10912 genfn(cpu_env, tcg_rd_regno, tcg_rn_regno);
10914 tcg_temp_free_i32(tcg_rd_regno);
10915 tcg_temp_free_i32(tcg_rn_regno);
10918 /* C3.6 Data processing - SIMD, inc Crypto
10920 * As the decode gets a little complex we are using a table based
10921 * approach for this part of the decode.
10923 static const AArch64DecodeTable data_proc_simd[] = {
10924 /* pattern , mask , fn */
10925 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same },
10926 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff },
10927 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
10928 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes },
10929 { 0x0e000400, 0x9fe08400, disas_simd_copy },
10930 { 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */
10931 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
10932 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm },
10933 { 0x0f000400, 0x9f800400, disas_simd_shift_imm },
10934 { 0x0e000000, 0xbf208c00, disas_simd_tb },
10935 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn },
10936 { 0x2e000000, 0xbf208400, disas_simd_ext },
10937 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same },
10938 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff },
10939 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
10940 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise },
10941 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy },
10942 { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */
10943 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
10944 { 0x4e280800, 0xff3e0c00, disas_crypto_aes },
10945 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha },
10946 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha },
10947 { 0x00000000, 0x00000000, NULL }
10950 static void disas_data_proc_simd(DisasContext *s, uint32_t insn)
10952 /* Note that this is called with all non-FP cases from
10953 * table C3-6 so it must UNDEF for entries not specifically
10954 * allocated to instructions in that table.
10956 AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn);
10960 unallocated_encoding(s);
10964 /* C3.6 Data processing - SIMD and floating point */
10965 static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
10967 if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) {
10968 disas_data_proc_fp(s, insn);
10970 /* SIMD, including crypto */
10971 disas_data_proc_simd(s, insn);
10975 /* C3.1 A64 instruction index by encoding */
10976 static void disas_a64_insn(CPUARMState *env, DisasContext *s)
10980 insn = arm_ldl_code(env, s->pc, s->sctlr_b);
10984 s->fp_access_checked = false;
10986 switch (extract32(insn, 25, 4)) {
10987 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
10988 unallocated_encoding(s);
10990 case 0x8: case 0x9: /* Data processing - immediate */
10991 disas_data_proc_imm(s, insn);
10993 case 0xa: case 0xb: /* Branch, exception generation and system insns */
10994 disas_b_exc_sys(s, insn);
10999 case 0xe: /* Loads and stores */
11000 disas_ldst(s, insn);
11003 case 0xd: /* Data processing - register */
11004 disas_data_proc_reg(s, insn);
11007 case 0xf: /* Data processing - SIMD and floating point */
11008 disas_data_proc_simd_fp(s, insn);
11011 assert(FALSE); /* all 15 cases should be handled above */
11015 /* if we allocated any temporaries, free them here */
11019 void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
11021 CPUState *cs = CPU(cpu);
11022 CPUARMState *env = &cpu->env;
11023 DisasContext dc1, *dc = &dc1;
11024 target_ulong pc_start;
11025 target_ulong next_page_start;
11033 dc->is_jmp = DISAS_NEXT;
11035 dc->singlestep_enabled = cs->singlestep_enabled;
11039 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11040 * there is no secure EL1, so we route exceptions to EL3.
11042 dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
11043 !arm_el_is_aa64(env, 3);
11046 dc->be_data = ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE;
11047 dc->condexec_mask = 0;
11048 dc->condexec_cond = 0;
11049 dc->mmu_idx = ARM_TBFLAG_MMUIDX(tb->flags);
11050 dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
11051 #if !defined(CONFIG_USER_ONLY)
11052 dc->user = (dc->current_el == 0);
11054 dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(tb->flags);
11056 dc->vec_stride = 0;
11057 dc->cp_regs = cpu->cp_regs;
11058 dc->features = env->features;
11060 /* Single step state. The code-generation logic here is:
11062 * generate code with no special handling for single-stepping (except
11063 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11064 * this happens anyway because those changes are all system register or
11066 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11067 * emit code for one insn
11068 * emit code to clear PSTATE.SS
11069 * emit code to generate software step exception for completed step
11070 * end TB (as usual for having generated an exception)
11071 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11072 * emit code to generate a software step exception
11075 dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags);
11076 dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags);
11077 dc->is_ldex = false;
11078 dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el);
11080 init_tmp_a64_array(dc);
11082 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
11084 max_insns = tb->cflags & CF_COUNT_MASK;
11085 if (max_insns == 0) {
11086 max_insns = CF_COUNT_MASK;
11088 if (max_insns > TCG_MAX_INSNS) {
11089 max_insns = TCG_MAX_INSNS;
11094 tcg_clear_temp_count();
11097 tcg_gen_insn_start(dc->pc, 0);
11100 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11102 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
11103 if (bp->pc == dc->pc) {
11104 if (bp->flags & BP_CPU) {
11105 gen_a64_set_pc_im(dc->pc);
11106 gen_helper_check_breakpoints(cpu_env);
11107 /* End the TB early; it likely won't be executed */
11108 dc->is_jmp = DISAS_UPDATE;
11110 gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
11111 /* The address covered by the breakpoint must be
11112 included in [tb->pc, tb->pc + tb->size) in order
11113 to for it to be properly cleared -- thus we
11114 increment the PC here so that the logic setting
11115 tb->size below does the right thing. */
11117 goto done_generating;
11124 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
11128 if (dc->ss_active && !dc->pstate_ss) {
11129 /* Singlestep state is Active-pending.
11130 * If we're in this state at the start of a TB then either
11131 * a) we just took an exception to an EL which is being debugged
11132 * and this is the first insn in the exception handler
11133 * b) debug exceptions were masked and we just unmasked them
11134 * without changing EL (eg by clearing PSTATE.D)
11135 * In either case we're going to take a swstep exception in the
11136 * "did not step an insn" case, and so the syndrome ISV and EX
11137 * bits should be zero.
11139 assert(num_insns == 1);
11140 gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
11141 default_exception_el(dc));
11142 dc->is_jmp = DISAS_EXC;
11146 disas_a64_insn(env, dc);
11148 if (tcg_check_temp_count()) {
11149 fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
11153 /* Translation stops when a conditional branch is encountered.
11154 * Otherwise the subsequent code could get translated several times.
11155 * Also stop translation when a page boundary is reached. This
11156 * ensures prefetch aborts occur at the right place.
11158 } while (!dc->is_jmp && !tcg_op_buf_full() &&
11159 !cs->singlestep_enabled &&
11162 dc->pc < next_page_start &&
11163 num_insns < max_insns);
11165 if (tb->cflags & CF_LAST_IO) {
11169 if (unlikely(cs->singlestep_enabled || dc->ss_active)
11170 && dc->is_jmp != DISAS_EXC) {
11171 /* Note that this means single stepping WFI doesn't halt the CPU.
11172 * For conditional branch insns this is harmless unreachable code as
11173 * gen_goto_tb() has already handled emitting the debug exception
11174 * (and thus a tb-jump is not possible when singlestepping).
11176 assert(dc->is_jmp != DISAS_TB_JUMP);
11177 if (dc->is_jmp != DISAS_JUMP) {
11178 gen_a64_set_pc_im(dc->pc);
11180 if (cs->singlestep_enabled) {
11181 gen_exception_internal(EXCP_DEBUG);
11183 gen_step_complete_exception(dc);
11186 switch (dc->is_jmp) {
11188 gen_goto_tb(dc, 1, dc->pc);
11192 gen_a64_set_pc_im(dc->pc);
11195 /* indicate that the hash table must be used to find the next TB */
11196 tcg_gen_exit_tb(0);
11198 case DISAS_TB_JUMP:
11203 gen_a64_set_pc_im(dc->pc);
11204 gen_helper_wfe(cpu_env);
11207 gen_a64_set_pc_im(dc->pc);
11208 gen_helper_yield(cpu_env);
11211 /* This is a special case because we don't want to just halt the CPU
11212 * if trying to debug across a WFI.
11214 gen_a64_set_pc_im(dc->pc);
11215 gen_helper_wfi(cpu_env);
11216 /* The helper doesn't necessarily throw an exception, but we
11217 * must go back to the main loop to check for interrupts anyway.
11219 tcg_gen_exit_tb(0);
11225 gen_tb_end(tb, num_insns);
11228 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) &&
11229 qemu_log_in_addr_range(pc_start)) {
11230 qemu_log("----------------\n");
11231 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11232 log_target_disas(cs, pc_start, dc->pc - pc_start,
11233 4 | (bswap_code(dc->sctlr_b) ? 2 : 0));
11237 tb->size = dc->pc - pc_start;
11238 tb->icount = num_insns;