2 // QEMU Cirrus CLGD 54xx VGABIOS Extension.
4 // Copyright (c) 2004 Makoto Suzuki (suzu)
6 // This library is free software; you can redistribute it and/or
7 // modify it under the terms of the GNU Lesser General Public
8 // License as published by the Free Software Foundation; either
9 // version 2 of the License, or (at your option) any later version.
11 // This library is distributed in the hope that it will be useful,
12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 // Lesser General Public License for more details.
16 // You should have received a copy of the GNU Lesser General Public
17 // License along with this library; if not, write to the Free Software
18 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 //#define CIRRUS_VESA3_PMINFO
23 #undef CIRRUS_VESA3_PMINFO
26 #define PM_BIOSMEM_CURRENT_MODE 0x449
27 #define PM_BIOSMEM_CRTC_ADDRESS 0x463
28 #define PM_BIOSMEM_VBE_MODE 0x4BA
35 unsigned short height;
38 unsigned short hidden_dac; /* 0x3c6 */
39 unsigned short *seq; /* 0x3c4 */
40 unsigned short *graph; /* 0x3ce */
41 unsigned short *crtc; /* 0x3d4 */
43 unsigned char bitsperpixel;
44 unsigned char vesacolortype;
45 unsigned char vesaredmask;
46 unsigned char vesaredpos;
47 unsigned char vesagreenmask;
48 unsigned char vesagreenpos;
49 unsigned char vesabluemask;
50 unsigned char vesabluepos;
52 unsigned char vesareservedmask;
53 unsigned char vesareservedpos;
55 #define CIRRUS_MODE_SIZE 26
58 /* For VESA BIOS 3.0 */
59 #define CIRRUS_PM16INFO_SIZE 20
62 unsigned short cseq_vga[] = {0x0007,0xffff};
63 unsigned short cgraph_vga[] = {0x0009,0x000a,0x000b,0xffff};
64 unsigned short ccrtc_vga[] = {0x001a,0x001b,0x001d,0xffff};
67 unsigned short cgraph_svgacolor[] = {
68 0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
73 unsigned short cseq_640x480x8[] = {
74 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
75 0x580b,0x580c,0x580d,0x580e,
77 0x331b,0x331c,0x331d,0x331e,
80 unsigned short ccrtc_640x480x8[] = {
82 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
84 0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
89 unsigned short cseq_640x480x16[] = {
90 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
91 0x580b,0x580c,0x580d,0x580e,
93 0x331b,0x331c,0x331d,0x331e,
96 unsigned short ccrtc_640x480x16[] = {
98 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
100 0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
101 0x001a,0x221b,0x001d,
105 unsigned short cseq_640x480x24[] = {
106 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
107 0x580b,0x580c,0x580d,0x580e,
108 0x0412,0x0013,0x2017,
109 0x331b,0x331c,0x331d,0x331e,
112 unsigned short ccrtc_640x480x24[] = {
114 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
115 0x4009,0x000c,0x000d,
116 0xea10,0xdf12,0x0013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
117 0x001a,0x321b,0x001d,
121 unsigned short cseq_800x600x8[] = {
122 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
123 0x230b,0x230c,0x230d,0x230e,
124 0x0412,0x0013,0x2017,
125 0x141b,0x141c,0x141d,0x141e,
128 unsigned short ccrtc_800x600x8[] = {
129 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
130 0x6009,0x000c,0x000d,
131 0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
132 0x001a,0x221b,0x001d,
136 unsigned short cseq_800x600x16[] = {
137 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
138 0x230b,0x230c,0x230d,0x230e,
139 0x0412,0x0013,0x2017,
140 0x141b,0x141c,0x141d,0x141e,
143 unsigned short ccrtc_800x600x16[] = {
144 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
145 0x6009,0x000c,0x000d,
146 0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
147 0x001a,0x221b,0x001d,
151 unsigned short cseq_800x600x24[] = {
152 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
153 0x230b,0x230c,0x230d,0x230e,
154 0x0412,0x0013,0x2017,
155 0x141b,0x141c,0x141d,0x141e,
158 unsigned short ccrtc_800x600x24[] = {
159 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
160 0x6009,0x000c,0x000d,
161 0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
162 0x001a,0x321b,0x001d,
166 unsigned short cseq_1024x768x8[] = {
167 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
168 0x760b,0x760c,0x760d,0x760e,
169 0x0412,0x0013,0x2017,
170 0x341b,0x341c,0x341d,0x341e,
173 unsigned short ccrtc_1024x768x8[] = {
174 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
175 0x6009,0x000c,0x000d,
176 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
177 0x001a,0x221b,0x001d,
181 unsigned short cseq_1024x768x16[] = {
182 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
183 0x760b,0x760c,0x760d,0x760e,
184 0x0412,0x0013,0x2017,
185 0x341b,0x341c,0x341d,0x341e,
188 unsigned short ccrtc_1024x768x16[] = {
189 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
190 0x6009,0x000c,0x000d,
191 0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
192 0x001a,0x321b,0x001d,
196 unsigned short cseq_1024x768x24[] = {
197 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
198 0x760b,0x760c,0x760d,0x760e,
199 0x0412,0x0013,0x2017,
200 0x341b,0x341c,0x341d,0x341e,
203 unsigned short ccrtc_1024x768x24[] = {
204 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
205 0x6009,0x000c,0x000d,
206 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
207 0x001a,0x321b,0x001d,
211 unsigned short cseq_1280x1024x8[] = {
212 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
213 0x760b,0x760c,0x760d,0x760e,
214 0x0412,0x0013,0x2017,
215 0x341b,0x341c,0x341d,0x341e,
218 unsigned short ccrtc_1280x1024x8[] = {
219 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
220 0x6009,0x000c,0x000d,
221 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
222 0x001a,0x221b,0x001d,
226 unsigned short cseq_1280x1024x16[] = {
227 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
228 0x760b,0x760c,0x760d,0x760e,
229 0x0412,0x0013,0x2017,
230 0x341b,0x341c,0x341d,0x341e,
233 unsigned short ccrtc_1280x1024x16[] = {
234 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
235 0x6009,0x000c,0x000d,
236 0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
237 0x001a,0x321b,0x001d,
242 unsigned short cseq_1600x1200x8[] = {
243 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
244 0x760b,0x760c,0x760d,0x760e,
245 0x0412,0x0013,0x2017,
246 0x341b,0x341c,0x341d,0x341e,
249 unsigned short ccrtc_1600x1200x8[] = {
250 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
251 0x6009,0x000c,0x000d,
252 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
253 0x001a,0x221b,0x001d,
257 cirrus_mode_t cirrus_modes[] =
259 {0x5f,640,480,8,0x00,
260 cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8,8,
262 {0x64,640,480,16,0xe1,
263 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
265 {0x66,640,480,15,0xf0,
266 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
267 6,5,10,5,5,5,0,1,15},
268 {0x71,640,480,24,0xe5,
269 cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24,24,
272 {0x5c,800,600,8,0x00,
273 cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8,8,
275 {0x65,800,600,16,0xe1,
276 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
278 {0x67,800,600,15,0xf0,
279 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
280 6,5,10,5,5,5,0,1,15},
282 {0x60,1024,768,8,0x00,
283 cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8,8,
285 {0x74,1024,768,16,0xe1,
286 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
288 {0x68,1024,768,15,0xf0,
289 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
290 6,5,10,5,5,5,0,1,15},
292 {0x78,800,600,24,0xe5,
293 cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24,24,
295 {0x79,1024,768,24,0xe5,
296 cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24,24,
299 {0x6d,1280,1024,8,0x00,
300 cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8,8,
302 {0x69,1280,1024,15,0xf0,
303 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
304 6,5,10,5,5,5,0,1,15},
305 {0x75,1280,1024,16,0xe1,
306 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
309 {0x7b,1600,1200,8,0x00,
310 cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8,8,
313 {0xfe,0,0,0,0,cseq_vga,cgraph_vga,ccrtc_vga,0,
314 0xff,0,0,0,0,0,0,0,0},
315 {0xff,0,0,0,0,0,0,0,0,
316 0xff,0,0,0,0,0,0,0,0},
319 unsigned char cirrus_id_table[] = {
329 unsigned short cirrus_vesa_modelist[] = {
368 .ascii "cirrus-compatible VGA is detected"
372 cirrus_not_installed:
373 .ascii "cirrus-compatible VGA is not detected"
377 cirrus_vesa_vendorname:
378 cirrus_vesa_productname:
380 .ascii "VGABIOS Cirrus extension"
382 cirrus_vesa_productrevision:
389 SET_INT_VECTOR(0x10, #0xC000, #cirrus_int10_handler)
390 mov al, #0x0f ; memory setup
400 mov ax, #0x0007 ; set vga mode
402 mov ax, #0x0431 ; reset bitblt
416 mov si, #cirrus_not_installed
417 jnz cirrus_msgnotinstalled
418 mov si, #cirrus_installed
420 cirrus_msgnotinstalled:
440 cirrus_int10_handler:
443 cmp ah, #0x00 ;; set video mode
444 jz cirrus_set_video_mode
445 cmp ah, #0x12 ;; cirrus extension
447 cmp ah, #0x4F ;; VESA extension
453 jmp vgabios_int10_handler
457 call cirrus_debug_dump
463 cirrus_set_video_mode:
465 call cirrus_debug_dump
471 #ifdef CIRRUS_VESA3_PMINFO
473 mov si, [cirrus_vesa_sel0000_data]
479 mov [PM_BIOSMEM_VBE_MODE], bx
482 call cirrus_get_modeentry
483 jnc cirrus_set_video_mode_extended
485 call cirrus_get_modeentry_nomask
486 call cirrus_switch_mode
493 call cirrus_debug_dump
503 mov bp, cirrus_extbios_handlers[bx]
511 call cirrus_debug_dump
514 ja cirrus_vesa_not_handled
520 mov bp, cirrus_vesa_handlers[bx]
526 cirrus_vesa_not_handled:
527 mov ax, #0x014F ;; not implemented
537 call _cirrus_debugmsg
544 cirrus_set_video_mode_extended:
545 call cirrus_switch_mode
548 jnz cirrus_set_video_mode_extended_1
550 mov ax, #0xffff ; set to 0xff to keep win 2K happy
551 call cirrus_clear_vram
553 cirrus_set_video_mode_extended_1:
557 #ifdef CIRRUS_VESA3_PMINFO
559 mov si, [cirrus_vesa_sel0000_data]
564 mov [PM_BIOSMEM_CURRENT_MODE], al
572 cirrus_vesa_pmbios_init:
574 cirrus_vesa_pmbios_entry:
578 jnz cirrus_vesa_pmbios_unimplemented
580 ja cirrus_vesa_pmbios_unimplemented
586 mov bp, cirrus_vesa_handlers[bx]
588 push #cirrus_vesa_pmbios_return
591 cirrus_vesa_pmbios_unimplemented:
593 cirrus_vesa_pmbios_return:
606 mov bx, [si+10] ;; seq
609 out dx, ax ;; Unlock cirrus special
610 call cirrus_switch_mode_setregs
612 mov bx, [si+12] ;; graph
614 call cirrus_switch_mode_setregs
616 mov bx, [si+14] ;; crtc
618 call cirrus_switch_mode_setregs
627 mov al, [si+8] ;; hidden dac
633 mov bl, [si+17] ;; memory model
642 call biosfn_get_single_palette_reg
645 call biosfn_set_single_palette_reg
652 cirrus_enable_16k_granularity:
660 or al, #0x20 ;; enable 16k
666 cirrus_switch_mode_setregs:
684 mov bx, #_cirrus_id_table
704 mov ax, #0x100 ;; XXX
723 mov al, #0x0f ;; get DRAM band width
727 ;; al = 4 << bandwidth
739 mov al, #0x20 ;; 2 MB
741 mov al, #0x40 ;; 4 MB
753 call cirrus_get_modeentry
756 mov bx, cirrus_extbios_A0h_callback
763 cirrus_extbios_A0h_callback:
764 ;; fatal: not implemented yet
770 mov bx, #0x0E00 ;; IBM 8512/8513, color
774 mov al, #0x07 ;; HSync 31.5 - 64.0 kHz
778 mov al, #0x01 ;; High Refresh 75Hz
781 cirrus_extbios_unimplemented:
792 cmp ax, #0x4256 ;; VB
795 cmp ax, #0x3245 ;; E2
799 mov ax, #0x0100 ;; soft ver.
801 mov ax, # cirrus_vesa_vendorname
805 mov ax, # cirrus_vesa_productname
809 mov ax, # cirrus_vesa_productrevision
815 mov ax, #0x4556 ;; VE
817 mov ax, #0x4153 ;; SA
819 mov ax, #0x0200 ;; v2.00
821 mov ax, # cirrus_vesa_oemname
832 call cirrus_extbios_85h ;; vram in 64k
839 mov si, #_cirrus_vesa_modelist
856 call cirrus_vesamode_to_mode
858 jnz cirrus_vesa_01h_1
859 jmp cirrus_vesa_unimplemented
870 call cirrus_get_modeentry_nomask
876 stosw ;; clear buffer
879 mov ax, #0x003b ;; mode
881 mov ax, #0x0007 ;; attr
883 mov ax, #0x0010 ;; granularity =16K
885 mov ax, #0x0040 ;; size =64K
887 mov ax, #0xA000 ;; segment A
889 xor ax, ax ;; no segment B
891 mov ax, #cirrus_vesa_05h_farentry
895 call cirrus_get_line_offset_entry
896 stosw ;; bytes per scan line
897 mov ax, [si+2] ;; width
899 mov ax, [si+4] ;; height
905 mov al, #1 ;; count of planes
907 mov al, [si+6] ;; bpp
909 mov al, #0x1 ;; XXX number of banks
912 stosb ;; memory model
913 mov al, #0x0 ;; XXX size of bank in K
915 call cirrus_get_line_offset_entry
917 mul bx ;; dx:ax=vramdisp
922 call cirrus_extbios_85h ;; al=vram in 64k
928 stosb ;; number of image pages = vramtotal/vramdisp-1
944 rcl al, #1 ; bit 0=palette flag
945 stosb ;; direct screen mode info
948 ;; 32-bit LFB address
951 mov ax, #0x1013 ;; vendor Cirrus
952 call _pci_get_lfb_addr
960 or ax, #0x0080 ;; mode bit 7:LFB
978 test cx, #0x4000 ;; LFB flag
983 cmp cx, #0x0080 ;; is LFB supported?
984 jnz cirrus_vesa_01h_6
985 mov ax, #0x014F ;; error - no LFB
992 ;; XXX support CRTC registers
994 jnz cirrus_vesa_02h_2 ;; unknown flags
996 and ax, #0x1ff ;; bit 8-0 mode
997 cmp ax, #0x100 ;; legacy VGA mode
998 jb cirrus_vesa_02h_legacy
999 call cirrus_vesamode_to_mode
1001 jnz cirrus_vesa_02h_1
1003 jmp cirrus_vesa_unimplemented
1004 cirrus_vesa_02h_legacy:
1005 #ifdef CIRRUS_VESA3_PMINFO
1007 cmp byte ptr [cirrus_vesa_is_protected_mode], #0
1008 jnz cirrus_vesa_02h_2
1009 #endif // CIRRUS_VESA3_PMINFO
1016 call cirrus_get_modeentry_nomask
1017 call cirrus_switch_mode
1018 test bx, #0x4000 ;; LFB
1019 jnz cirrus_vesa_02h_3
1020 call cirrus_enable_16k_granularity
1022 test bx, #0x8000 ;; no clear
1023 jnz cirrus_vesa_02h_4
1026 call cirrus_clear_vram
1031 #ifdef CIRRUS_VESA3_PMINFO
1033 mov si, [cirrus_vesa_sel0000_data]
1038 mov [PM_BIOSMEM_CURRENT_MODE], al
1039 mov [PM_BIOSMEM_VBE_MODE], bx
1047 #ifdef CIRRUS_VESA3_PMINFO
1049 mov ax, [cirrus_vesa_sel0000_data]
1054 mov bx, # PM_BIOSMEM_VBE_MODE
1058 jnz cirrus_vesa_03h_1
1059 mov bx, # PM_BIOSMEM_CURRENT_MODE
1068 cirrus_vesa_05h_farentry:
1069 call cirrus_vesa_05h
1074 ja cirrus_vesa_05h_1
1076 jz cirrus_vesa_05h_setmempage
1078 jz cirrus_vesa_05h_getmempage
1080 jmp cirrus_vesa_unimplemented
1081 cirrus_vesa_05h_setmempage:
1082 or dh, dh ; address must be < 0x100
1083 jnz cirrus_vesa_05h_1
1085 mov al, bl ;; bl=bank number
1087 mov ah, dl ;; dx=window address in granularity
1093 cirrus_vesa_05h_getmempage:
1094 mov al, bl ;; bl=bank number
1101 mov dl, al ;; dx=window address in granularity
1108 je cirrus_vesa_06h_3
1110 je cirrus_vesa_06h_2
1111 jb cirrus_vesa_06h_1
1115 call cirrus_get_bpp_bytes
1121 call cirrus_set_line_offset
1123 call cirrus_get_bpp_bytes
1127 call cirrus_get_line_offset
1132 call cirrus_extbios_85h ;; al=vram in 64k
1143 je cirrus_vesa_07h_1
1145 je cirrus_vesa_07h_2
1146 jb cirrus_vesa_07h_1
1151 call cirrus_get_bpp_bytes
1158 call cirrus_get_line_offset
1162 jnc cirrus_vesa_07h_3
1171 call cirrus_set_start_addr
1175 call cirrus_get_start_addr
1183 call cirrus_get_line_offset
1189 call cirrus_get_bpp_bytes
1202 jne cirrus_vesa_10h_01
1208 jne cirrus_vesa_10h_02
1220 jne cirrus_vesa_unimplemented
1231 cirrus_vesa_unimplemented:
1232 mov ax, #0x014F ;; not implemented
1236 ;; in ax:vesamode, out ax:cirrusmode
1237 cirrus_vesamode_to_mode:
1244 mov si, #_cirrus_vesa_modelist
1260 ;; NOTE - may be called in protected mode
1274 ;; in - al:mode, out - cflag:result, si:table, ax:destroyed
1275 cirrus_get_modeentry:
1277 cirrus_get_modeentry_nomask:
1278 mov si, #_cirrus_modes
1286 add si, # CIRRUS_MODE_SIZE
1290 stc ;; video mode is not supported
1293 clc ;; video mode is supported
1297 ;; out - al:bytes per pixel
1298 cirrus_get_bpp_bytes:
1307 jne cirrus_get_bpp_bytes_1
1309 cirrus_get_bpp_bytes_1:
1312 je cirrus_get_bpp_bytes_2
1314 cirrus_get_bpp_bytes_2:
1318 ;; in - ax: new line offset
1319 cirrus_set_line_offset:
1322 call cirrus_get_crtc
1339 ;; out - ax: active line offset
1340 cirrus_get_line_offset:
1343 call cirrus_get_crtc
1364 ;; out - ax: line offset for mode
1365 cirrus_get_line_offset_entry:
1367 mov bx, [si+14] ;; crtc table
1396 ;; in - new address in DX:AX
1397 cirrus_set_start_addr:
1401 call cirrus_get_crtc
1441 ;; out - current address in DX:AX
1442 cirrus_get_start_addr:
1444 call cirrus_get_crtc
1485 call cirrus_enable_16k_granularity
1486 call cirrus_extbios_85h
1490 cirrus_clear_vram_1:
1506 jne cirrus_clear_vram_1
1516 cirrus_extbios_handlers:
1518 dw cirrus_extbios_80h
1519 dw cirrus_extbios_81h
1520 dw cirrus_extbios_82h
1521 dw cirrus_extbios_unimplemented
1523 dw cirrus_extbios_unimplemented
1524 dw cirrus_extbios_85h
1525 dw cirrus_extbios_unimplemented
1526 dw cirrus_extbios_unimplemented
1528 dw cirrus_extbios_unimplemented
1529 dw cirrus_extbios_unimplemented
1530 dw cirrus_extbios_unimplemented
1531 dw cirrus_extbios_unimplemented
1533 dw cirrus_extbios_unimplemented
1534 dw cirrus_extbios_unimplemented
1535 dw cirrus_extbios_unimplemented
1536 dw cirrus_extbios_unimplemented
1538 dw cirrus_extbios_unimplemented
1539 dw cirrus_extbios_unimplemented
1540 dw cirrus_extbios_unimplemented
1541 dw cirrus_extbios_unimplemented
1543 dw cirrus_extbios_unimplemented
1544 dw cirrus_extbios_unimplemented
1545 dw cirrus_extbios_unimplemented
1546 dw cirrus_extbios_unimplemented
1548 dw cirrus_extbios_unimplemented
1549 dw cirrus_extbios_unimplemented
1550 dw cirrus_extbios_9Ah
1551 dw cirrus_extbios_unimplemented
1553 dw cirrus_extbios_unimplemented
1554 dw cirrus_extbios_unimplemented
1555 dw cirrus_extbios_unimplemented
1556 dw cirrus_extbios_unimplemented
1558 dw cirrus_extbios_A0h
1559 dw cirrus_extbios_A1h
1560 dw cirrus_extbios_A2h
1561 dw cirrus_extbios_unimplemented
1563 dw cirrus_extbios_unimplemented
1564 dw cirrus_extbios_unimplemented
1565 dw cirrus_extbios_unimplemented
1566 dw cirrus_extbios_unimplemented
1568 dw cirrus_extbios_unimplemented
1569 dw cirrus_extbios_unimplemented
1570 dw cirrus_extbios_unimplemented
1571 dw cirrus_extbios_unimplemented
1573 dw cirrus_extbios_unimplemented
1574 dw cirrus_extbios_unimplemented
1575 dw cirrus_extbios_AEh
1576 dw cirrus_extbios_unimplemented
1578 cirrus_vesa_handlers:
1585 dw cirrus_vesa_unimplemented
1590 dw cirrus_vesa_unimplemented
1591 dw cirrus_vesa_unimplemented
1592 dw cirrus_vesa_unimplemented
1593 dw cirrus_vesa_unimplemented
1595 dw cirrus_vesa_unimplemented
1596 dw cirrus_vesa_unimplemented
1597 dw cirrus_vesa_unimplemented
1598 dw cirrus_vesa_unimplemented
1605 #ifdef CIRRUS_VESA3_PMINFO
1609 .byte 0x50,0x4d,0x49,0x44 ;; signature[4]
1611 dw cirrus_vesa_pmbios_entry ;; entry_bios
1612 dw cirrus_vesa_pmbios_init ;; entry_init
1614 cirrus_vesa_sel0000_data:
1615 dw 0x0000 ;; sel_00000
1616 cirrus_vesa_selA000_data:
1617 dw 0xA000 ;; sel_A0000
1619 cirrus_vesa_selB000_data:
1620 dw 0xB000 ;; sel_B0000
1621 cirrus_vesa_selB800_data:
1622 dw 0xB800 ;; sel_B8000
1624 cirrus_vesa_selC000_data:
1625 dw 0xC000 ;; sel_C0000
1626 cirrus_vesa_is_protected_mode:
1627 ;; protected mode flag and checksum
1628 dw (~((0xf2 + (cirrus_vesa_pmbios_entry >> 8) + (cirrus_vesa_pmbios_entry) \
1629 + (cirrus_vesa_pmbios_init >> 8) + (cirrus_vesa_pmbios_init)) & 0xff) << 8) + 0x01
1631 #endif // CIRRUS_VESA3_PMINFO
1635 static void cirrus_debugmsg(DI, SI, BP, SP, BX, DX, CX, AX, DS, ES, FLAGS)
1636 Bit16u DI, SI, BP, SP, BX, DX, CX, AX, ES, DS, FLAGS;
1638 if((GET_AH()!=0x0E)&&(GET_AH()!=0x02)&&(GET_AH()!=0x09)&&(AX!=0x4F05))
1639 printf("vgabios call ah%02x al%02x bx%04x cx%04x dx%04x\n",GET_AH(),GET_AL(),BX,CX,DX);