2 * Cirrus Logic EP93xx PLL support.
4 * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/ep93xx.h>
15 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
17 * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
18 * the specified bus in HZ.
22 * return the PLL output frequency
24 * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
25 * / (X2IPD + 1) / 2^PS
27 static ulong get_PLLCLK(uint32_t *pllreg)
30 const uint32_t clkset = readl(pllreg);
31 uint64_t rate = CONFIG_SYS_CLK_FREQ;
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
33 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
34 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
35 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
41 /* return FCLK frequency */
44 const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
45 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
47 const uint32_t clkset1 = readl(&syscon->clkset1);
48 const uint8_t fclk_div =
49 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
50 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
55 /* return HCLK frequency */
58 const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
59 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
61 const uint32_t clkset1 = readl(&syscon->clkset1);
62 const uint8_t hclk_div =
63 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
64 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
69 /* return PCLK frequency */
72 const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
73 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
75 const uint32_t clkset1 = readl(&syscon->clkset1);
76 const uint8_t pclk_div =
77 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
78 const ulong pclk_rate = get_HCLK() / pclk_div;
83 /* return UCLK frequency */
86 struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
89 const uint32_t value = readl(&syscon->pwrcnt);
90 if (value & SYSCON_PWRCNT_UART_BAUD)
91 uclk_rate = CONFIG_SYS_CLK_FREQ;
93 uclk_rate = CONFIG_SYS_CLK_FREQ / 2;