6 /* Define for section 12.3 */
8 #define TCG_PC_TPMERROR 0x1
9 #define TCG_PC_LOGOVERFLOW 0x2
10 #define TCG_PC_UNSUPPORTED 0x3
12 #define TPM_ALG_SHA 0x4
14 #define TCG_MAGIC 0x41504354L
15 #define TCG_VERSION_MAJOR 1
16 #define TCG_VERSION_MINOR 2
19 #define TPM_RET_BASE 0x1
20 #define TCG_GENERAL_ERROR (TPM_RET_BASE + 0x0)
21 #define TCG_TPM_IS_LOCKED (TPM_RET_BASE + 0x1)
22 #define TCG_NO_RESPONSE (TPM_RET_BASE + 0x2)
23 #define TCG_INVALID_RESPONSE (TPM_RET_BASE + 0x3)
24 #define TCG_INVALID_ACCESS_REQUEST (TPM_RET_BASE + 0x4)
25 #define TCG_FIRMWARE_ERROR (TPM_RET_BASE + 0x5)
26 #define TCG_INTEGRITY_CHECK_FAILED (TPM_RET_BASE + 0x6)
27 #define TCG_INVALID_DEVICE_ID (TPM_RET_BASE + 0x7)
28 #define TCG_INVALID_VENDOR_ID (TPM_RET_BASE + 0x8)
29 #define TCG_UNABLE_TO_OPEN (TPM_RET_BASE + 0x9)
30 #define TCG_UNABLE_TO_CLOSE (TPM_RET_BASE + 0xa)
31 #define TCG_RESPONSE_TIMEOUT (TPM_RET_BASE + 0xb)
32 #define TCG_INVALID_COM_REQUEST (TPM_RET_BASE + 0xc)
33 #define TCG_INVALID_ADR_REQUEST (TPM_RET_BASE + 0xd)
34 #define TCG_WRITE_BYTE_ERROR (TPM_RET_BASE + 0xe)
35 #define TCG_READ_BYTE_ERROR (TPM_RET_BASE + 0xf)
36 #define TCG_BLOCK_WRITE_TIMEOUT (TPM_RET_BASE + 0x10)
37 #define TCG_CHAR_WRITE_TIMEOUT (TPM_RET_BASE + 0x11)
38 #define TCG_CHAR_READ_TIMEOUT (TPM_RET_BASE + 0x12)
39 #define TCG_BLOCK_READ_TIMEOUT (TPM_RET_BASE + 0x13)
40 #define TCG_TRANSFER_ABORT (TPM_RET_BASE + 0x14)
41 #define TCG_INVALID_DRV_FUNCTION (TPM_RET_BASE + 0x15)
42 #define TCG_OUTPUT_BUFFER_TOO_SHORT (TPM_RET_BASE + 0x16)
43 #define TCG_FATAL_COM_ERROR (TPM_RET_BASE + 0x17)
44 #define TCG_INVALID_INPUT_PARA (TPM_RET_BASE + 0x18)
45 #define TCG_TCG_COMMAND_ERROR (TPM_RET_BASE + 0x19)
46 #define TCG_INTERFACE_SHUTDOWN (TPM_RET_BASE + 0x20)
47 //define TCG_PC_UNSUPPORTED (TPM_RET_BASE + 0x21)
48 #define TCG_PC_TPM_NOT_PRESENT (TPM_RET_BASE + 0x22)
49 #define TCG_PC_TPM_DEACTIVATED (TPM_RET_BASE + 0x23)
52 #define TPM_ORD_SelfTestFull 0x00000050
53 #define TPM_ORD_ForceClear 0x0000005d
54 #define TPM_ORD_GetCapability 0x00000065
55 #define TPM_ORD_PhysicalEnable 0x0000006f
56 #define TPM_ORD_PhysicalDisable 0x00000070
57 #define TPM_ORD_SetOwnerInstall 0x00000071
58 #define TPM_ORD_PhysicalSetDeactivated 0x00000072
59 #define TPM_ORD_Startup 0x00000099
60 #define TPM_ORD_PhysicalPresence 0x4000000a
61 #define TPM_ORD_Extend 0x00000014
62 #define TPM_ORD_SHA1Start 0x000000a0
63 #define TPM_ORD_SHA1Update 0x000000a1
64 #define TPM_ORD_SHA1Complete 0x000000a2
65 #define TSC_ORD_ResetEstablishmentBit 0x4000000b
68 #define TPM_ST_CLEAR 0x1
69 #define TPM_ST_STATE 0x2
70 #define TPM_ST_DEACTIVATED 0x3
73 /* TPM command error codes */
74 #define TPM_INVALID_POSTINIT 0x26
75 #define TPM_BAD_LOCALITY 0x3d
77 /* TPM command tags */
78 #define TPM_TAG_RQU_CMD 0x00c1
80 /* interrupt identifiers (al register) */
83 TCG_HashLogExtendEvent = 1,
84 TCG_PassThroughToTPM = 2,
85 TCG_ShutdownPreBootInterface = 3,
89 TCG_CompactHashLogExtendEvent = 7,
92 /* event types: 10.4.1 / table 11 */
93 #define EV_POST_CODE 1
94 #define EV_SEPARATOR 4
96 #define EV_EVENT_TAG 6
97 #define EV_COMPACT_HASH 12
99 #define EV_IPL_PARTITION_DATA 14
102 #define STATUS_FLAG_SHUTDOWN (1 << 0)
104 #define SHA1_BUFSIZE 20
114 /* Input and Output blocks for the TCG BIOS commands */
120 const void *hashdataptr;
123 const void *logdataptr;
146 u8 digest[SHA1_BUFSIZE];
172 const void *hashdataptr;
176 const void *logdataptr;
193 const void *hashdataptr;
221 u8 digest[SHA1_BUFSIZE];
230 u8 digest[SHA1_BUFSIZE];
239 u8 digest[SHA1_BUFSIZE];
243 #define TPM_REQ_HEADER \
248 #define TPM_REQ_HEADER_SIZE (sizeof(u16) + sizeof(u32) + sizeof(u32))
250 #define TPM_RSP_HEADER \
255 #define TPM_RSP_HEADER_SIZE (sizeof(u16) + sizeof(u32) + sizeof(u32))
257 struct tpm_req_header {
262 struct tpm_rsp_header {
267 struct tpm_req_extend {
270 u8 digest[SHA1_BUFSIZE];
274 struct tpm_rsp_extend {
276 u8 digest[SHA1_BUFSIZE];
280 struct tpm_req_getcap_perm_flags {
288 struct tpm_permanent_flags {
294 enum permFlagsIndex {
295 PERM_FLAG_IDX_DISABLE = 0,
296 PERM_FLAG_IDX_OWNERSHIP,
297 PERM_FLAG_IDX_DEACTIVATED,
298 PERM_FLAG_IDX_READPUBEK,
299 PERM_FLAG_IDX_DISABLEOWNERCLEAR,
300 PERM_FLAG_IDX_ALLOW_MAINTENANCE,
301 PERM_FLAG_IDX_PHYSICAL_PRESENCE_LIFETIME_LOCK,
302 PERM_FLAG_IDX_PHYSICAL_PRESENCE_HW_ENABLE,
306 struct tpm_res_getcap_perm_flags {
309 struct tpm_permanent_flags perm_flags;
313 struct tpm_res_getcap_ownerauth {
320 struct tpm_res_getcap_timeouts {
327 struct tpm_res_getcap_durations {
334 struct tpm_res_sha1start {
340 struct tpm_res_sha1complete {
345 struct pttti_extend {
347 struct tpm_req_extend req;
351 struct pttto_extend {
353 struct tpm_rsp_extend rsp;
365 void tpm_interrupt_handler32(struct bregs *regs);
367 void tpm_setup(void);
368 void tpm_prepboot(void);
369 void tpm_s3_resume(void);
370 u32 tpm_add_bcv(u32 bootdrv, const u8 *addr, u32 length);
371 u32 tpm_add_cdrom(u32 bootdrv, const u8 *addr, u32 length);
372 u32 tpm_add_cdrom_catalog(const u8 *addr, u32 length);
373 u32 tpm_option_rom(const void *addr, u32 len);
375 #endif /* TCGBIOS_H */