1 // Code for misc 16bit handlers and variables.
3 // Copyright (C) 2008,2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "biosvar.h" // GET_BDA
9 #include "bregs.h" // struct bregs
10 #include "hw/pic.h" // enable_hwirq
11 #include "output.h" // debug_enter
12 #include "stacks.h" // call16_int
13 #include "string.h" // memset
15 #define PORT_MATH_CLEAR 0x00f0
17 // Indicator if POST phase has been started (and if it has completed).
18 int HaveRunPost VARFSEG;
23 return GET_GLOBAL(HaveRunPost) == 1;
27 /****************************************************************
29 ****************************************************************/
31 // INT 12h Memory Size Service Entry Point
33 handle_12(struct bregs *regs)
35 debug_enter(regs, DEBUG_HDL_12);
36 regs->ax = GET_BDA(mem_size_kb);
39 // INT 11h Equipment List Service Entry Point
41 handle_11(struct bregs *regs)
43 debug_enter(regs, DEBUG_HDL_11);
44 regs->ax = GET_BDA(equipment_list_flags);
47 // INT 05h Print Screen Service Entry Point
49 handle_05(struct bregs *regs)
51 debug_enter(regs, DEBUG_HDL_05);
54 // INT 10h Video Support Service Entry Point
56 handle_10(struct bregs *regs)
58 debug_enter(regs, DEBUG_HDL_10);
59 // don't do anything, since the VGA BIOS handles int10h requests
66 debug_isr(DEBUG_ISR_02);
72 dprintf(3, "math cp init\n");
73 // 80x87 coprocessor installed
74 set_equipment_flags(0x02, 0x02);
75 enable_hwirq(13, FUNC16(entry_75));
78 // INT 75 - IRQ13 - MATH COPROCESSOR EXCEPTION
82 debug_isr(DEBUG_ISR_75);
85 outb(0, PORT_MATH_CLEAR);
90 memset(&br, 0, sizeof(br));
92 call16_int(0x02, &br);
96 /****************************************************************
98 ****************************************************************/
100 // DMA channel 3 used by hard disk BIOS
101 #define CBT_F1_DMA3USED (1<<7)
102 // 2nd interrupt controller (8259) installed
103 #define CBT_F1_2NDPIC (1<<6)
104 // Real-Time Clock installed
105 #define CBT_F1_RTC (1<<5)
106 // INT 15/AH=4Fh called upon INT 09h
107 #define CBT_F1_INT154F (1<<4)
108 // wait for external event (INT 15/AH=41h) supported
109 #define CBT_F1_WAITEXT (1<<3)
110 // extended BIOS area allocated (usually at top of RAM)
111 #define CBT_F1_EBDA (1<<2)
112 // bus is Micro Channel instead of ISA
113 #define CBT_F1_MCA (1<<1)
114 // system has dual bus (Micro Channel + ISA)
115 #define CBT_F1_MCAISA (1<<0)
117 // INT 16/AH=09h (keyboard functionality) supported
118 #define CBT_F2_INT1609 (1<<6)
120 struct bios_config_table_s BIOS_CONFIG_TABLE VARFSEGFIXED(0xe6f5) = {
121 .size = sizeof(BIOS_CONFIG_TABLE) - 2,
122 .model = BUILD_MODEL_ID,
123 .submodel = BUILD_SUBMODEL_ID,
124 .biosrev = BUILD_BIOS_REVISION,
126 CBT_F1_2NDPIC | CBT_F1_RTC | CBT_F1_EBDA
127 | (CONFIG_KBD_CALL_INT15_4F ? CBT_F1_INT154F : 0)),
128 .feature2 = CBT_F2_INT1609,
135 /****************************************************************
137 ****************************************************************/
139 // Real mode IDT descriptor
140 struct descloc_s rmode_IDT_info VARFSEG = {
141 .length = sizeof(struct rmode_IVT) - 1,
142 .addr = (u32)MAKE_FLATPTR(SEG_IVT, 0),
145 // Dummy IDT that forces a machine shutdown if an irq happens in
147 u8 dummy_IDT VARFSEG;
149 // Protected mode IDT descriptor
150 struct descloc_s pmode_IDT_info VARFSEG = {
151 .length = sizeof(dummy_IDT) - 1,
152 .addr = (u32)&dummy_IDT,
156 u64 rombios32_gdt[] VARFSEG __aligned(8) = {
157 // First entry can't be used.
158 0x0000000000000000LL,
159 // 32 bit flat code segment (SEG32_MODE32_CS)
160 GDT_GRANLIMIT(0xffffffff) | GDT_CODE | GDT_B,
161 // 32 bit flat data segment (SEG32_MODE32_DS)
162 GDT_GRANLIMIT(0xffffffff) | GDT_DATA | GDT_B,
163 // 16 bit code segment base=0xf0000 limit=0xffff (SEG32_MODE16_CS)
164 GDT_LIMIT(BUILD_BIOS_SIZE-1) | GDT_CODE | GDT_BASE(BUILD_BIOS_ADDR),
165 // 16 bit data segment base=0x0 limit=0xffff (SEG32_MODE16_DS)
166 GDT_LIMIT(0x0ffff) | GDT_DATA,
167 // 16 bit code segment base=0xf0000 limit=0xffffffff (SEG32_MODE16BIG_CS)
168 GDT_GRANLIMIT(0xffffffff) | GDT_CODE | GDT_BASE(BUILD_BIOS_ADDR),
169 // 16 bit data segment base=0 limit=0xffffffff (SEG32_MODE16BIG_DS)
170 GDT_GRANLIMIT(0xffffffff) | GDT_DATA,
174 struct descloc_s rombios32_gdt_48 VARFSEG = {
175 .length = sizeof(rombios32_gdt) - 1,
176 .addr = (u32)rombios32_gdt,
180 /****************************************************************
182 ****************************************************************/
185 char BiosDate[] VARFSEGFIXED(0xfff5) = "06/23/99";
187 u8 BiosModelId VARFSEGFIXED(0xfffe) = BUILD_MODEL_ID;
189 u8 BiosChecksum VARFSEGFIXED(0xffff);
191 struct floppy_dbt_s diskette_param_table VARFSEGFIXED(0xefc7);
193 // Old Fixed Disk Parameter Table (newer tables are in the ebda).
194 struct fdpt_s OldFDPT VARFSEGFIXED(0xe401);
196 // XXX - Baud Rate Generator Table
197 u8 BaudTable[16] VARFSEGFIXED(0xe729);
199 // XXX - Initial Interrupt Vector Offsets Loaded by POST
200 u8 InitVectors[13] VARFSEGFIXED(0xfef3);
202 // XXX - INT 1D - SYSTEM DATA - VIDEO PARAMETER TABLES
203 u8 VideoParams[88] VARFSEGFIXED(0xf0a4);