1 // Code for handling EHCI USB controllers.
3 // Copyright (C) 2010-2013 Kevin O'Connor <kevin@koconnor.net>
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
7 #include "biosvar.h" // GET_LOWFLAT
8 #include "config.h" // CONFIG_*
9 #include "output.h" // dprintf
10 #include "malloc.h" // free
11 #include "memmap.h" // PAGE_SIZE
12 #include "pci.h" // pci_bdf_to_bus
13 #include "pci_ids.h" // PCI_CLASS_SERIAL_USB_UHCI
14 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
15 #include "string.h" // memset
16 #include "usb.h" // struct usb_s
17 #include "usb-ehci.h" // struct ehci_qh
18 #include "util.h" // msleep
19 #include "x86.h" // readl
23 struct ehci_caps *caps;
24 struct ehci_regs *regs;
25 struct ehci_qh *async_qh;
31 struct ehci_qtd *next_td, *tds;
36 static int PendingEHCI;
39 /****************************************************************
41 ****************************************************************/
43 #define EHCI_TIME_POSTPOWER 20
44 #define EHCI_TIME_POSTRESET 2
46 // Check if device attached to port
48 ehci_hub_detect(struct usbhub_s *hub, u32 port)
50 struct usb_ehci_s *cntl = container_of(hub->cntl, struct usb_ehci_s, usb);
51 u32 *portreg = &cntl->regs->portsc[port];
52 u32 portsc = readl(portreg);
54 if (!(portsc & PORT_CONNECT))
58 if ((portsc & PORT_LINESTATUS_MASK) == PORT_LINESTATUS_KSTATE) {
60 writel(portreg, portsc | PORT_OWNER);
64 // XXX - if just powered up, need to wait for USB_TIME_ATTDB?
66 // Begin reset on port
67 portsc = (portsc & ~PORT_PE) | PORT_RESET;
68 writel(portreg, portsc);
69 msleep(USB_TIME_DRSTR);
73 // Reset device on port
75 ehci_hub_reset(struct usbhub_s *hub, u32 port)
77 struct usb_ehci_s *cntl = container_of(hub->cntl, struct usb_ehci_s, usb);
78 u32 *portreg = &cntl->regs->portsc[port];
79 u32 portsc = readl(portreg);
81 // Finish reset on port
82 portsc &= ~PORT_RESET;
83 writel(portreg, portsc);
84 msleep(EHCI_TIME_POSTRESET);
86 portsc = readl(portreg);
87 if (!(portsc & PORT_CONNECT))
88 // No longer connected
90 if (!(portsc & PORT_PE)) {
92 writel(portreg, portsc | PORT_OWNER);
101 ehci_hub_disconnect(struct usbhub_s *hub, u32 port)
103 struct usb_ehci_s *cntl = container_of(hub->cntl, struct usb_ehci_s, usb);
104 u32 *portreg = &cntl->regs->portsc[port];
105 u32 portsc = readl(portreg);
106 writel(portreg, portsc & ~PORT_PE);
109 static struct usbhub_op_s ehci_HubOp = {
110 .detect = ehci_hub_detect,
111 .reset = ehci_hub_reset,
112 .disconnect = ehci_hub_disconnect,
115 // Find any devices connected to the root hub.
117 check_ehci_ports(struct usb_ehci_s *cntl)
121 for (i=0; i<cntl->checkports; i++) {
122 u32 *portreg = &cntl->regs->portsc[i];
123 u32 portsc = readl(portreg);
124 if (!(portsc & PORT_POWER)) {
125 portsc |= PORT_POWER;
126 writel(portreg, portsc);
129 msleep(EHCI_TIME_POSTPOWER);
132 memset(&hub, 0, sizeof(hub));
133 hub.cntl = &cntl->usb;
134 hub.portcount = cntl->checkports;
135 hub.op = &ehci_HubOp;
141 /****************************************************************
143 ****************************************************************/
145 // Wait for next USB async frame to start - for ensuring safe memory release.
147 ehci_waittick(struct usb_ehci_s *cntl)
153 // Wait for access to "doorbell"
156 u32 end = timer_calc(100);
158 sts = readl(&cntl->regs->usbsts);
159 if (!(sts & STS_IAA)) {
160 cmd = readl(&cntl->regs->usbcmd);
161 if (!(cmd & CMD_IAAD))
164 if (timer_check(end)) {
171 writel(&cntl->regs->usbcmd, cmd | CMD_IAAD);
172 // Wait for completion
174 sts = readl(&cntl->regs->usbsts);
177 if (timer_check(end)) {
184 writel(&cntl->regs->usbsts, STS_IAA);
188 ehci_free_pipes(struct usb_ehci_s *cntl)
190 dprintf(7, "ehci_free_pipes %p\n", cntl);
192 struct ehci_qh *start = cntl->async_qh;
193 struct ehci_qh *pos = start;
195 struct ehci_qh *next = (void*)(pos->next & ~EHCI_PTR_BITS);
198 struct ehci_pipe *pipe = container_of(next, struct ehci_pipe, qh);
199 if (usb_is_freelist(&cntl->usb, &pipe->pipe))
200 pos->next = next->next;
206 struct usb_pipe *usbpipe = cntl->usb.freelist;
209 cntl->usb.freelist = usbpipe->freenext;
210 struct ehci_pipe *pipe = container_of(usbpipe, struct ehci_pipe, pipe);
216 configure_ehci(void *data)
218 struct usb_ehci_s *cntl = data;
220 // Allocate ram for schedule storage
221 struct ehci_framelist *fl = memalign_high(sizeof(*fl), sizeof(*fl));
222 struct ehci_qh *intr_qh = memalign_high(EHCI_QH_ALIGN, sizeof(*intr_qh));
223 struct ehci_qh *async_qh = memalign_high(EHCI_QH_ALIGN, sizeof(*async_qh));
224 if (!fl || !intr_qh || !async_qh) {
230 // XXX - check for halted?
233 u32 cmd = readl(&cntl->regs->usbcmd);
234 writel(&cntl->regs->usbcmd, (cmd & ~(CMD_ASE | CMD_PSE)) | CMD_HCRESET);
235 u32 end = timer_calc(250);
237 cmd = readl(&cntl->regs->usbcmd);
238 if (!(cmd & CMD_HCRESET))
240 if (timer_check(end)) {
248 // Disable interrupts (just to be safe).
249 writel(&cntl->regs->usbintr, 0);
251 // Set schedule to point to primary intr queue head
252 memset(intr_qh, 0, sizeof(*intr_qh));
253 intr_qh->next = EHCI_PTR_TERM;
254 intr_qh->info2 = (0x01 << QH_SMASK_SHIFT);
255 intr_qh->token = QTD_STS_HALT;
256 intr_qh->qtd_next = intr_qh->alt_next = EHCI_PTR_TERM;
258 for (i=0; i<ARRAY_SIZE(fl->links); i++)
259 fl->links[i] = (u32)intr_qh | EHCI_PTR_QH;
260 writel(&cntl->regs->periodiclistbase, (u32)fl);
262 // Set async list to point to primary async queue head
263 memset(async_qh, 0, sizeof(*async_qh));
264 async_qh->next = (u32)async_qh | EHCI_PTR_QH;
265 async_qh->info1 = QH_HEAD;
266 async_qh->token = QTD_STS_HALT;
267 async_qh->qtd_next = async_qh->alt_next = EHCI_PTR_TERM;
268 cntl->async_qh = async_qh;
269 writel(&cntl->regs->asynclistbase, (u32)async_qh);
272 writel(&cntl->regs->usbcmd, cmd | CMD_ASE | CMD_PSE | CMD_RUN);
274 // Set default of high speed for root hub.
275 writel(&cntl->regs->configflag, 1);
279 int count = check_ehci_ports(cntl);
280 ehci_free_pipes(cntl);
285 // No devices found - shutdown and free controller.
286 writel(&cntl->regs->usbcmd, cmd & ~CMD_RUN);
287 msleep(4); // 2ms to stop reading memory - XXX
296 ehci_controller_setup(struct pci_device *pci)
298 wait_preempt(); // Avoid pci_config_readl when preempting
300 u32 baseaddr = pci_config_readl(bdf, PCI_BASE_ADDRESS_0);
301 struct ehci_caps *caps = (void*)(baseaddr & PCI_BASE_ADDRESS_MEM_MASK);
302 u32 hcc_params = readl(&caps->hccparams);
304 struct usb_ehci_s *cntl = malloc_tmphigh(sizeof(*cntl));
309 memset(cntl, 0, sizeof(*cntl));
311 cntl->usb.type = USB_TYPE_EHCI;
313 cntl->checkports = readl(&cntl->caps->hcsparams) & HCS_N_PORTS_MASK;
314 cntl->regs = (void*)caps + readb(&caps->caplength);
315 if (hcc_params & HCC_64BIT_ADDR)
316 cntl->regs->ctrldssegment = 0;
319 dprintf(1, "EHCI init on dev %02x:%02x.%x (regs=%p)\n"
320 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf)
321 , pci_bdf_to_fn(bdf), cntl->regs);
323 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_MASTER);
325 // XXX - check for and disable SMM control?
327 run_thread(configure_ehci, cntl);
333 if (! CONFIG_USB_EHCI)
335 struct pci_device *pci;
337 if (pci_classprog(pci) == PCI_CLASS_SERIAL_USB_EHCI)
338 ehci_controller_setup(pci);
341 // Wait for all EHCI controllers to initialize. This forces OHCI/UHCI
342 // setup to always be after any EHCI ports are routed to EHCI.
348 /****************************************************************
349 * End point communication
350 ****************************************************************/
352 // Setup fields in qh
354 ehci_desc2pipe(struct ehci_pipe *pipe, struct usbdevice_s *usbdev
355 , struct usb_endpoint_descriptor *epdesc)
357 usb_desc2pipe(&pipe->pipe, usbdev, epdesc);
359 pipe->qh.info1 = ((pipe->pipe.maxpacket << QH_MAXPACKET_SHIFT)
360 | (pipe->pipe.speed << QH_SPEED_SHIFT)
361 | (pipe->pipe.ep << QH_EP_SHIFT)
362 | (pipe->pipe.devaddr << QH_DEVADDR_SHIFT));
364 pipe->qh.info2 = (1 << QH_MULT_SHIFT);
365 struct usbdevice_s *hubdev = usbdev->hub->usbdev;
367 struct ehci_pipe *hpipe = container_of(
368 hubdev->defpipe, struct ehci_pipe, pipe);
369 if (hpipe->pipe.speed == USB_HIGHSPEED)
370 pipe->qh.info2 |= (((usbdev->port+1) << QH_HUBPORT_SHIFT)
371 | (hpipe->pipe.devaddr << QH_HUBADDR_SHIFT));
373 pipe->qh.info2 = hpipe->qh.info2;
376 u8 eptype = epdesc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
377 if (eptype == USB_ENDPOINT_XFER_CONTROL)
378 pipe->qh.info1 |= ((pipe->pipe.speed != USB_HIGHSPEED ? QH_CONTROL : 0)
380 else if (eptype == USB_ENDPOINT_XFER_INT)
381 pipe->qh.info2 |= (0x01 << QH_SMASK_SHIFT) | (0x1c << QH_CMASK_SHIFT);
384 static struct usb_pipe *
385 ehci_alloc_intr_pipe(struct usbdevice_s *usbdev
386 , struct usb_endpoint_descriptor *epdesc)
388 struct usb_ehci_s *cntl = container_of(
389 usbdev->hub->cntl, struct usb_ehci_s, usb);
390 int frameexp = usb_get_period(usbdev, epdesc);
391 dprintf(7, "ehci_alloc_intr_pipe %p %d\n", &cntl->usb, frameexp);
395 int maxpacket = epdesc->wMaxPacketSize;
396 // Determine number of entries needed for 2 timer ticks.
397 int ms = 1<<frameexp;
398 int count = DIV_ROUND_UP(ticks_to_ms(2), ms);
399 struct ehci_pipe *pipe = memalign_low(EHCI_QH_ALIGN, sizeof(*pipe));
400 struct ehci_qtd *tds = memalign_low(EHCI_QTD_ALIGN, sizeof(*tds) * count);
401 void *data = malloc_low(maxpacket * count);
402 if (!pipe || !tds || !data) {
406 memset(pipe, 0, sizeof(*pipe));
407 memset(tds, 0, sizeof(*tds) * count);
408 memset(data, 0, maxpacket * count);
409 ehci_desc2pipe(pipe, usbdev, epdesc);
410 pipe->next_td = pipe->tds = tds;
412 pipe->qh.qtd_next = (u32)tds;
415 for (i=0; i<count; i++) {
416 struct ehci_qtd *td = &tds[i];
417 td->qtd_next = (i==count-1 ? (u32)tds : (u32)&td[1]);
418 td->alt_next = EHCI_PTR_TERM;
419 td->token = (ehci_explen(maxpacket) | QTD_STS_ACTIVE
420 | QTD_PID_IN | ehci_maxerr(3));
421 td->buf[0] = (u32)data + maxpacket * i;
424 // Add to interrupt schedule.
425 struct ehci_framelist *fl = (void*)readl(&cntl->regs->periodiclistbase);
427 // Add to existing interrupt entry.
428 struct ehci_qh *intr_qh = (void*)(fl->links[0] & ~EHCI_PTR_BITS);
429 pipe->qh.next = intr_qh->next;
431 intr_qh->next = (u32)&pipe->qh | EHCI_PTR_QH;
433 int startpos = 1<<(frameexp-1);
434 pipe->qh.next = fl->links[startpos];
436 for (i=startpos; i<ARRAY_SIZE(fl->links); i+=ms)
437 fl->links[i] = (u32)&pipe->qh | EHCI_PTR_QH;
449 ehci_realloc_pipe(struct usbdevice_s *usbdev, struct usb_pipe *upipe
450 , struct usb_endpoint_descriptor *epdesc)
452 if (! CONFIG_USB_EHCI)
454 usb_add_freelist(upipe);
457 u8 eptype = epdesc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
458 if (eptype == USB_ENDPOINT_XFER_INT)
459 return ehci_alloc_intr_pipe(usbdev, epdesc);
460 struct usb_ehci_s *cntl = container_of(
461 usbdev->hub->cntl, struct usb_ehci_s, usb);
462 dprintf(7, "ehci_alloc_async_pipe %p %d\n", &cntl->usb, eptype);
464 struct usb_pipe *usbpipe = usb_get_freelist(&cntl->usb, eptype);
466 // Use previously allocated pipe.
467 struct ehci_pipe *pipe = container_of(usbpipe, struct ehci_pipe, pipe);
468 ehci_desc2pipe(pipe, usbdev, epdesc);
472 // Allocate a new queue head.
473 struct ehci_pipe *pipe;
474 if (eptype == USB_ENDPOINT_XFER_CONTROL)
475 pipe = memalign_tmphigh(EHCI_QH_ALIGN, sizeof(*pipe));
477 pipe = memalign_low(EHCI_QH_ALIGN, sizeof(*pipe));
482 memset(pipe, 0, sizeof(*pipe));
483 ehci_desc2pipe(pipe, usbdev, epdesc);
484 pipe->qh.qtd_next = pipe->qh.alt_next = EHCI_PTR_TERM;
486 // Add queue head to controller list.
487 struct ehci_qh *async_qh = cntl->async_qh;
488 pipe->qh.next = async_qh->next;
490 async_qh->next = (u32)&pipe->qh | EHCI_PTR_QH;
495 ehci_reset_pipe(struct ehci_pipe *pipe)
497 SET_LOWFLAT(pipe->qh.qtd_next, EHCI_PTR_TERM);
498 SET_LOWFLAT(pipe->qh.alt_next, EHCI_PTR_TERM);
500 SET_LOWFLAT(pipe->qh.token, GET_LOWFLAT(pipe->qh.token) & QTD_TOGGLE);
504 ehci_wait_td(struct ehci_pipe *pipe, struct ehci_qtd *td, u32 end)
509 if (!(status & QTD_STS_ACTIVE))
511 if (timer_check(end)) {
512 u32 cur = GET_LOWFLAT(pipe->qh.current);
513 u32 tok = GET_LOWFLAT(pipe->qh.token);
514 u32 next = GET_LOWFLAT(pipe->qh.qtd_next);
516 dprintf(1, "ehci pipe=%p cur=%08x tok=%08x next=%x td=%p status=%x\n"
517 , pipe, cur, tok, next, td, status);
518 ehci_reset_pipe(pipe);
519 struct usb_ehci_s *cntl = container_of(
520 GET_LOWFLAT(pipe->pipe.cntl), struct usb_ehci_s, usb);
526 if (status & QTD_STS_HALT) {
527 dprintf(1, "ehci_wait_td error - status=%x\n", status);
528 ehci_reset_pipe(pipe);
535 ehci_fill_tdbuf(struct ehci_qtd *td, u32 dest, int transfer)
537 u32 *pos = td->buf, end = dest + transfer;
538 for (; dest < end; dest = ALIGN_DOWN(dest + PAGE_SIZE, PAGE_SIZE))
545 ehci_send_pipe(struct usb_pipe *p, int dir, const void *cmd
546 , void *data, int datasize)
548 if (! CONFIG_USB_EHCI)
550 struct ehci_pipe *pipe = container_of(p, struct ehci_pipe, pipe);
551 dprintf(7, "ehci_send_pipe qh=%p dir=%d data=%p size=%d\n"
552 , &pipe->qh, dir, data, datasize);
554 // Allocate tds on stack (with required alignment)
555 u8 tdsbuf[sizeof(struct ehci_qtd) * STACKQTDS + EHCI_QTD_ALIGN - 1];
556 struct ehci_qtd *tds = (void*)ALIGN((u32)tdsbuf, EHCI_QTD_ALIGN), *td = tds;
557 memset(tds, 0, sizeof(*tds) * STACKQTDS);
559 // Setup transfer descriptors
560 u16 maxpacket = GET_LOWFLAT(pipe->pipe.maxpacket);
563 // Send setup pid on control transfers
564 td->qtd_next = (u32)MAKE_FLATPTR(GET_SEG(SS), td+1);
565 td->alt_next = EHCI_PTR_TERM;
566 td->token = (ehci_explen(USB_CONTROL_SETUP_SIZE) | QTD_STS_ACTIVE
567 | QTD_PID_SETUP | ehci_maxerr(3));
568 ehci_fill_tdbuf(td, (u32)cmd, USB_CONTROL_SETUP_SIZE);
572 u32 dest = (u32)data, dataend = dest + datasize;
573 while (dest < dataend) {
575 if (td >= &tds[STACKQTDS]) {
579 int maxtransfer = 5*PAGE_SIZE - (dest & (PAGE_SIZE-1));
580 int transfer = dataend - dest;
581 if (transfer > maxtransfer)
582 transfer = ALIGN_DOWN(maxtransfer, maxpacket);
583 td->qtd_next = (u32)MAKE_FLATPTR(GET_SEG(SS), td+1);
584 td->alt_next = EHCI_PTR_TERM;
585 td->token = (ehci_explen(transfer) | toggle | QTD_STS_ACTIVE
586 | (dir ? QTD_PID_IN : QTD_PID_OUT) | ehci_maxerr(3));
587 ehci_fill_tdbuf(td, dest, transfer);
592 // Send status pid on control transfers
593 if (td >= &tds[STACKQTDS]) {
597 td->qtd_next = EHCI_PTR_TERM;
598 td->alt_next = EHCI_PTR_TERM;
599 td->token = (QTD_TOGGLE | QTD_STS_ACTIVE
600 | (dir ? QTD_PID_OUT : QTD_PID_IN) | ehci_maxerr(3));
605 (td-1)->qtd_next = EHCI_PTR_TERM;
607 SET_LOWFLAT(pipe->qh.qtd_next, (u32)MAKE_FLATPTR(GET_SEG(SS), tds));
608 u32 end = timer_calc(usb_xfer_time(p, datasize));
610 for (i=0, td=tds; i<STACKQTDS; i++, td++) {
611 int ret = ehci_wait_td(pipe, td, end);
620 ehci_poll_intr(struct usb_pipe *p, void *data)
623 if (! CONFIG_USB_EHCI)
625 struct ehci_pipe *pipe = container_of(p, struct ehci_pipe, pipe);
626 struct ehci_qtd *td = GET_LOWFLAT(pipe->next_td);
627 u32 token = GET_LOWFLAT(td->token);
628 if (token & QTD_STS_ACTIVE)
631 // XXX - check for errors.
634 int maxpacket = GET_LOWFLAT(pipe->pipe.maxpacket);
635 int pos = td - GET_LOWFLAT(pipe->tds);
636 void *tddata = GET_LOWFLAT(pipe->data) + maxpacket * pos;
637 memcpy_far(GET_SEG(SS), data, SEG_LOW, LOWFLAT2LOW(tddata), maxpacket);
640 struct ehci_qtd *next = (void*)(GET_LOWFLAT(td->qtd_next) & ~EHCI_PTR_BITS);
641 SET_LOWFLAT(pipe->next_td, next);
642 SET_LOWFLAT(td->buf[0], (u32)tddata);
644 SET_LOWFLAT(td->token, (ehci_explen(maxpacket) | QTD_STS_ACTIVE
645 | QTD_PID_IN | ehci_maxerr(3)));