2 * Creation Date: <2000/10/29 01:43:29 samuel>
3 * Time-stamp: <2003/07/27 22:37:49 samuel>
7 * Extract from <asm/processor.h>
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation
20 #define PTE0_VSID(s) (((s)>>7) & 0xffffff)
22 #define PTE0_H BIT(25)
25 #define PTE1_R BIT(23)
26 #define PTE1_C BIT(24)
27 #define PTE1_W BIT(25)
28 #define PTE1_I BIT(26)
29 #define PTE1_M BIT(27)
30 #define PTE1_G BIT(28)
31 #define PTE1_WIMG (PTE1_W | PTE1_I | PTE1_M | PTE1_G)
33 #define PTE1_RPN (~0xfffUL)
35 #define VSID_Ks BIT(1)
36 #define VSID_Kp BIT(2)
43 #define MSR_SF (1 << 63) /* Sixty-Four Bit Mode */
45 #define MSR_VEC (1<<25) /* 6: Enable AltiVec */
46 #define MSR_POW (1<<18) /* 13: Enable Power Management */
47 #define MSR_TGPR (1<<17) /* 14: TLB Update registers in use */
48 #define MSR_ILE (1<<16) /* 15: Interrupt Little Endian */
49 #define MSR_EE (1<<15) /* 16: External Interrupt Enable */
50 #define MSR_PR (1<<14) /* 17: Privilege Level */
51 #define MSR_FP (1<<13) /* 18: Floating Point enable */
52 #define MSR_ME (1<<12) /* 19: Machine Check Enable */
53 #define MSR_FE0 (1<<11) /* 20: Floating Exception mode 0 */
54 #define MSR_SE (1<<10) /* 21: Single Step */
55 #define MSR_BE (1<<9) /* 22: Branch Trace */
56 #define MSR_FE1 (1<<8) /* 23: Floating Exception mode 1 */
57 #define MSR_IP (1<<6) /* 25: Exception prefix 0x000/0xFFF */
58 #define MSR_IR (1<<5) /* 26: Instruction Relocate */
59 #define MSR_DR (1<<4) /* 27: Data Relocate */
60 #define MSR_PE (1<<2) /* 29: Performance Monitor Flag */
61 #define MSR_RI (1<<1) /* 30: Recoverable Exception */
62 #define MSR_LE (1<<0) /* 31: Little Endian */
70 #define S_RTCU_R 4 /* 601 RTC Upper/Lower (Reading) */
74 #define S_DSISR 18 /* Source Instruction Service Register */
75 #define S_DAR 19 /* Data Address Register */
76 #define S_RTCU_W 20 /* 601 RTC Upper/Lower (Writing) */
78 #define S_DEC 22 /* Decrementer Register */
79 #define S_SDR1 25 /* Table Search Description Register */
80 #define S_SRR0 26 /* Save and Restore Register 0 */
81 #define S_SRR1 27 /* Save and Restore Register 1 */
82 #define S_VRSAVE 256 /* (AltiVec) Vector Register Save Register */
83 #define S_TBRL 268 /* Time base Upper/Lower (Reading) */
85 #define S_SPRG0 272 /* SPR General 0-3 */
89 #define S_SPRG4 276 /* SPR General 4-7 (7445/7455) */
93 #define S_EAR 282 /* External Access Register */
94 #define S_TBWL 284 /* Time base Upper/Lower (Writing) */
96 #define S_PVR 287 /* Processor Version Register */
97 #define S_HIOR 311 /* Hardware Interrupt Offset Register */
115 #define S_UPMC5 929 /* User Performance Monitor Counter Register */
118 #define S_UMMCR0 936 /* User Monitor Mode Control Register */
121 #define S_USIAR 939 /* User Sampled Instruction Address Register */
124 #define S_UPMC4 942 /* User Performance Monitor Counter Register 4 */
125 #define S_USDAR 943 /* User Sampled Data Address Register */
126 #define S_MMCR2 944 /* Monitor Mode Control Register */
129 #define S_BAMR 951 /* Breakpoint Address Mask Register (74xx) */
130 #define S_MMCR0 952 /* Monitor Mode Control Register 0 */
131 #define S_PMC1 953 /* Performance Counter Register */
133 #define S_SIAR 955 /* Sampled Instruction Address Register */
137 #define S_SDAR 959 /* Sampled Data Address Register */
138 #define S_DMISS 976 /* 603 */
139 #define S_DCMP 977 /* 603 */
140 #define S_HASH1 978 /* 603 */
141 #define S_HASH2 979 /* 603 */
142 #define S_IMISS 980 /* 603 */
143 #define S_TLBMISS 980 /* 7445/7455 */
144 #define S_ICMP 981 /* 603 */
145 #define S_PTEHI 981 /* 7445/7455 */
146 #define S_RPA 982 /* 603 */
147 #define S_PTELO 982 /* 7445/7455 */
148 #define S_L3PM 983 /* L3 Private Memory Address Control Register */
149 #define S_L3ITCR0 984 /* ??? */
150 #define S_L3OHCR 1000 /* ??? */
151 #define S_L3ITCR1 1001 /* ??? */
152 #define S_L3ITCR2 1002 /* ??? */
153 #define S_L3ITCR3 1003 /* ??? */
154 #define S_HID0 1008 /* Hardware Implementation Registers */
157 #define S_IABR S_HID2 /* HID2 - Instruction Address Breakpoint Register */
158 #define S_ICTRL 1011 /* HID3 - Instruction Cache & Interrupt control reg */
159 #define S_HID4 1012 /* HID4 - Instruction Address Compare 1 (?) */
161 #define S_DABR S_HID5 /* HID5 - Data Address Breakpoint */
162 #define S_MSSCR0 1014 /* HID6 - Memory Subsystem Control Register 0 */
163 #define S_MSSCR1 1015 /* HID7 - Memory Subsystem Control Register 1 */
164 #define S_LDSTCR 1016 /* HID8 - Load/Store Control Register */
165 #define S_L2CR 1017 /* HID9 - Level 2 Cache Control Regsiter */
166 #define S_L3CR 1018 /* HID10 - Level 3 Cache Control Regsiter (7450) */
168 #define S_ICTC S_HID11 /* HID11 - Instruction Cache Throttling Control Reg */
169 #define S_ICCR S_HID11 /* Instruction Cache Cacheability Reigster */
170 #define S_THRM1 1020 /* HID12 - Thermal Management Register 1 */
171 #define S_THRM2 1021 /* HID13 - Thermal Management Register 2 */
172 #define S_THRM3 1022 /* HID14 - Thermal Management Register 3 */
174 #define S_PIR S_HID15 /* HID15 - Processor Identification Register */
178 /* the kernel might define these too... */
179 #if !defined(__KERNEL__) || defined(__ASSEMBLY__)
181 /* Floating Point Status and Control Register (FPSCR) Fields */
182 #define FPSCR_FX 0x80000000 /* FPU exception summary */
183 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
184 #define FPSCR_VX 0x20000000 /* Invalid operation summary */
185 #define FPSCR_OX 0x10000000 /* Overflow exception summary */
186 #define FPSCR_UX 0x08000000 /* Underflow exception summary */
187 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
188 #define FPSCR_XX 0x02000000 /* Inexact exception summary */
189 #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
190 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
191 #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
192 #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
193 #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
194 #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
195 #define FPSCR_FR 0x00040000 /* Fraction rounded */
196 #define FPSCR_FI 0x00020000 /* Fraction inexact */
197 #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
198 #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
199 #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
200 #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
201 #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
202 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
203 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
204 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
205 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
206 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
207 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
208 #define FPSCR_RN 0x00000003 /* FPU rounding control */
211 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
212 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
213 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
214 #define HID0_SBCLK (1<<27)
215 #define HID0_EICE (1<<26)
216 #define HID0_ECLK (1<<25)
217 #define HID0_PAR (1<<24)
218 #define HID0_DOZE (1<<23)
219 #define HID0_NAP (1<<22)
220 #define HID0_SLEEP (1<<21)
221 #define HID0_DPM (1<<20)
222 #define HID0_NHR (1<<16) /* Not Hard Reset */
223 #define HID0_ICE (1<<15) /* Instruction Cache Enable */
224 #define HID0_DCE (1<<14) /* Data Cache Enable */
225 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
226 #define HID0_DLOCK (1<<12) /* Data Cache Lock */
227 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
228 #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
229 #define HID0_SPD (1<<9) /* Speculative disable */
230 #define HID0_SGE (1<<7) /* Store Gathering Enable */
231 #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
232 #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
233 #define HID0_ABE (1<<3) /* Address Broadcast Enable */
234 #define HID0_BHT (1<<2) /* Branch History Table Enable */
235 #define HID0_BTCD (1<<1) /* Branch target cache disable */
237 #define L2CR_L2E BIT(0) /* L2 enable */
238 #define L2CR_L2PE BIT(1) /* L2 data parity generation and checking */
239 #define L2CR_L2SIZ_512K BIT(2)
240 #define L2CR_L2SIZ_256K BIT(3)
241 #define L2CR_L2SIZ_1MB (BIT(2)|BIT(3))
242 #define L2CR_L2CLK_1 BIT(6) /* L2 clock ration */
243 #define L2CR_L2CLK_15 (BIT(6)*2)
244 #define L2CR_L2CLK_2 (BIT(6)*4)
245 #define L2CR_L2CLK_25 (BIT(6)*5)
246 #define L2CR_L2CLK_3 (BIT(6)*6)
247 #define L2CR_L2RAM_FT 0 /* flow-through (reg-buf) synchronous SRAM */
248 #define L2CR_L2RAM_PB BIT(7) /* Piplined (reg-reg) synchronous burst SRAM */
249 #define L2CR_L2RAM_PLW (BIT(7)|BIT(8)) /* Piplined (reg-reg) synchronous late-write */
250 #define L2CR_L2DO BIT(9) /* L2 data-only */
251 #define L2CR_L2I BIT(10) /* L2 global invalidate */
252 #define L2CR_L2CTL BIT(11) /* L2 RAM control (ZZ enable, low-power mode) */
253 #define L2CR_L2WT BIT(12) /* L2 write-through */
254 #define L2CR_L2TS BIT(13) /* L2 test support */
255 #define L2CR_L2OH_05 0 /* L2 output hold 0.5 nS */
256 #define L2CR_L2OH_10 BIT(15) /* L2 output hold 1.0 nS */
257 #define L2CR_L2SL BIT(16) /* L2 DLL slow (use if bus freq < 150 MHz) */
258 #define L2CR_L2DF BIT(17) /* L2 differential clock */
259 #define L2CR_L2BYP BIT(18) /* L2 DLL bypass */
260 #define L2CR_L2IP BIT(31) /* L2 global invalidate in progress */
263 #define THRM1_TIN (1 << 31)
264 #define THRM1_TIV (1 << 30)
265 #define THRM1_THRES(x) ((x&0x7f)<<23)
266 #define THRM3_SITV(x) ((x&0x3fff)<<1)
267 #define THRM1_TID (1<<2)
268 #define THRM1_TIE (1<<1)
269 #define THRM1_V (1<<0)
272 #define THRM3_E (1<<0)
274 /* Processor Version Numbers */
276 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
277 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
279 #define PVR_403GA 0x00200000
280 #define PVR_403GB 0x00200100
281 #define PVR_403GC 0x00200200
282 #define PVR_403GCX 0x00201400
283 #define PVR_405GP 0x40110000
284 #define PVR_601 0x00010000
285 #define PVR_602 0x00050000
286 #define PVR_603 0x00030000
287 #define PVR_603e 0x00060000
288 #define PVR_603ev 0x00070000
289 #define PVR_603r 0x00071000
290 #define PVR_604 0x00040000
291 #define PVR_604e 0x00090000
292 #define PVR_604r 0x000A0000
293 #define PVR_620 0x00140000
294 #define PVR_740 0x00080000
295 #define PVR_750 PVR_740
296 #define PVR_740P 0x10080000
297 #define PVR_750P PVR_740P
298 #define PVR_821 0x00500000
299 #define PVR_823 PVR_821
300 #define PVR_850 PVR_821
301 #define PVR_860 PVR_821
302 #define PVR_7400 0x000C0000
303 #define PVR_8240 0x00810100
304 #define PVR_8260 PVR_8240
306 /* Vector VSCR register */
307 #define VSCR_NJ 0x10000
310 #endif /* __KERNEL__ */
315 #define CTR S_CTR /* Counter Register */
316 #define DAR S_DAR /* Data Address Register */
317 #define DABR S_DABR /* Data Address Breakpoint Register */
318 #define DBAT0L S_DBAT0L /* Data BAT 0 Lower Register */
319 #define DBAT0U S_DBAT0U /* Data BAT 0 Upper Register */
320 #define DBAT1L S_DBAT1L /* Data BAT 1 Lower Register */
321 #define DBAT1U S_DBAT1U /* Data BAT 1 Upper Register */
322 #define DBAT2L S_DBAT2L /* Data BAT 2 Lower Register */
323 #define DBAT2U S_DBAT2U /* Data BAT 2 Upper Register */
324 #define DBAT3L S_DBAT3L /* Data BAT 3 Lower Register */
325 #define DBAT3U S_DBAT3U /* Data BAT 3 Upper Register */
326 #define DCMP S_DCMP /* Data TLB Compare Register */
327 #define DEC S_DEC /* Decrement Register */
328 #define DMISS S_DMISS /* Data TLB Miss Register */
329 #define DSISR S_DSISR /* Data Storage Interrupt Status Register */
330 #define EAR S_EAR /* External Address Register */
331 #define HASH1 S_HASH1 /* Primary Hash Address Register */
332 #define HASH2 S_HASH2 /* Secondary Hash Address Register */
333 #define HID0 S_HID0 /* Hardware Implementation Register 0 */
334 #define HID1 S_HID1 /* Hardware Implementation Register 1 */
335 #define IABR S_IABR /* Instruction Address Breakpoint Register */
336 #define IBAT0L S_IBAT0L /* Instruction BAT 0 Lower Register */
337 #define IBAT0U S_IBAT0U /* Instruction BAT 0 Upper Register */
338 #define IBAT1L S_IBAT1L /* Instruction BAT 1 Lower Register */
339 #define IBAT1U S_IBAT1U /* Instruction BAT 1 Upper Register */
340 #define IBAT2L S_IBAT2L /* Instruction BAT 2 Lower Register */
341 #define IBAT2U S_IBAT2U /* Instruction BAT 2 Upper Register */
342 #define IBAT3L S_IBAT3L /* Instruction BAT 3 Lower Register */
343 #define IBAT3U S_IBAT3U /* Instruction BAT 3 Upper Register */
344 #define ICMP S_ICMP /* Instruction TLB Compare Register */
345 #define IMISS S_IMISS /* Instruction TLB Miss Register */
346 #define IMMR S_IMMR /* PPC 860/821 Internal Memory Map Register */
347 #define L2CR S_L2CR /* PPC 750 L2 control register */
348 #define PVR S_PVR /* Processor Version */
349 #define RPA S_RPA /* Required Physical Address Register */
350 #define SDR1 S_SDR1 /* MMU hash base register */
351 #define SPR0 S_SPRG0 /* Supervisor Private Registers */
355 #define SPRG0 S_SPRG0
356 #define SPRG1 S_SPRG1
357 #define SPRG2 S_SPRG2
358 #define SPRG3 S_SPRG3
359 #define SRR0 S_SRR0 /* Save and Restore Register 0 */
360 #define SRR1 S_SRR1 /* Save and Restore Register 1 */
361 #define TBRL S_STBRL /* Time Base Read Lower Register */
362 #define TBRU S_TBRU /* Time Base Read Upper Register */
363 #define TBWL S_TBWL /* Time Base Write Lower Register */
364 #define TBWU S_TBWU /* Time Base Write Upper Register */
366 #define THRM1 S_THRM1 /* Thermal Management Register 1 */
367 #define THRM2 S_THRM2 /* Thermal Management Register 2 */
368 #define THRM3 S_THRM3 /* Thermal Management Register 3 */
373 #define SR0 0 /* Segment registers */
390 #endif /* __ASSEMBLY__ */
394 #define OPCODE_PRIM(n) ( ((unsigned long)(n)) >> 26 )
395 #define OPCODE_EXT(n) ( (((unsigned long)(n)) >> 1) & 0x3ff )
396 #define OPCODE(op,op_ext) ( ((op)<<10) + op_ext )
398 #define B1(n) ( (((unsigned long)(n)) >> 21) & 0x1f )
399 #define B2(n) ( (((unsigned long)(n)) >> 16) & 0x1f )
400 #define B3(n) ( (((unsigned long)(n)) >> 11) & 0x1f )
402 #define BD(n) ((unsigned long)((n) & 0x7fff) + (((n) & 0x8000) ? (unsigned long)0xffff8000 : 0))
404 #define SPRNUM_FLIP( v ) ( (((v)>>5) & 0x1f) | (((v)<<5) & 0x3e0) )
408 #ifndef __ASSEMBLER__
410 #define __stringify_1(x) #x
411 #define __stringify(x) __stringify_1(x)
412 #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
414 static inline unsigned long mfmsr(void)
417 asm volatile("mfmsr %0" : "=r" (msr));
421 static inline void mtmsr(unsigned long msr)
424 asm volatile("mtmsrd %0" :: "r" (msr));
426 asm volatile("mtmsr %0" :: "r" (msr));
431 #define SDR1_HTABORG_MASK 0x3FFFFFFFFFFC0000UL
433 #define SDR1_HTABORG_MASK 0xffff0000
436 static inline unsigned long mfsdr1(void)
439 asm volatile("mfsdr1 %0" : "=r" (sdr1));
443 static inline void mtsdr1(unsigned long sdr1)
445 asm volatile("mtsdr1 %0" :: "r" (sdr1));
448 static inline unsigned int mfpvr(void)
451 asm volatile("mfspr %0, 0x11f" : "=r" (pvr) );
455 static inline void slbia(void)
457 asm volatile("slbia" ::: "memory");
460 static inline void slbmte(unsigned long rs, unsigned long rb)
462 asm volatile("slbmte %0,%1 ; isync" :: "r" (rs), "r" (rb) : "memory");
465 #endif /* !__ASSEMBLER__ */
467 #endif /* _H_PROCESSOR */