2 * Driver for USB OHCI ported from CoreBoot
4 * Copyright (C) 2014 BALATON Zoltan
6 * This file was part of the libpayload project.
8 * Copyright (C) 2010 Patrick Georgi
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 //#define USB_DEBUG_ED
38 #include <libopenbios/ofmem.h>
40 #include "drivers/pci.h"
42 #include <drivers/usb.h>
43 #include "usbohci_private.h"
46 static void ohci_start (hci_t *controller);
47 static void ohci_stop (hci_t *controller);
48 static void ohci_reset (hci_t *controller);
49 static void ohci_shutdown (hci_t *controller);
50 static int ohci_bulk (endpoint_t *ep, int size, u8 *data, int finalize);
51 static int ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq,
53 static void* ohci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming);
54 static void ohci_destroy_intr_queue (endpoint_t *ep, void *queue);
55 static u8* ohci_poll_intr_queue (void *queue);
56 static void ohci_process_done_queue(ohci_t *ohci, int spew_debug);
62 usb_debug("+---------------------------------------------------+\n");
63 if (((__le32_to_cpu(cur->config) & (3UL << 19)) >> 19) == 0)
64 usb_debug("|..[SETUP]..........................................|\n");
65 else if (((__le32_to_cpu(cur->config) & (3UL << 8)) >> 8) == 2)
66 usb_debug("|..[IN].............................................|\n");
67 else if (((__le32_to_cpu(cur->config) & (3UL << 8)) >> 8) == 1)
68 usb_debug("|..[OUT]............................................|\n");
70 usb_debug("|..[]...............................................|\n");
71 usb_debug("|:|============ OHCI TD at [0x%08lx] ==========|:|\n", virt_to_phys(cur));
72 usb_debug("|:| ERRORS = [%ld] | CONFIG = [0x%08x] | |:|\n",
73 3 - ((__le32_to_cpu(cur->config) & (3UL << 26)) >> 26), __le32_to_cpu(cur->config));
74 usb_debug("|:+-----------------------------------------------+:|\n");
75 usb_debug("|:| C | Condition Code | [%02ld] |:|\n",
76 (__le32_to_cpu(cur->config) & (0xFUL << 28)) >> 28);
77 usb_debug("|:| O | Direction/PID | [%ld] |:|\n",
78 (__le32_to_cpu(cur->config) & (3UL << 19)) >> 19);
79 usb_debug("|:| N | Buffer Rounding | [%ld] |:|\n",
80 (__le32_to_cpu(cur->config) & (1UL << 18)) >> 18);
81 usb_debug("|:| F | Delay Intterrupt | [%ld] |:|\n",
82 (__le32_to_cpu(cur->config) & (7UL << 21)) >> 21);
83 usb_debug("|:| I | Data Toggle | [%ld] |:|\n",
84 (__le32_to_cpu(cur->config) & (3UL << 24)) >> 24);
85 usb_debug("|:| G | Error Count | [%ld] |:|\n",
86 (__le32_to_cpu(cur->config) & (3UL << 26)) >> 26);
87 usb_debug("|:+-----------------------------------------------+:|\n");
88 usb_debug("|:| Current Buffer Pointer [0x%08x] |:|\n", __le32_to_cpu(cur->current_buffer_pointer));
89 usb_debug("|:+-----------------------------------------------+:|\n");
90 usb_debug("|:| Next TD [0x%08x] |:|\n", __le32_to_cpu(cur->next_td));
91 usb_debug("|:+-----------------------------------------------+:|\n");
92 usb_debug("|:| Current Buffer End [0x%08x] |:|\n", __le32_to_cpu(cur->buffer_end));
93 usb_debug("|:|-----------------------------------------------|:|\n");
94 usb_debug("|...................................................|\n");
95 usb_debug("+---------------------------------------------------+\n");
102 usb_debug("+===================================================+\n");
103 usb_debug("| ############# OHCI ED at [0x%08lx] ########### |\n", virt_to_phys(cur));
104 usb_debug("+---------------------------------------------------+\n");
105 usb_debug("| Next Endpoint Descriptor [0x%08lx] |\n", __le32_to_cpu(cur->next_ed) & ~0xFUL);
106 usb_debug("+---------------------------------------------------+\n");
107 usb_debug("| | @ 0x%08x : |\n", __le32_to_cpu(cur->config));
108 usb_debug("| C | Maximum Packet Length | [%04ld] |\n",
109 ((__le32_to_cpu(cur->config) & (0x3fffUL << 16)) >> 16));
110 usb_debug("| O | Function Address | [%04d] |\n",
111 __le32_to_cpu(cur->config) & 0x7F);
112 usb_debug("| N | Endpoint Number | [%02ld] |\n",
113 (__le32_to_cpu(cur->config) & (0xFUL << 7)) >> 7);
114 usb_debug("| F | Endpoint Direction | [%ld] |\n",
115 ((__le32_to_cpu(cur->config) & (3UL << 11)) >> 11));
116 usb_debug("| I | Endpoint Speed | [%ld] |\n",
117 ((__le32_to_cpu(cur->config) & (1UL << 13)) >> 13));
118 usb_debug("| G | Skip | [%ld] |\n",
119 ((__le32_to_cpu(cur->config) & (1UL << 14)) >> 14));
120 usb_debug("| | Format | [%ld] |\n",
121 ((__le32_to_cpu(cur->config) & (1UL << 15)) >> 15));
122 usb_debug("+---------------------------------------------------+\n");
123 usb_debug("| TD Queue Tail Pointer [0x%08lx] |\n",
124 __le32_to_cpu(cur->tail_pointer) & ~0xFUL);
125 usb_debug("+---------------------------------------------------+\n");
126 usb_debug("| TD Queue Head Pointer [0x%08lx] |\n",
127 __le32_to_cpu(cur->head_pointer) & ~0xFUL);
128 usb_debug("| CarryToggleBit [%d] Halted [%d] |\n",
129 (u16)(__le32_to_cpu(cur->head_pointer) & 0x2UL)>>1, (u16)(__le32_to_cpu(cur->head_pointer) & 0x1UL));
131 tmp_td = (td_t *)phys_to_virt((__le32_to_cpu(cur->head_pointer) & ~0xFUL));
132 if ((__le32_to_cpu(cur->head_pointer) & ~0xFUL) != (__le32_to_cpu(cur->tail_pointer) & ~0xFUL)) {
133 usb_debug("|:::::::::::::::::: OHCI TD CHAIN ::::::::::::::::::|\n");
134 while (virt_to_phys(tmp_td) != (__le32_to_cpu(cur->tail_pointer) & ~0xFUL))
137 tmp_td = (td_t *)phys_to_virt((__le32_to_cpu(tmp_td->next_td) & ~0xFUL));
139 usb_debug("|:::::::::::::::: EOF OHCI TD CHAIN ::::::::::::::::|\n");
140 usb_debug("+---------------------------------------------------+\n");
142 usb_debug("+---------------------------------------------------+\n");
148 ohci_reset (hci_t *controller)
150 if (controller == NULL)
153 OHCI_INST(controller)->opreg->HcCommandStatus = __cpu_to_le32(HostControllerReset);
154 mdelay(2); /* wait 2ms */
155 OHCI_INST(controller)->opreg->HcControl = 0;
156 mdelay(10); /* wait 10ms */
160 ohci_reinit (hci_t *controller)
165 ohci_init (void *bar)
169 hci_t *controller = new_controller ();
172 printk("Could not create USB controller instance.\n");
176 controller->instance = malloc (sizeof (ohci_t));
177 if(!controller->instance) {
178 printk("Not enough memory creating USB controller instance.\n");
182 controller->type = OHCI;
184 controller->start = ohci_start;
185 controller->stop = ohci_stop;
186 controller->reset = ohci_reset;
187 controller->init = ohci_reinit;
188 controller->shutdown = ohci_shutdown;
189 controller->bulk = ohci_bulk;
190 controller->control = ohci_control;
191 controller->set_address = generic_set_address;
192 controller->finish_device_config = NULL;
193 controller->destroy_device = NULL;
194 controller->create_intr_queue = ohci_create_intr_queue;
195 controller->destroy_intr_queue = ohci_destroy_intr_queue;
196 controller->poll_intr_queue = ohci_poll_intr_queue;
197 for (i = 0; i < 128; i++) {
198 controller->devices[i] = 0;
200 init_device_entry (controller, 0);
201 OHCI_INST (controller)->roothub = controller->devices[0];
203 controller->reg_base = (u32)(unsigned long)bar;
204 OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(controller->reg_base);
205 usb_debug("OHCI Version %x.%x\n",
206 (READ_OPREG(OHCI_INST(controller), HcRevision) >> 4) & 0xf,
207 READ_OPREG(OHCI_INST(controller), HcRevision) & 0xf);
209 if ((READ_OPREG(OHCI_INST(controller), HcControl) & HostControllerFunctionalStateMask) == USBReset) {
211 OHCI_INST (controller)->opreg->HcControl &= __cpu_to_le32(~RemoteWakeupConnected);
212 OHCI_INST (controller)->opreg->HcFmInterval =
213 __cpu_to_le32((11999 * FrameInterval) | ((((11999 - 210)*6)/7) * FSLargestDataPacket));
214 /* TODO: right value for PowerOnToPowerGoodTime ? */
215 OHCI_INST (controller)->opreg->HcRhDescriptorA =
216 __cpu_to_le32(NoPowerSwitching | NoOverCurrentProtection | (10 * PowerOnToPowerGoodTime));
217 OHCI_INST (controller)->opreg->HcRhDescriptorB = __cpu_to_le32(0 * DeviceRemovable);
218 udelay(100); /* TODO: reset asserting according to USB spec */
219 } else if ((READ_OPREG(OHCI_INST(controller), HcControl) & HostControllerFunctionalStateMask) != USBOperational) {
220 OHCI_INST (controller)->opreg->HcControl =
221 __cpu_to_le32((READ_OPREG(OHCI_INST(controller), HcControl) & ~HostControllerFunctionalStateMask)
223 udelay(100); /* TODO: resume time according to USB spec */
225 int interval = OHCI_INST (controller)->opreg->HcFmInterval;
227 OHCI_INST (controller)->opreg->HcCommandStatus = __cpu_to_le32(HostControllerReset);
228 udelay (10); /* at most 10us for reset to complete. State must be set to Operational within 2ms (5.1.1.4) */
229 OHCI_INST (controller)->opreg->HcFmInterval = interval;
230 ofmem_posix_memalign((void **)&(OHCI_INST (controller)->hcca), 256, 256);
231 memset((void*)OHCI_INST (controller)->hcca, 0, 256);
233 usb_debug("HCCA addr %p\n", OHCI_INST(controller)->hcca);
234 /* Initialize interrupt table. */
235 u32 *const intr_table = OHCI_INST(controller)->hcca->HccaInterruptTable;
236 ed_t *const periodic_ed;
237 ofmem_posix_memalign((void **)&periodic_ed, sizeof(ed_t), sizeof(ed_t));
238 memset((void *)periodic_ed, 0, sizeof(*periodic_ed));
239 for (i = 0; i < 32; ++i)
240 intr_table[i] = __cpu_to_le32(virt_to_phys(periodic_ed));
241 OHCI_INST (controller)->periodic_ed = periodic_ed;
243 OHCI_INST (controller)->opreg->HcHCCA = __cpu_to_le32(virt_to_phys(OHCI_INST(controller)->hcca));
244 /* Make sure periodic schedule is enabled. */
245 OHCI_INST (controller)->opreg->HcControl |= __cpu_to_le32(PeriodicListEnable);
246 OHCI_INST (controller)->opreg->HcControl &= __cpu_to_le32(~IsochronousEnable); // unused by this driver
247 // disable everything, contrary to what OHCI spec says in 5.1.1.4, as we don't need IRQs
248 OHCI_INST (controller)->opreg->HcInterruptEnable = __cpu_to_le32(1<<31);
249 OHCI_INST (controller)->opreg->HcInterruptDisable = __cpu_to_le32(~(1<<31));
250 OHCI_INST (controller)->opreg->HcInterruptStatus = __cpu_to_le32(~0);
251 OHCI_INST (controller)->opreg->HcPeriodicStart =
252 __cpu_to_le32((READ_OPREG(OHCI_INST(controller), HcFmInterval) & FrameIntervalMask) / 10 * 9);
253 OHCI_INST (controller)->opreg->HcControl = __cpu_to_le32((READ_OPREG(OHCI_INST(controller), HcControl)
254 & ~HostControllerFunctionalStateMask) | USBOperational);
258 controller->devices[0]->controller = controller;
259 controller->devices[0]->init = ohci_rh_init;
260 controller->devices[0]->init (controller->devices[0]);
265 ohci_pci_init (pci_addr addr)
270 cmd = pci_config_read16(addr, PCI_COMMAND);
271 cmd |= PCI_COMMAND_BUS_MASTER;
272 pci_config_write16(addr, PCI_COMMAND, cmd);
274 /* regarding OHCI spec, Appendix A, BAR_OHCI register description, Table A-4
275 * BASE ADDRESS only [31-12] bits. All other usually 0, but not all.
276 * OHCI mandates MMIO, so bit 0 is clear */
277 reg_base = pci_config_read32 (addr, PCI_BASE_ADDR_0) & 0xfffff000;
279 return ohci_init((void *)(unsigned long)reg_base);
283 ohci_shutdown (hci_t *controller)
287 detach_controller (controller);
288 ohci_stop(controller);
289 OHCI_INST (controller)->roothub->destroy (OHCI_INST (controller)->
291 controller->reset (controller);
292 free ((void *)OHCI_INST (controller)->periodic_ed);
293 free (OHCI_INST (controller));
298 ohci_start (hci_t *controller)
300 // TODO: turn on all operation of OHCI, but assume that it's initialized.
304 ohci_stop (hci_t *controller)
306 // TODO: turn off all operation of OHCI
310 wait_for_ed(usbdev_t *dev, ed_t *head, int pages)
312 usb_debug("Waiting for %d pages on dev %p with head %p\n", pages, dev, head);
313 /* wait for results */
314 /* TOTEST: how long to wait?
315 * give 2s per TD (2 pages) plus another 2s for now
317 int timeout = pages*1000 + 2000;
318 while (((__le32_to_cpu(head->head_pointer) & ~3) != __le32_to_cpu(head->tail_pointer)) &&
319 !(__le32_to_cpu(head->head_pointer) & 1) &&
320 ((__le32_to_cpu((((td_t*)phys_to_virt(__le32_to_cpu(head->head_pointer) & ~3)))->config)
321 & TD_CC_MASK) >= TD_CC_NOACCESS) && timeout--) {
322 /* don't log every ms */
323 if (!(timeout % 100))
324 usb_debug("intst: %x; ctrl: %x; cmdst: %x; head: %x -> %x, tail: %x, condition: %x\n",
325 READ_OPREG(OHCI_INST(dev->controller), HcInterruptStatus),
326 READ_OPREG(OHCI_INST(dev->controller), HcControl),
327 READ_OPREG(OHCI_INST(dev->controller), HcCommandStatus),
328 __le32_to_cpu(head->head_pointer),
329 __le32_to_cpu(((td_t*)phys_to_virt(__le32_to_cpu(head->head_pointer) & ~3))->next_td),
330 __le32_to_cpu(head->tail_pointer),
331 (__le32_to_cpu(((td_t*)phys_to_virt(__le32_to_cpu(head->head_pointer) & ~3))->config) & TD_CC_MASK) >> TD_CC_SHIFT);
335 usb_debug("Error: ohci: endpoint "
336 "descriptor processing timed out.\n");
337 /* Clear the done queue. */
338 ohci_process_done_queue(OHCI_INST(dev->controller), 1);
340 if (__le32_to_cpu(head->head_pointer) & 1) {
341 usb_debug("HALTED!\n");
348 ohci_free_ed (ed_t *const head)
350 /* In case the transfer canceled, we have to free unprocessed TDs. */
351 while ((__le32_to_cpu(head->head_pointer) & ~0x3) != __le32_to_cpu(head->tail_pointer)) {
352 /* Save current TD pointer. */
354 (td_t*)phys_to_virt(__le32_to_cpu(head->head_pointer) & ~0x3);
355 /* Advance head pointer. */
356 head->head_pointer = cur_td->next_td;
357 /* Free current TD. */
358 free((void *)cur_td);
361 /* Always free the dummy TD */
362 if ((__le32_to_cpu(head->head_pointer) & ~0x3) == __le32_to_cpu(head->tail_pointer))
363 free(phys_to_virt(__le32_to_cpu(head->head_pointer) & ~0x3));
369 ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen,
374 // pages are specified as 4K in OHCI, so don't use getpagesize()
375 int first_page = (unsigned long)data / 4096;
376 int last_page = (unsigned long)(data+dalen-1)/4096;
377 if (last_page < first_page) last_page = first_page;
378 int pages = (dalen==0)?0:(last_page - first_page + 1);
381 td_t *const first_td;
382 ofmem_posix_memalign((void **)&first_td, sizeof(td_t), sizeof(td_t));
383 memset((void *)first_td, 0, sizeof(*first_td));
386 cur->config = __cpu_to_le32(TD_DIRECTION_SETUP |
387 TD_DELAY_INTERRUPT_NOINTR |
391 cur->current_buffer_pointer = __cpu_to_le32(virt_to_phys(devreq));
392 cur->buffer_end = __cpu_to_le32(virt_to_phys((char *)devreq + drlen - 1));
397 ofmem_posix_memalign((void **)&next, sizeof(td_t), sizeof(td_t));
398 memset((void *)next, 0, sizeof(*next));
399 /* Linked to the previous. */
400 cur->next_td = __cpu_to_le32(virt_to_phys(next));
401 /* Advance to the new TD. */
404 cur->config = __cpu_to_le32((dir == IN ? TD_DIRECTION_IN : TD_DIRECTION_OUT) |
405 TD_DELAY_INTERRUPT_NOINTR |
408 cur->current_buffer_pointer = __cpu_to_le32(virt_to_phys(data));
410 int consumed = (4096 - ((unsigned long)data % 4096));
411 if (consumed >= dalen) {
412 // end of data is within same page
413 cur->buffer_end = __cpu_to_le32(virt_to_phys(data + dalen - 1));
415 /* assert(pages == 0); */
420 int second_page_size = dalen;
422 second_page_size = 4096;
424 cur->buffer_end = __cpu_to_le32(virt_to_phys(data + second_page_size - 1));
425 dalen -= second_page_size;
426 data += second_page_size;
432 ofmem_posix_memalign((void **)&next_td, sizeof(td_t), sizeof(td_t));
433 memset((void *)next_td, 0, sizeof(*next_td));
434 /* Linked to the previous. */
435 cur->next_td = __cpu_to_le32(virt_to_phys(next_td));
436 /* Advance to the new TD. */
438 cur->config = __cpu_to_le32((dir == IN ? TD_DIRECTION_OUT : TD_DIRECTION_IN) |
439 TD_DELAY_INTERRUPT_ZERO | /* Write done head after this TD. */
443 cur->current_buffer_pointer = 0;
446 /* Final dummy TD. */
447 td_t *const final_td;
448 ofmem_posix_memalign((void **)&final_td, sizeof(td_t), sizeof(td_t));
449 memset((void *)final_td, 0, sizeof(*final_td));
450 /* Linked to the previous. */
451 cur->next_td = __cpu_to_le32(virt_to_phys(final_td));
453 /* Data structures */
455 ofmem_posix_memalign((void **)&head, sizeof(ed_t), sizeof(ed_t));
456 memset((void*)head, 0, sizeof(*head));
457 head->config = __cpu_to_le32((dev->address << ED_FUNC_SHIFT) |
459 (OHCI_FROM_TD << ED_DIR_SHIFT) |
460 (dev->speed?ED_LOWSPEED:0) |
461 (dev->endpoints[0].maxpacketsize << ED_MPS_SHIFT));
462 head->tail_pointer = __cpu_to_le32(virt_to_phys(final_td));
463 head->head_pointer = __cpu_to_le32(virt_to_phys(first_td));
465 usb_debug("ohci_control(): doing transfer with %x. first_td at %x\n",
466 __le32_to_cpu(head->config) & ED_FUNC_MASK, __le32_to_cpu(head->head_pointer));
471 /* activate schedule */
472 OHCI_INST(dev->controller)->opreg->HcControlHeadED = __cpu_to_le32(virt_to_phys(head));
473 OHCI_INST(dev->controller)->opreg->HcControl |= __cpu_to_le32(ControlListEnable);
474 OHCI_INST(dev->controller)->opreg->HcCommandStatus = __cpu_to_le32(ControlListFilled);
476 int failure = wait_for_ed(dev, head,
477 (dalen==0)?0:(last_page - first_page + 1));
478 /* Wait some frames before and one after disabling list access. */
480 OHCI_INST(dev->controller)->opreg->HcControl &= __cpu_to_le32(~ControlListEnable);
489 /* finalize == 1: if data is of packet aligned size, add a zero length packet */
491 ohci_bulk (endpoint_t *ep, int dalen, u8 *data, int finalize)
494 usb_debug("bulk: %x bytes from %p, finalize: %x, maxpacketsize: %x\n", dalen, data, finalize, ep->maxpacketsize);
498 // pages are specified as 4K in OHCI, so don't use getpagesize()
499 int first_page = (unsigned long)data / 4096;
500 int last_page = (unsigned long)(data+dalen-1)/4096;
501 if (last_page < first_page) last_page = first_page;
502 int pages = (dalen==0)?0:(last_page - first_page + 1);
503 int td_count = (pages+1)/2;
505 if (finalize && ((dalen % ep->maxpacketsize) == 0)) {
510 td_t *const first_td;
511 ofmem_posix_memalign((void **)&first_td, sizeof(td_t), sizeof(td_t));
512 memset((void *)first_td, 0, sizeof(*first_td));
513 cur = next = first_td;
515 for (i = 0; i < td_count; ++i) {
516 /* Advance to next TD. */
518 cur->config = __cpu_to_le32((ep->direction == IN ? TD_DIRECTION_IN : TD_DIRECTION_OUT) |
519 TD_DELAY_INTERRUPT_NOINTR |
522 cur->current_buffer_pointer = __cpu_to_le32(virt_to_phys(data));
525 /* magic TD for empty packet transfer */
526 cur->current_buffer_pointer = 0;
528 /* assert((pages == 0) && finalize); */
530 int consumed = (4096 - ((unsigned long)data % 4096));
531 if (consumed >= dalen) {
532 // end of data is within same page
533 cur->buffer_end = __cpu_to_le32(virt_to_phys(data + dalen - 1));
535 /* assert(pages == finalize); */
540 int second_page_size = dalen;
542 second_page_size = 4096;
544 cur->buffer_end = __cpu_to_le32(virt_to_phys(data + second_page_size - 1));
545 dalen -= second_page_size;
546 data += second_page_size;
549 ofmem_posix_memalign((void **)&next, sizeof(td_t), sizeof(td_t));
550 memset((void *)next, 0, sizeof(*next));
551 /* Linked to the previous. */
552 cur->next_td = __cpu_to_le32(virt_to_phys(next));
555 /* Write done head after last TD. */
556 cur->config &= __cpu_to_le32(~TD_DELAY_INTERRUPT_MASK);
557 /* Advance to final, dummy TD. */
560 /* Data structures */
562 ofmem_posix_memalign((void **)&head, sizeof(ed_t), sizeof(ed_t));
563 memset((void*)head, 0, sizeof(*head));
564 head->config = __cpu_to_le32((ep->dev->address << ED_FUNC_SHIFT) |
565 ((ep->endpoint & 0xf) << ED_EP_SHIFT) |
566 (((ep->direction==IN)?OHCI_IN:OHCI_OUT) << ED_DIR_SHIFT) |
567 (ep->dev->speed?ED_LOWSPEED:0) |
568 (ep->maxpacketsize << ED_MPS_SHIFT));
569 head->tail_pointer = __cpu_to_le32(virt_to_phys(cur));
570 head->head_pointer = __cpu_to_le32(virt_to_phys(first_td) | (ep->toggle?ED_TOGGLE:0));
572 usb_debug("doing bulk transfer with %x(%x). first_td at %lx, last %lx\n",
573 __le32_to_cpu(head->config) & ED_FUNC_MASK,
574 (__le32_to_cpu(head->config) & ED_EP_MASK) >> ED_EP_SHIFT,
575 virt_to_phys(first_td), virt_to_phys(cur));
577 /* activate schedule */
578 OHCI_INST(ep->dev->controller)->opreg->HcBulkHeadED = __cpu_to_le32(virt_to_phys(head));
579 OHCI_INST(ep->dev->controller)->opreg->HcControl |= __cpu_to_le32(BulkListEnable);
580 OHCI_INST(ep->dev->controller)->opreg->HcCommandStatus = __cpu_to_le32(BulkListFilled);
582 int failure = wait_for_ed(ep->dev, head,
583 (dalen==0)?0:(last_page - first_page + 1));
584 /* Wait some frames before and one after disabling list access. */
586 OHCI_INST(ep->dev->controller)->opreg->HcControl &= __cpu_to_le32(~BulkListEnable);
589 ep->toggle = __le32_to_cpu(head->head_pointer) & ED_TOGGLE;
608 struct _intrq_td *next;
609 struct _intr_queue *intrq;
614 struct _intrq_td *head;
615 struct _intrq_td *tail;
619 unsigned int remaining_tds;
623 typedef struct _intrq_td intrq_td_t;
624 typedef struct _intr_queue intr_queue_t;
626 #define INTRQ_TD_FROM_TD(x) ((intrq_td_t *)x)
629 ohci_fill_intrq_td(intrq_td_t *const td, intr_queue_t *const intrq,
632 memset(td, 0, sizeof(*td));
633 td->td.config = __cpu_to_le32(TD_QUEUETYPE_INTR |
634 (intrq->endp->direction == IN ? TD_DIRECTION_IN : TD_DIRECTION_OUT) |
635 TD_DELAY_INTERRUPT_ZERO |
638 td->td.current_buffer_pointer = __cpu_to_le32(virt_to_phys(data));
639 td->td.buffer_end = __cpu_to_le32(virt_to_phys(data) + intrq->reqsize - 1);
644 /* create and hook-up an intr queue into device schedule */
646 ohci_create_intr_queue(endpoint_t *const ep, const int reqsize,
647 const int reqcount, const int reqtiming)
650 intrq_td_t *first_td = NULL, *last_td = NULL;
655 intr_queue_t *const intrq;
656 ofmem_posix_memalign((void **)&intrq, sizeof(intrq->ed), sizeof(*intrq));
657 memset(intrq, 0, sizeof(*intrq));
658 intrq->data = (u8 *)malloc(reqcount * reqsize);
659 intrq->reqsize = reqsize;
662 /* Create #reqcount TDs. */
663 u8 *cur_data = intrq->data;
664 for (i = 0; i < reqcount; ++i) {
665 intrq_td_t *const td;
666 ofmem_posix_memalign((void **)&td, sizeof(td->td), sizeof(*td));
667 ++intrq->remaining_tds;
668 ohci_fill_intrq_td(td, intrq, cur_data);
673 last_td->td.next_td = __cpu_to_le32(virt_to_phys(&td->td));
677 /* Create last, dummy TD. */
678 intrq_td_t *dummy_td;
679 ofmem_posix_memalign((void **)&dummy_td, sizeof(dummy_td->td), sizeof(*dummy_td));
680 memset(dummy_td, 0, sizeof(*dummy_td));
681 dummy_td->intrq = intrq;
683 last_td->td.next_td = __cpu_to_le32(virt_to_phys(&dummy_td->td));
687 intrq->ed.config = __cpu_to_le32((ep->dev->address << ED_FUNC_SHIFT) |
688 ((ep->endpoint & 0xf) << ED_EP_SHIFT) |
689 (((ep->direction == IN) ? OHCI_IN : OHCI_OUT) << ED_DIR_SHIFT) |
690 (ep->dev->speed ? ED_LOWSPEED : 0) |
691 (ep->maxpacketsize << ED_MPS_SHIFT));
692 intrq->ed.tail_pointer = __cpu_to_le32(virt_to_phys(last_td));
693 intrq->ed.head_pointer = __cpu_to_le32(virt_to_phys(first_td) | (ep->toggle ? ED_TOGGLE : 0));
698 /* Insert ED into periodic table. */
699 int nothing_placed = 1;
700 ohci_t *const ohci = OHCI_INST(ep->dev->controller);
701 u32 *const intr_table = ohci->hcca->HccaInterruptTable;
702 const u32 dummy_ptr = __cpu_to_le32(virt_to_phys(ohci->periodic_ed));
703 for (i = 0; i < 32; i += reqtiming) {
704 /* Advance to the next free position. */
705 while ((i < 32) && (intr_table[i] != dummy_ptr)) ++i;
707 usb_debug("Placed endpoint %lx to %d\n", virt_to_phys(&intrq->ed), i);
708 intr_table[i] = __cpu_to_le32(virt_to_phys(&intrq->ed));
712 if (nothing_placed) {
713 usb_debug("Error: Failed to place ohci interrupt endpoint "
714 "descriptor into periodic table: no space left\n");
715 ohci_destroy_intr_queue(ep, intrq);
722 /* remove queue from device schedule, dropping all data that came in */
724 ohci_destroy_intr_queue(endpoint_t *const ep, void *const q_)
726 intr_queue_t *const intrq = (intr_queue_t *)q_;
730 /* Remove interrupt queue from periodic table. */
731 ohci_t *const ohci = OHCI_INST(ep->dev->controller);
732 u32 *const intr_table = ohci->hcca->HccaInterruptTable;
733 for (i=0; i < 32; ++i) {
734 if (intr_table[i] == __cpu_to_le32(virt_to_phys(intrq)))
735 intr_table[i] = __cpu_to_le32(virt_to_phys(ohci->periodic_ed));
737 /* Wait for frame to finish. */
740 /* Free unprocessed TDs. */
741 while ((__le32_to_cpu(intrq->ed.head_pointer) & ~0x3) != __le32_to_cpu(intrq->ed.tail_pointer)) {
742 td_t *const cur_td = (td_t *)phys_to_virt(__le32_to_cpu(intrq->ed.head_pointer) & ~0x3);
743 intrq->ed.head_pointer = cur_td->next_td;
744 free(INTRQ_TD_FROM_TD(cur_td));
745 --intrq->remaining_tds;
747 /* Free final, dummy TD. */
748 free(phys_to_virt(__le32_to_cpu(intrq->ed.head_pointer) & ~0x3));
749 /* Free data buffer. */
752 /* Free TDs already fetched from the done queue. */
753 ohci_process_done_queue(ohci, 1);
754 while (intrq->head) {
755 intrq_td_t *const cur_td = (intrq_td_t *const )__le32_to_cpu(intrq->head);
756 intrq->head = intrq->head->next;
758 --intrq->remaining_tds;
761 /* Mark interrupt queue to be destroyed.
762 ohci_process_done_queue() will free the remaining TDs
763 and finish the interrupt queue off once all TDs are gone. */
766 /* Save data toggle. */
767 ep->toggle = __le32_to_cpu(intrq->ed.head_pointer) & ED_TOGGLE;
770 /* read one intr-packet from queue, if available. extend the queue for new input.
771 return NULL if nothing new available.
772 Recommended use: while (data=poll_intr_queue(q)) process(data);
775 ohci_poll_intr_queue(void *const q_)
777 intr_queue_t *const intrq = (intr_queue_t *)q_;
781 /* Process done queue first, then check if we have work to do. */
782 ohci_process_done_queue(OHCI_INST(intrq->endp->dev->controller), 0);
785 /* Save pointer to processed TD and advance. */
786 intrq_td_t *const cur_td = intrq->head;
787 intrq->head = cur_td->next;
789 /* Return data buffer of this TD. */
792 /* Requeue this TD (i.e. copy to dummy and requeue as dummy). */
793 intrq_td_t *const dummy_td =
794 INTRQ_TD_FROM_TD(phys_to_virt(__le32_to_cpu(intrq->ed.tail_pointer)));
795 ohci_fill_intrq_td(dummy_td, intrq, data);
796 /* Reset all but intrq pointer (i.e. init as dummy). */
797 memset(cur_td, 0, sizeof(*cur_td));
798 cur_td->intrq = intrq;
799 /* Insert into interrupt queue as dummy. */
800 dummy_td->td.next_td = __le32_to_cpu(virt_to_phys(&cur_td->td));
801 intrq->ed.tail_pointer = __le32_to_cpu(virt_to_phys(&cur_td->td));
808 ohci_process_done_queue(ohci_t *const ohci, const int spew_debug)
812 /* Temporary queue of interrupt queue TDs (to reverse order). */
813 intrq_td_t *temp_tdq = NULL;
815 /* Check if done head has been written. */
816 if (!(READ_OPREG(ohci, HcInterruptStatus) & WritebackDoneHead))
818 /* Fetch current done head.
819 Lsb is only interesting for hw interrupts. */
820 u32 phys_done_queue = __le32_to_cpu(ohci->hcca->HccaDoneHead) & ~1;
821 /* Tell host controller, he may overwrite the done head pointer. */
822 ohci->opreg->HcInterruptStatus = __cpu_to_le32(WritebackDoneHead);
825 /* Process done queue (it's in reversed order). */
826 while (phys_done_queue) {
827 td_t *const done_td = (td_t *)phys_to_virt(phys_done_queue);
829 /* Advance pointer to next TD. */
830 phys_done_queue = __le32_to_cpu(done_td->next_td);
832 switch (__le32_to_cpu(done_td->config) & TD_QUEUETYPE_MASK) {
833 case TD_QUEUETYPE_ASYNC:
834 /* Free processed async TDs. */
835 free((void *)done_td);
837 case TD_QUEUETYPE_INTR: {
838 intrq_td_t *const td = INTRQ_TD_FROM_TD(done_td);
839 intr_queue_t *const intrq = td->intrq;
840 /* Check if the corresponding interrupt
841 queue is still beeing processed. */
842 if (intrq->destroy) {
843 /* Free this TD, and */
845 --intrq->remaining_tds;
846 /* the interrupt queue if it has no more TDs. */
847 if (!intrq->remaining_tds)
849 usb_debug("Freed TD from orphaned interrupt "
850 "queue, %d TDs remain.\n",
851 intrq->remaining_tds);
853 /* Save done TD to be processed. */
865 usb_debug("Processed %d done TDs.\n", i);
868 /* Process interrupt queue TDs in right order. */
870 /* Save pointer of current TD and advance. */
871 intrq_td_t *const cur_td = temp_tdq;
872 temp_tdq = temp_tdq->next;
874 /* The interrupt queue for the current TD. */
875 intr_queue_t *const intrq = cur_td->intrq;
876 /* Append to interrupt queue. */
879 intrq->head = intrq->tail = cur_td;
881 /* Insert at tail. */
882 intrq->tail->next = cur_td;
883 intrq->tail = cur_td;
885 /* It's always the last element. */
890 usb_debug("processed %d done tds, %d intr tds thereof.\n", i, j);
893 int ob_usb_ohci_init (const char *path, uint32_t addr)
898 usb_debug("ohci_init: %s addr = %x\n", path, addr);
899 ctrl = ohci_pci_init(addr);
906 /* Look for a keyboard */
907 for (i = 0; i < 128; i++) {
908 if (ctrl->devices[i] && ctrl->devices[i]->configuration) {
909 configuration_descriptor_t *cd;
910 interface_descriptor_t *intf;
912 cd = (configuration_descriptor_t *)ctrl->devices[i]->configuration;
913 intf = (interface_descriptor_t *)(ctrl->devices[i]->configuration + cd->bLength);
914 usb_debug("Device at port %d is class %d\n", i, intf->bInterfaceClass);
915 if (intf->bInterfaceClass == hid_device &&
916 intf->bInterfaceSubClass == hid_subclass_boot &&
917 intf->bInterfaceProtocol == hid_boot_proto_keyboard ) {
923 ob_usb_hid_add_keyboard(path);