4 * This driver is compliant to the
5 * PCI bus binding to IEEE 1275-1994 Rev 2.1
7 * (C) 2004 Stefan Reinauer <stepan@openbios.org>
8 * (C) 2005 Ed Schouten <ed@fxq.nl>
10 * Some parts from OpenHackWare-0.4, Copyright (c) 2004-2005 Jocelyn Mayer
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
19 #include "libopenbios/bindings.h"
20 #include "libopenbios/ofmem.h"
21 #include "kernel/kernel.h"
22 #include "drivers/pci.h"
23 #include "libc/byteorder.h"
24 #include "libc/vsprintf.h"
26 #include "drivers/drivers.h"
27 #include "drivers/vga.h"
28 #include "packages/video.h"
29 #include "libopenbios/video.h"
32 #include "pci_database.h"
33 #ifdef CONFIG_DRIVER_MACIO
37 #ifdef CONFIG_DRIVER_USB
38 #include "drivers/usb.h"
41 #if defined (CONFIG_DEBUG_PCI)
42 # define PCI_DPRINTF(format, ...) printk(format, ## __VA_ARGS__)
44 # define PCI_DPRINTF(format, ...) do { } while (0)
47 #define set_bool_property(ph, name) set_property(ph, name, NULL, 0);
49 /* DECLARE data structures for the nodes. */
51 DECLARE_UNNAMED_NODE( ob_pci_bus_node, INSTALL_OPEN, 2*sizeof(int) );
52 DECLARE_UNNAMED_NODE( ob_pci_simple_node, INSTALL_OPEN, 2*sizeof(int) );
53 DECLARE_UNNAMED_NODE( ob_pci_empty_node, 0, 2*sizeof(int) );
55 const pci_arch_t *arch;
57 #define IS_NOT_RELOCATABLE 0x80000000
58 #define IS_PREFETCHABLE 0x40000000
59 #define IS_ALIASED 0x20000000
62 CONFIGURATION_SPACE = 0,
68 static int encode_int32_cells(int num_cells, u32 *prop, ucell val)
73 for (i=0; i < num_cells; ++i) {
74 prop[num_cells - i - 1] = val;
82 static inline int pci_encode_phys_addr(u32 *phys, int flags, int space_code,
83 pci_addr dev, uint8_t reg, uint64_t addr)
88 phys[0] = flags | (space_code << 24) | dev | reg;
101 static inline int pci_encode_size(u32 *prop, uint64_t size)
103 return encode_int32_cells(2, prop, size);
106 static int host_address_cells(void)
108 return get_int_property(find_dev("/"), "#address-cells", NULL);
111 static int host_encode_phys_addr(u32 *prop, ucell addr)
113 return encode_int32_cells(host_address_cells(), prop, addr);
116 static int host_size_cells(void)
118 return get_int_property(find_dev("/"), "#size-cells", NULL);
122 static int parent_address_cells(void)
124 phandle_t parent_ph = ih_to_phandle(my_parent());
125 return get_int_property(parent_ph, "#address-cells", NULL);
128 static int parent_size_cells(void)
130 phandle_t parent_ph = ih_to_phandle(my_parent());
131 return get_int_property(parent_ph, "#size-cells", NULL);
135 #if defined(CONFIG_DEBUG_PCI)
136 static void dump_reg_property(const char* description, int nreg, u32 *reg)
139 printk("%s reg", description);
140 for (i=0; i < nreg; ++i) {
141 printk(" %08X", reg[i]);
147 static unsigned long pci_bus_addr_to_host_addr(int space, uint32_t ba)
149 if (space == IO_SPACE) {
150 return arch->io_base + (unsigned long)ba;
151 } else if (space == MEMORY_SPACE_32) {
152 return arch->host_pci_base + (unsigned long)ba;
154 /* Return unaltered to aid debugging property values */
155 return (unsigned long)ba;
160 ob_pci_open(int *idx)
167 ob_pci_close(int *idx)
172 ob_pci_initialize(int *idx)
176 /* ( str len -- phys.lo phys.mid phys.hi ) */
179 ob_pci_decode_unit(int *idx)
182 const char *arg = pop_fstr_copy();
183 int dev, fn, reg, ss, n, p, t;
184 int bus = 0; /* no information */
187 PCI_DPRINTF("ob_pci_decode_unit idx=%p\n", idx);
197 n = IS_NOT_RELOCATABLE;
208 /* DD,F,RR,NNNNNNNN */
210 dev = strtol(ptr, &ptr, 16);
212 fn = strtol(ptr, &ptr, 16);
214 reg = strtol(ptr, &ptr, 16);
216 lo = strtol(ptr, &ptr, 16);
219 } else if (*ptr == 'm') {
220 ss = MEMORY_SPACE_32;
231 /* DD,F,RR,NNNNNNNN */
233 dev = strtol(ptr, &ptr, 16);
235 fn = strtol(ptr, &ptr, 16);
237 reg = strtol(ptr, &ptr, 16);
239 lo = strtol(ptr, &ptr, 16);
242 } else if (*ptr == 'x') {
243 unsigned long long addr64;
244 ss = MEMORY_SPACE_64;
251 /* DD,F,RR,NNNNNNNNNNNNNNNN */
253 dev = strtol(ptr, &ptr, 16);
255 fn = strtol(ptr, &ptr, 16);
257 reg = strtol(ptr, &ptr, 16);
259 addr64 = strtoll(ptr, &ptr, 16);
264 ss = CONFIGURATION_SPACE;
265 /* "DD" or "DD,FF" */
266 dev = strtol(ptr, &ptr, 16);
269 fn = strtol(ptr, NULL, 16);
276 hi = n | p | t | (ss << 24) | (bus << 16) | (dev << 11) | (fn << 8) | reg;
282 PCI_DPRINTF("ob_pci_decode_unit idx=%p addr="
283 FMT_ucellx " " FMT_ucellx " " FMT_ucellx "\n",
287 /* ( phys.lo phy.mid phys.hi -- str len ) */
290 ob_pci_encode_unit(int *idx)
296 int n, p, t, ss, dev, fn, reg;
298 n = hi & IS_NOT_RELOCATABLE;
299 p = hi & IS_PREFETCHABLE;
301 ss = (hi >> 24) & 0x03;
303 dev = (hi >> 11) & 0x1F;
304 fn = (hi >> 8) & 0x07;
308 case CONFIGURATION_SPACE:
310 if (fn == 0) /* DD */
311 snprintf(buf, sizeof(buf), "%x", dev);
313 snprintf(buf, sizeof(buf), "%x,%x", dev, fn);
318 /* [n]i[t]DD,F,RR,NNNNNNNN */
319 snprintf(buf, sizeof(buf), "%si%s%x,%x,%x," FMT_ucellx,
320 n ? "n" : "", /* relocatable */
321 t ? "t" : "", /* aliased */
322 dev, fn, reg, t ? lo & 0x03FF : lo);
325 case MEMORY_SPACE_32:
327 /* [n]m[t][p]DD,F,RR,NNNNNNNN */
328 snprintf(buf, sizeof(buf), "%sm%s%s%x,%x,%x," FMT_ucellx,
329 n ? "n" : "", /* relocatable */
330 t ? "t" : "", /* aliased */
331 p ? "p" : "", /* prefetchable */
335 case MEMORY_SPACE_64:
337 /* [n]x[p]DD,F,RR,NNNNNNNNNNNNNNNN */
338 snprintf(buf, sizeof(buf), "%sx%s%x,%x,%x,%llx",
339 n ? "n" : "", /* relocatable */
340 p ? "p" : "", /* prefetchable */
341 dev, fn, reg, ((long long)mid << 32) | (long long)lo);
346 PCI_DPRINTF("ob_pci_encode_unit space=%d dev=%d fn=%d buf=%s\n",
350 /* ( pci-addr.lo pci-addr.mid pci-addr.hi size -- virt ) */
353 ob_pci_map_in(int *idx)
357 ucell size, virt, tmp;
360 PCI_DPRINTF("ob_pci_bar_map_in idx=%p\n", idx);
367 /* Get the space from the pci-addr.hi */
368 space = ((tmp & PCI_RANGE_TYPE_MASK) >> 24);
370 phys = pci_bus_addr_to_host_addr(space, ba);
372 #if defined(CONFIG_OFMEM)
373 ofmem_claim_phys(phys, size, 0);
375 #if defined(CONFIG_PPC)
376 /* For some reason PPC gets upset when virt != phys for map-in... */
377 virt = ofmem_claim_virt(phys, size, 0);
379 virt = ofmem_claim_virt(-1, size, size);
382 ofmem_map(phys, virt, size, ofmem_arch_io_translation_mode(phys));
385 virt = size; /* Keep compiler quiet */
392 NODE_METHODS(ob_pci_bus_node) = {
393 { NULL, ob_pci_initialize },
394 { "open", ob_pci_open },
395 { "close", ob_pci_close },
396 { "decode-unit", ob_pci_decode_unit },
397 { "encode-unit", ob_pci_encode_unit },
398 { "pci-map-in", ob_pci_map_in },
401 NODE_METHODS(ob_pci_simple_node) = {
402 { NULL, ob_pci_initialize },
403 { "open", ob_pci_open },
404 { "close", ob_pci_close },
407 NODE_METHODS(ob_pci_empty_node) = {
408 { NULL, ob_pci_initialize }
411 static void pci_set_bus_range(const pci_config_t *config)
413 phandle_t dev = find_dev(config->path);
416 props[0] = config->secondary_bus;
417 props[1] = config->subordinate_bus;
419 PCI_DPRINTF("setting bus range for %s PCI device, "
420 "package handle " FMT_ucellx " "
421 "bus primary=%d secondary=%d subordinate=%d\n",
425 config->secondary_bus,
426 config->subordinate_bus);
429 set_property(dev, "bus-range", (char *)props, 2 * sizeof(props[0]));
432 static void pci_host_set_reg(phandle_t phandle)
434 phandle_t dev = phandle;
436 /* at most 2 integers for address and size */
440 ncells += encode_int32_cells(host_address_cells(), props + ncells,
443 ncells += encode_int32_cells(host_size_cells(), props + ncells,
446 set_property(dev, "reg", (char *)props, ncells * sizeof(props[0]));
448 #if defined(CONFIG_DEBUG_PCI)
449 dump_reg_property("pci_host_set_reg", 4, props);
453 /* child-phys : parent-phys : size */
454 /* 3 cells for PCI : 2 cells for 64bit parent : 2 cells for PCI */
456 static void pci_host_set_ranges(const pci_config_t *config)
458 phandle_t dev = get_cur_dev();
464 #ifdef CONFIG_SPARC64
465 /* While configuration space isn't mentioned in the IEEE-1275 PCI
466 bindings, it appears in the PCI host bridge ranges property in
467 real device trees. Hence we disable this range for all host
468 bridges except for SPARC, particularly as it causes Darwin/OS X
469 to incorrectly calculated PCI memory space ranges on PPC. */
470 ncells += pci_encode_phys_addr(props + ncells, 0, CONFIGURATION_SPACE,
472 ncells += host_encode_phys_addr(props + ncells, arch->cfg_addr);
473 ncells += pci_encode_size(props + ncells, arch->cfg_len);
477 ncells += pci_encode_phys_addr(props + ncells, 0, IO_SPACE,
479 ncells += host_encode_phys_addr(props + ncells, arch->io_base);
480 ncells += pci_encode_size(props + ncells, arch->io_len);
483 ncells += pci_encode_phys_addr(props + ncells, 0, MEMORY_SPACE_32,
485 ncells += host_encode_phys_addr(props + ncells, arch->rbase);
486 ncells += pci_encode_size(props + ncells, arch->rlen);
488 if (arch->pci_mem_base) {
489 ncells += pci_encode_phys_addr(props + ncells, 0, MEMORY_SPACE_32,
490 config->dev, 0, arch->pci_mem_base);
491 ncells += host_encode_phys_addr(props + ncells, arch->host_pci_base +
493 ncells += pci_encode_size(props + ncells, arch->mem_len);
495 set_property(dev, "ranges", (char *)props, ncells * sizeof(props[0]));
498 int host_config_cb(const pci_config_t *config)
500 //XXX this overrides "reg" property
501 pci_host_set_reg(get_cur_dev());
502 pci_host_set_ranges(config);
507 static int sabre_configure(phandle_t dev)
511 props[0] = 0xc0000000;
512 props[1] = 0x20000000;
513 set_property(dev, "virtual-dma", (char *)props, 2 * sizeof(props[0]));
515 set_property(dev, "#virtual-dma-size-cells", (char *)props,
517 set_property(dev, "#virtual-dma-addr-cells", (char *)props,
520 set_property(dev, "no-streaming-cache", (char *)props, 0);
522 props[0] = 0x000007f0;
523 props[1] = 0x000007ee;
524 props[2] = 0x000007ef;
525 props[3] = 0x000007e5;
526 set_property(dev, "interrupts", (char *)props, 4 * sizeof(props[0]));
527 props[0] = 0x0000001f;
528 set_property(dev, "upa-portid", (char *)props, 1 * sizeof(props[0]));
532 int sabre_config_cb(const pci_config_t *config)
534 host_config_cb(config);
536 return sabre_configure(get_cur_dev());
539 int bridge_config_cb(const pci_config_t *config)
543 aliases = find_dev("/aliases");
544 set_property(aliases, "bridge", config->path, strlen(config->path) + 1);
549 int ide_config_cb2 (const pci_config_t *config)
551 ob_ide_init(config->path,
552 config->assigned[0] & ~0x0000000F,
553 (config->assigned[1] & ~0x0000000F) + 2,
554 config->assigned[2] & ~0x0000000F,
555 (config->assigned[3] & ~0x0000000F) + 2);
559 int eth_config_cb (const pci_config_t *config)
561 phandle_t ph = get_cur_dev();
563 set_property(ph, "network-type", "ethernet", 9);
564 set_property(ph, "removable", "network", 8);
565 set_property(ph, "category", "net", 4);
570 static inline void pci_decode_pci_addr(pci_addr addr, int *flags,
571 int *space_code, uint32_t *mask)
576 *space_code = IO_SPACE;
580 *space_code = MEMORY_SPACE_64;
581 *flags |= IS_NOT_RELOCATABLE; /* XXX: why not relocatable? */
583 *space_code = MEMORY_SPACE_32;
587 *flags |= IS_PREFETCHABLE;
595 * "Designing PCI Cards and Drivers for Power Macintosh Computers", p. 454
597 * "AAPL,address" provides an array of 32-bit logical addresses
598 * Nth entry corresponding to Nth "assigned-address" base address entry.
601 static void pci_set_AAPL_address(const pci_config_t *config)
603 phandle_t dev = get_cur_dev();
606 int ncells, i, flags, space_code;
609 for (i = 0; i < 6; i++) {
610 if (!config->assigned[i] || !config->sizes[i])
612 pci_decode_pci_addr(config->assigned[i],
613 &flags, &space_code, &mask);
615 props[ncells++] = pci_bus_addr_to_host_addr(space_code,
616 config->assigned[i] & ~mask);
619 set_property(dev, "AAPL,address", (char *)props,
620 ncells * sizeof(cell));
623 static void pci_set_assigned_addresses(phandle_t phandle,
624 const pci_config_t *config, int num_bars)
626 phandle_t dev = phandle;
631 int flags, space_code;
634 for (i = 0; i < num_bars; i++) {
635 /* consider only bars with non-zero region size */
636 if (!config->sizes[i])
638 pci_decode_pci_addr(config->assigned[i],
639 &flags, &space_code, &mask);
641 ncells += pci_encode_phys_addr(props + ncells,
642 flags, space_code, config->dev,
643 PCI_BASE_ADDR_0 + (i * sizeof(uint32_t)),
644 config->assigned[i] & ~mask);
646 props[ncells++] = 0x00000000;
647 props[ncells++] = config->sizes[i];
650 set_property(dev, "assigned-addresses", (char *)props,
651 ncells * sizeof(props[0]));
654 /* call after writing "reg" property to update config->path */
655 static void ob_pci_reload_device_path(phandle_t phandle, pci_config_t *config)
657 /* since "name" and "reg" are now assigned
658 we need to reload current node name */
661 fword("get-package-path");
662 char *new_path = pop_fstr_copy();
664 if (0 != strcmp(config->path, new_path)) {
665 PCI_DPRINTF("\n=== CHANGED === package path old=%s new=%s\n",
666 config->path, new_path);
667 strncpy(config->path, new_path, sizeof(config->path));
668 config->path[sizeof(config->path)-1] = '\0';
672 PCI_DPRINTF("\n=== package path old=%s new=NULL\n", config->path);
676 static void pci_set_reg(phandle_t phandle,
677 pci_config_t *config, int num_bars)
679 phandle_t dev = phandle;
684 int space_code, flags;
688 /* first (addr, size) pair is the beginning of configuration address space */
689 ncells += pci_encode_phys_addr(props + ncells, 0, CONFIGURATION_SPACE,
692 ncells += pci_encode_size(props + ncells, 0);
694 for (i = 0; i < num_bars; i++) {
695 /* consider only bars with non-zero region size */
696 if (!config->sizes[i])
699 pci_decode_pci_addr(config->regions[i],
700 &flags, &space_code, &mask);
702 ncells += pci_encode_phys_addr(props + ncells,
703 flags, space_code, config->dev,
704 PCI_BASE_ADDR_0 + (i * sizeof(uint32_t)),
705 config->regions[i] & ~mask);
708 ncells += pci_encode_size(props + ncells, config->sizes[i]);
711 set_property(dev, "reg", (char *)props, ncells * sizeof(props[0]));
712 ob_pci_reload_device_path(dev, config);
714 #if defined(CONFIG_DEBUG_PCI)
715 dump_reg_property("pci_set_reg", ncells, props);
720 static void pci_set_ranges(const pci_config_t *config)
722 phandle_t dev = get_cur_dev();
731 for (i = 0; i < 6; i++) {
732 if (!config->assigned[i] || !config->sizes[i])
737 props[ncells++] = 0x00000000;
741 pci_decode_pci_addr(config->assigned[i],
742 &flags, &space_code, &mask);
743 ncells += pci_encode_phys_addr(props + ncells, flags, space_code,
744 config->dev, 0x10 + i * 4,
745 config->assigned[i] & ~mask);
749 props[ncells++] = config->sizes[i];
751 set_property(dev, "ranges", (char *)props, ncells * sizeof(props[0]));
754 int macio_heathrow_config_cb (const pci_config_t *config)
756 pci_set_ranges(config);
758 #ifdef CONFIG_DRIVER_MACIO
759 ob_macio_heathrow_init(config->path, config->assigned[0] & ~0x0000000F);
764 int macio_keylargo_config_cb (const pci_config_t *config)
766 pci_set_ranges(config);
768 #ifdef CONFIG_DRIVER_MACIO
769 ob_macio_keylargo_init(config->path, config->assigned[0] & ~0x0000000F);
774 int vga_config_cb (const pci_config_t *config)
777 uint32_t rom_size, size, mask;
778 int flags, space_code;
781 if (config->assigned[0] != 0x00000000) {
784 pci_decode_pci_addr(config->assigned[1],
785 &flags, &space_code, &mask);
787 rom = pci_bus_addr_to_host_addr(space_code,
788 config->assigned[1] & ~0x0000000F);
790 rom_size = config->sizes[1];
797 p = (const char *)rom;
798 if (p[0] == 'N' && p[1] == 'D' && p[2] == 'R' && p[3] == 'V') {
799 size = *(uint32_t*)(p + 4);
800 set_property(ph, "driver,AAPL,MacOS,PowerPC", p + 8, size);
804 /* Currently we don't read FCode from the hardware but execute it directly */
805 feval("['] vga-driver-fcode 2 cells + 1 byte-load");
808 /* Install special words for Mac On Linux */
817 int ebus_config_cb(const pci_config_t *config)
819 #ifdef CONFIG_DRIVER_EBUS
820 phandle_t dev = get_cur_dev();
825 int flags, space_code;
830 props[3] = find_dev("/");
832 set_property(dev, "interrupt-map", (char *)props, 5 * sizeof(props[0]));
834 props[0] = 0x000001ff;
835 props[1] = 0xffffffff;
837 set_property(dev, "interrupt-map-mask", (char *)props, 3 * sizeof(props[0]));
839 /* Build ranges property from the BARs */
841 for (i = 0; i < 6; i++) {
842 /* consider only bars with non-zero region size */
843 if (!config->sizes[i])
846 pci_decode_pci_addr(config->assigned[i],
847 &flags, &space_code, &mask);
849 props[ncells++] = PCI_BASE_ADDR_0 + (i * sizeof(uint32_t));
850 props[ncells++] = 0x0;
852 ncells += pci_encode_phys_addr(props + ncells,
853 flags, space_code, config->dev,
854 PCI_BASE_ADDR_0 + (i * sizeof(uint32_t)),
855 config->assigned[i] & ~mask);
857 props[ncells++] = config->sizes[i];
860 set_property(dev, "ranges", (char *)props, ncells * sizeof(props[0]));
862 /* Build eeprom node */
879 fword("device-name");
880 fword("finish-device");
882 #ifdef CONFIG_DRIVER_FLOPPY
883 ob_floppy_init(config->path, "fdthree", 0x3f0ULL, 0);
885 #ifdef CONFIG_DRIVER_PC_SERIAL
886 ob_pc_serial_init(config->path, "su", (PCI_BASE_ADDR_1 | 0ULL) << 32, 0x3f8ULL, 0);
888 #ifdef CONFIG_DRIVER_PC_KBD
889 ob_pc_kbd_init(config->path, "kb_ps2", (PCI_BASE_ADDR_1 | 0ULL) << 32, 0x60ULL, 0);
895 int i82378_config_cb(const pci_config_t *config)
897 #ifdef CONFIG_DRIVER_PC_SERIAL
898 ob_pc_serial_init(config->path, "serial", arch->io_base, 0x3f8ULL, 0);
900 #ifdef CONFIG_DRIVER_PC_KBD
901 ob_pc_kbd_init(config->path, "8042", arch->io_base, 0x60ULL, 0);
903 #ifdef CONFIG_DRIVER_IDE
904 ob_ide_init(config->path, 0x1f0, 0x3f6, 0x170, 0x376);
910 int usb_ohci_config_cb(const pci_config_t *config)
912 #ifdef CONFIG_DRIVER_USB
913 ob_usb_ohci_init(config->path, 0x80000000 | config->dev);
918 static void ob_pci_add_properties(phandle_t phandle,
919 pci_addr addr, const pci_dev_t *pci_dev,
920 const pci_config_t *config, int num_bars)
922 /* cannot use get_cur_dev() path resolution since "name" and "reg"
923 properties are being changed */
924 phandle_t dev=phandle;
926 uint16_t vendor_id, device_id;
931 vendor_id = pci_config_read16(addr, PCI_VENDOR_ID);
932 device_id = pci_config_read16(addr, PCI_DEVICE_ID);
933 rev = pci_config_read8(addr, PCI_REVISION_ID);
934 class_prog = pci_config_read8(addr, PCI_CLASS_PROG);
935 class_code = pci_config_read16(addr, PCI_CLASS_DEVICE);
940 push_str(pci_dev->name);
941 fword("encode-string");
946 snprintf(path, sizeof(path),
947 "pci%x,%x", vendor_id, device_id);
949 fword("encode-string");
954 PCI_DPRINTF("*** missing pci_dev\n");
957 /* create properties as described in 2.5 */
959 set_int_property(dev, "vendor-id", vendor_id);
960 set_int_property(dev, "device-id", device_id);
961 set_int_property(dev, "revision-id", rev);
962 set_int_property(dev, "class-code", class_code << 8 | class_prog);
964 if (config->irq_pin) {
965 OLDWORLD(set_int_property(dev, "AAPL,interrupts",
967 #if defined(CONFIG_SPARC64)
968 set_int_property(dev, "interrupts", config->irq_pin);
970 NEWWORLD(set_int_property(dev, "interrupts", config->irq_pin));
974 set_int_property(dev, "min-grant", pci_config_read8(addr, PCI_MIN_GNT));
975 set_int_property(dev, "max-latency", pci_config_read8(addr, PCI_MAX_LAT));
977 status=pci_config_read16(addr, PCI_STATUS);
979 set_int_property(dev, "devsel-speed",
980 (status&PCI_STATUS_DEVSEL_MASK)>>10);
982 if(status&PCI_STATUS_FAST_BACK)
983 set_bool_property(dev, "fast-back-to-back");
984 if(status&PCI_STATUS_66MHZ)
985 set_bool_property(dev, "66mhz-capable");
986 if(status&PCI_STATUS_UDF)
987 set_bool_property(dev, "udf-supported");
989 id=pci_config_read16(addr, PCI_SUBSYSTEM_VENDOR_ID);
991 set_int_property(dev, "subsystem-vendor-id", id);
992 id=pci_config_read16(addr, PCI_SUBSYSTEM_ID);
994 set_int_property(dev, "subsystem-id", id);
996 set_int_property(dev, "cache-line-size",
997 pci_config_read16(addr, PCI_CACHE_LINE_SIZE));
1000 if (pci_dev->type) {
1001 push_str(pci_dev->type);
1002 fword("encode-string");
1003 push_str("device_type");
1006 if (pci_dev->model) {
1007 push_str(pci_dev->model);
1008 fword("encode-string");
1012 if (pci_dev->compat)
1013 set_property(dev, "compatible",
1014 pci_dev->compat, pci_compat_len(pci_dev));
1016 if (pci_dev->acells)
1017 set_int_property(dev, "#address-cells",
1019 if (pci_dev->scells)
1020 set_int_property(dev, "#size-cells",
1022 if (pci_dev->icells)
1023 set_int_property(dev, "#interrupt-cells",
1027 pci_set_assigned_addresses(phandle, config, num_bars);
1030 pci_set_AAPL_address(config);
1037 static char pci_xbox_blacklisted (int bus, int devnum, int fn)
1040 * The Xbox MCPX chipset is a derivative of the nForce 1
1041 * chipset. It almost has the same bus layout; some devices
1042 * cannot be used, because they have been removed.
1046 * Devices 00:00.1 and 00:00.2 used to be memory controllers on
1047 * the nForce chipset, but on the Xbox, using them will lockup
1050 if ((bus == 0) && (devnum == 0) && ((fn == 1) || (fn == 2)))
1054 * Bus 1 only contains a VGA controller at 01:00.0. When you try
1055 * to probe beyond that device, you only get garbage, which
1056 * could cause lockups.
1058 if ((bus == 1) && ((devnum != 0) || (fn != 0)))
1062 * Bus 2 used to contain the AGP controller, but the Xbox MCPX
1063 * doesn't have one. Probing it can cause lockups.
1069 * The device is not blacklisted.
1075 static void ob_pci_configure_bar(pci_addr addr, pci_config_t *config,
1076 int reg, int config_addr,
1078 unsigned long *mem_base,
1079 unsigned long *io_base)
1081 uint32_t smask, amask, size, reloc, min_align;
1084 config->assigned[reg] = 0x00000000;
1085 config->sizes[reg] = 0x00000000;
1087 if ((*p_omask & 0x0000000f) == 0x4) {
1088 /* 64 bits memory mapping */
1089 PCI_DPRINTF("Skipping 64 bit BARs for %s\n", config->path);
1093 config->regions[reg] = pci_config_read32(addr, config_addr);
1095 /* get region size */
1097 pci_config_write32(addr, config_addr, 0xffffffff);
1098 smask = pci_config_read32(addr, config_addr);
1099 if (smask == 0x00000000 || smask == 0xffffffff)
1102 if (smask & 0x00000001 && reg != 6) {
1110 min_align = 1 << 16;
1113 smask |= 1; /* ROM */
1116 *p_omask = smask & amask;
1118 size = (~smask) + 1;
1119 config->sizes[reg] = size;
1121 if (size < min_align)
1123 reloc = (reloc + size -1) & ~(size - 1);
1124 if (*io_base == base) {
1125 PCI_DPRINTF("changing io_base from 0x%lx to 0x%x\n",
1126 *io_base, reloc + size);
1127 *io_base = reloc + size;
1129 PCI_DPRINTF("changing mem_base from 0x%lx to 0x%x\n",
1130 *mem_base, reloc + size);
1131 *mem_base = reloc + size;
1133 PCI_DPRINTF("Configuring BARs for %s: reloc 0x%x omask 0x%x "
1134 "io_base 0x%lx mem_base 0x%lx size 0x%x\n",
1135 config->path, reloc, *p_omask, *io_base, *mem_base, size);
1136 pci_config_write32(addr, config_addr, reloc | *p_omask);
1137 config->assigned[reg] = reloc | *p_omask;
1140 static void ob_pci_configure_irq(pci_addr addr, pci_config_t *config)
1142 uint8_t irq_pin, irq_line;
1144 irq_pin = pci_config_read8(addr, PCI_INTERRUPT_PIN);
1146 config->irq_pin = irq_pin;
1147 irq_pin = (((config->dev >> 11) & 0x1F) + irq_pin - 1) & 3;
1148 irq_line = arch->irqs[irq_pin];
1149 pci_config_write8(addr, PCI_INTERRUPT_LINE, irq_line);
1150 config->irq_line = irq_line;
1152 config->irq_line = -1;
1156 ob_pci_configure(pci_addr addr, pci_config_t *config, int num_regs, int rom_bar,
1157 unsigned long *mem_base, unsigned long *io_base)
1163 pci_addr config_addr;
1165 ob_pci_configure_irq(addr, config);
1168 for (reg = 0; reg < num_regs; ++reg) {
1169 config_addr = PCI_BASE_ADDR_0 + reg * 4;
1171 ob_pci_configure_bar(addr, config, reg, config_addr,
1177 config_addr = rom_bar;
1178 ob_pci_configure_bar(addr, config, reg, config_addr,
1179 &omask, mem_base, io_base);
1181 cmd = pci_config_read16(addr, PCI_COMMAND);
1182 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
1183 pci_config_write16(addr, PCI_COMMAND, cmd);
1186 static void ob_configure_pci_device(const char* parent_path,
1187 int *bus_num, unsigned long *mem_base, unsigned long *io_base,
1188 int bus, int devnum, int fn, int *p_is_multi);
1190 static void ob_scan_pci_bus(int *bus_num, unsigned long *mem_base,
1191 unsigned long *io_base, const char *path,
1194 int devnum, fn, is_multi;
1196 PCI_DPRINTF("\nScanning bus %d at %s...\n", bus, path);
1198 for (devnum = 0; devnum < 32; devnum++) {
1200 for (fn = 0; fn==0 || (is_multi && fn<8); fn++) {
1201 ob_configure_pci_device(path, bus_num, mem_base, io_base,
1202 bus, devnum, fn, &is_multi);
1208 static void ob_configure_pci_bridge(pci_addr addr,
1209 int *bus_num, unsigned long *mem_base,
1210 unsigned long *io_base,
1211 int primary_bus, pci_config_t *config)
1213 config->primary_bus = primary_bus;
1214 pci_config_write8(addr, PCI_PRIMARY_BUS, config->primary_bus);
1216 config->secondary_bus = *bus_num;
1217 pci_config_write8(addr, PCI_SECONDARY_BUS, config->secondary_bus);
1219 config->subordinate_bus = 0xff;
1220 pci_config_write8(addr, PCI_SUBORDINATE_BUS, config->subordinate_bus);
1222 PCI_DPRINTF("scanning new pci bus %u under bridge %s\n",
1223 config->secondary_bus, config->path);
1225 /* make pci bridge parent device, prepare for recursion */
1227 ob_scan_pci_bus(bus_num, mem_base, io_base,
1228 config->path, config->secondary_bus);
1230 /* bus scan updates *bus_num to last revealed pci bus number */
1231 config->subordinate_bus = *bus_num;
1232 pci_config_write8(addr, PCI_SUBORDINATE_BUS, config->subordinate_bus);
1234 PCI_DPRINTF("bridge %s PCI bus primary=%d secondary=%d subordinate=%d\n",
1235 config->path, config->primary_bus, config->secondary_bus,
1236 config->subordinate_bus);
1238 pci_set_bus_range(config);
1241 static int ob_pci_read_identification(int bus, int devnum, int fn,
1242 int *p_vid, int *p_did,
1243 uint8_t *p_class, uint8_t *p_subclass)
1250 if (pci_xbox_blacklisted (bus, devnum, fn))
1253 addr = PCI_ADDR(bus, devnum, fn);
1254 vid = pci_config_read16(addr, PCI_VENDOR_ID);
1255 did = pci_config_read16(addr, PCI_DEVICE_ID);
1257 if (vid==0xffff || vid==0) {
1269 ccode = pci_config_read16(addr, PCI_CLASS_DEVICE);
1272 *p_class = ccode >> 8;
1276 *p_subclass = ccode;
1282 static void ob_configure_pci_device(const char* parent_path,
1283 int *bus_num, unsigned long *mem_base, unsigned long *io_base,
1284 int bus, int devnum, int fn, int *p_is_multi)
1289 pci_config_t config = {};
1290 const pci_dev_t *pci_dev;
1291 uint8_t class, subclass, iface;
1292 int num_bars, rom_bar;
1294 phandle_t phandle = 0;
1295 int is_host_bridge = 0;
1297 if (!ob_pci_read_identification(bus, devnum, fn, &vid, &did, &class, &subclass)) {
1301 addr = PCI_ADDR(bus, devnum, fn);
1302 iface = pci_config_read8(addr, PCI_CLASS_PROG);
1304 pci_dev = pci_find_device(class, subclass, iface,
1307 PCI_DPRINTF("%x:%x.%x - %x:%x - ", bus, devnum, fn,
1310 htype = pci_config_read8(addr, PCI_HEADER_TYPE);
1314 *p_is_multi = htype & 0x80;
1318 /* stop adding host bridge accessible from it's primary bus
1319 PCI host bridge is to be added by host code
1321 if (class == PCI_BASE_CLASS_BRIDGE &&
1322 subclass == PCI_SUBCLASS_BRIDGE_HOST) {
1326 if (is_host_bridge) {
1327 /* reuse device tree node */
1328 PCI_DPRINTF("host bridge found - ");
1329 snprintf(config.path, sizeof(config.path),
1331 } else if (pci_dev == NULL || pci_dev->name == NULL) {
1332 snprintf(config.path, sizeof(config.path),
1333 "%s/pci%x,%x", parent_path, vid, did);
1336 snprintf(config.path, sizeof(config.path),
1337 "%s/%s", parent_path, pci_dev->name);
1340 PCI_DPRINTF("%s - ", config.path);
1342 config.dev = addr & 0x00FFFFFF;
1345 case PCI_BASE_CLASS_BRIDGE:
1346 if (subclass != PCI_SUBCLASS_BRIDGE_HOST) {
1347 REGISTER_NAMED_NODE_PHANDLE(ob_pci_bus_node, config.path, phandle);
1350 case PCI_CLASS_DISPLAY:
1351 REGISTER_NAMED_NODE_PHANDLE(ob_pci_empty_node, config.path, phandle);
1354 REGISTER_NAMED_NODE_PHANDLE(ob_pci_simple_node, config.path, phandle);
1358 if (is_host_bridge) {
1359 phandle = find_dev(config.path);
1361 if (get_property(phandle, "vendor-id", NULL)) {
1362 PCI_DPRINTF("host bridge already configured\n");
1367 activate_dev(phandle);
1369 if (htype & PCI_HEADER_TYPE_BRIDGE) {
1371 rom_bar = PCI_ROM_ADDRESS1;
1374 rom_bar = PCI_ROM_ADDRESS;
1377 ob_pci_configure(addr, &config, num_bars, rom_bar,
1380 ob_pci_add_properties(phandle, addr, pci_dev, &config, num_bars);
1382 if (!is_host_bridge) {
1383 pci_set_reg(phandle, &config, num_bars);
1386 /* call device-specific configuration callback */
1387 if (pci_dev && pci_dev->config_cb) {
1388 //activate_device(config.path);
1389 pci_dev->config_cb(&config);
1392 /* device is configured so we may move it out of scope */
1395 /* scan bus behind bridge device */
1396 //if (htype & PCI_HEADER_TYPE_BRIDGE && class == PCI_BASE_CLASS_BRIDGE) {
1397 if ( class == PCI_BASE_CLASS_BRIDGE &&
1398 ( subclass == PCI_SUBCLASS_BRIDGE_PCI ||
1399 subclass == PCI_SUBCLASS_BRIDGE_HOST ) ) {
1401 if (subclass == PCI_SUBCLASS_BRIDGE_PCI) {
1402 /* reserve next pci bus number for this PCI bridge */
1406 ob_configure_pci_bridge(addr, bus_num, mem_base, io_base, bus, &config);
1410 static void ob_pci_set_available(phandle_t host, unsigned long mem_base, unsigned long io_base)
1412 /* Create an available property for both memory and IO space */
1417 ncells += pci_encode_phys_addr(props + ncells, 0, MEMORY_SPACE_32, 0, 0, mem_base);
1418 ncells += pci_encode_size(props + ncells, arch->mem_len - mem_base);
1419 ncells += pci_encode_phys_addr(props + ncells, 0, IO_SPACE, 0, 0, io_base);
1420 ncells += pci_encode_size(props + ncells, arch->io_len - io_base);
1422 set_property(host, "available", (char *)props, ncells * sizeof(props[0]));
1425 /* Convert device/irq pin to interrupt property */
1426 #define SUN4U_INTERRUPT(dev, irq_pin) \
1427 ((((dev >> 11) << 2) + irq_pin - 1) & 0x1f)
1429 static void ob_pci_host_set_interrupt_map(phandle_t host)
1431 phandle_t dnode = 0, pci_childnode = 0;
1432 u32 props[128], intno;
1437 #if defined(CONFIG_PPC)
1438 phandle_t target_node;
1440 /* Oldworld macs do interrupt maps differently */
1444 dnode = dt_iterate_type(0, "open-pic");
1446 /* patch in openpic interrupt-parent properties */
1447 target_node = find_dev("/pci/mac-io");
1448 set_int_property(target_node, "interrupt-parent", dnode);
1450 target_node = find_dev("/pci/mac-io/escc/ch-a");
1451 set_int_property(target_node, "interrupt-parent", dnode);
1453 target_node = find_dev("/pci/mac-io/escc/ch-b");
1454 set_int_property(target_node, "interrupt-parent", dnode);
1456 target_node = find_dev("/pci/mac-io/escc-legacy/ch-a");
1457 set_int_property(target_node, "interrupt-parent", dnode);
1459 target_node = find_dev("/pci/mac-io/escc-legacy/ch-b");
1460 set_int_property(target_node, "interrupt-parent", dnode);
1462 /* QEMU only emulates 2 of the 3 ata buses currently */
1463 /* On a new world Mac these are not numbered but named by the
1464 * ATA version they support. Thus we have: ata-3, ata-3, ata-4
1465 * On g3beige they all called just ide.
1466 * We take 2 x ata-3 buses which seems to work for
1467 * at least the clients we care about */
1468 target_node = find_dev("/pci/mac-io/ata-3@20000");
1469 set_int_property(target_node, "interrupt-parent", dnode);
1471 target_node = find_dev("/pci/mac-io/ata-3@21000");
1472 set_int_property(target_node, "interrupt-parent", dnode);
1474 target_node = find_dev("/pci/mac-io/via-cuda");
1475 set_int_property(target_node, "interrupt-parent", dnode);
1477 target_node = find_dev("/pci");
1478 set_int_property(target_node, "interrupt-parent", dnode);
1481 /* PCI host bridge is the default interrupt controller */
1485 /* Set interrupt-map for PCI devices with an interrupt pin present */
1490 pci_childnode = POP();
1491 while (pci_childnode) {
1492 intno = get_int_property(pci_childnode, "interrupts", &len);
1494 reg = get_property(pci_childnode, "reg", &len);
1498 for (i = 0; i < (len / sizeof(u32)); i += 5) {
1501 /* Device address is in 1st 32-bit word of encoded PCI address for config space */
1502 if ((addr & PCI_RANGE_TYPE_MASK) == PCI_RANGE_CONFIG) {
1503 #if defined(CONFIG_SPARC64)
1504 ncells += pci_encode_phys_addr(props + ncells, 0, 0, addr, 0, 0);
1505 props[ncells++] = intno;
1506 props[ncells++] = dnode;
1507 props[ncells++] = SUN4U_INTERRUPT(addr, intno);
1508 #elif defined(CONFIG_PPC)
1509 ncells += pci_encode_phys_addr(props + ncells, 0, 0, addr, 0, 0);
1510 props[ncells++] = intno;
1511 props[ncells++] = dnode;
1512 props[ncells++] = arch->irqs[intno - 1];
1513 props[ncells++] = 3;
1515 /* Keep compiler quiet */
1523 PUSH(pci_childnode);
1525 pci_childnode = POP();
1527 set_property(host, "interrupt-map", (char *)props, ncells * sizeof(props[0]));
1529 props[0] = 0x0000f800;
1533 set_property(host, "interrupt-map-mask", (char *)props, 4 * sizeof(props[0]));
1536 int ob_pci_init(void)
1538 int bus, devnum, fn;
1539 uint8_t class, subclass;
1540 unsigned long mem_base, io_base;
1542 pci_config_t config = {}; /* host bridge */
1543 phandle_t phandle_host = 0;
1545 PCI_DPRINTF("Initializing PCI host bridge...\n");
1547 activate_device("/");
1549 /* Find all PCI bridges */
1551 mem_base = arch->pci_mem_base;
1552 /* I/O ports under 0x400 are used by devices mapped at fixed
1558 for (devnum = 0; devnum < 32; devnum++) {
1559 /* scan only fn 0 */
1562 if (!ob_pci_read_identification(bus, devnum, fn,
1563 0, 0, &class, &subclass)) {
1567 if (class != PCI_BASE_CLASS_BRIDGE || subclass != PCI_SUBCLASS_BRIDGE_HOST) {
1571 /* create root node for host PCI bridge */
1574 snprintf(config.path, sizeof(config.path), "/pci");
1576 REGISTER_NAMED_NODE_PHANDLE(ob_pci_bus_node, config.path, phandle_host);
1578 pci_host_set_reg(phandle_host);
1580 /* update device path after changing "reg" property */
1581 ob_pci_reload_device_path(phandle_host, &config);
1583 ob_configure_pci_device(config.path, &bus, &mem_base, &io_base,
1584 bus, devnum, fn, 0);
1586 /* we expect single host PCI bridge
1587 but this may be machine-specific */
1591 /* create available attributes for the PCI bridge */
1592 ob_pci_set_available(phandle_host, mem_base, io_base);
1594 /* configure the host bridge interrupt map */
1595 ob_pci_host_set_interrupt_map(phandle_host);