2 * iPXE driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Derived from Linux skge driver (v1.13), which was
4 * based on earlier sk98lin, e100 and FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features of the
7 * original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * Modified for iPXE, July 2008 by Michael Decker <mrd999@gmail.com>
13 * Tested and Modified in December 2009 by
14 * Thomas Miletich <thomas.miletich@gmail.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
31 FILE_LICENCE ( GPL2_ONLY );
37 #include <ipxe/netdevice.h>
38 #include <ipxe/ethernet.h>
39 #include <ipxe/if_ether.h>
40 #include <ipxe/iobuf.h>
41 #include <ipxe/malloc.h>
46 static struct pci_device_id skge_id_table[] = {
47 PCI_ROM(0x10b7, 0x1700, "3C940", "3COM 3C940", 0),
48 PCI_ROM(0x10b7, 0x80eb, "3C940B", "3COM 3C940", 0),
49 PCI_ROM(0x1148, 0x4300, "GE", "Syskonnect GE", 0),
50 PCI_ROM(0x1148, 0x4320, "YU", "Syskonnect YU", 0),
51 PCI_ROM(0x1186, 0x4C00, "DGE510T", "DLink DGE-510T", 0),
52 PCI_ROM(0x1186, 0x4b01, "DGE530T", "DLink DGE-530T", 0),
53 PCI_ROM(0x11ab, 0x4320, "id4320", "Marvell id4320", 0),
54 PCI_ROM(0x11ab, 0x5005, "id5005", "Marvell id5005", 0), /* Belkin */
55 PCI_ROM(0x1371, 0x434e, "Gigacard", "CNET Gigacard", 0),
56 PCI_ROM(0x1737, 0x1064, "EG1064", "Linksys EG1064", 0),
57 PCI_ROM(0x1737, 0xffff, "id_any", "Linksys [any]", 0)
60 static int skge_up(struct net_device *dev);
61 static void skge_down(struct net_device *dev);
62 static void skge_tx_clean(struct net_device *dev);
63 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
64 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
65 static void yukon_init(struct skge_hw *hw, int port);
66 static void genesis_mac_init(struct skge_hw *hw, int port);
67 static void genesis_link_up(struct skge_port *skge);
69 static void skge_phyirq(struct skge_hw *hw);
70 static void skge_poll(struct net_device *dev);
71 static int skge_xmit_frame(struct net_device *dev, struct io_buffer *iob);
72 static void skge_net_irq ( struct net_device *dev, int enable );
74 static void skge_rx_refill(struct net_device *dev);
76 static struct net_device_operations skge_operations = {
79 .transmit = skge_xmit_frame,
84 /* Avoid conditionals by using array */
85 static const int txqaddr[] = { Q_XA1, Q_XA2 };
86 static const int rxqaddr[] = { Q_R1, Q_R2 };
87 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
88 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
89 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
90 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
92 /* Determine supported/advertised modes based on hardware.
93 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
95 static u32 skge_supported_modes(const struct skge_hw *hw)
100 supported = SUPPORTED_10baseT_Half
101 | SUPPORTED_10baseT_Full
102 | SUPPORTED_100baseT_Half
103 | SUPPORTED_100baseT_Full
104 | SUPPORTED_1000baseT_Half
105 | SUPPORTED_1000baseT_Full
106 | SUPPORTED_Autoneg| SUPPORTED_TP;
108 if (hw->chip_id == CHIP_ID_GENESIS)
109 supported &= ~(SUPPORTED_10baseT_Half
110 | SUPPORTED_10baseT_Full
111 | SUPPORTED_100baseT_Half
112 | SUPPORTED_100baseT_Full);
114 else if (hw->chip_id == CHIP_ID_YUKON)
115 supported &= ~SUPPORTED_1000baseT_Half;
117 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
118 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
123 /* Chip internal frequency for clock calculations */
124 static inline u32 hwkhz(const struct skge_hw *hw)
126 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
129 /* Microseconds to chip HZ */
130 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
132 return hwkhz(hw) * usec / 1000;
135 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
136 static void skge_led(struct skge_port *skge, enum led_mode mode)
138 struct skge_hw *hw = skge->hw;
139 int port = skge->port;
141 if (hw->chip_id == CHIP_ID_GENESIS) {
144 if (hw->phy_type == SK_PHY_BCOM)
145 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
147 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
148 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
150 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
151 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
152 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
156 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
157 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
159 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
160 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
165 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
166 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
167 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
169 if (hw->phy_type == SK_PHY_BCOM)
170 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
172 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
173 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
174 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
181 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
182 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
183 PHY_M_LED_MO_DUP(MO_LED_OFF) |
184 PHY_M_LED_MO_10(MO_LED_OFF) |
185 PHY_M_LED_MO_100(MO_LED_OFF) |
186 PHY_M_LED_MO_1000(MO_LED_OFF) |
187 PHY_M_LED_MO_RX(MO_LED_OFF));
190 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
191 PHY_M_LED_PULS_DUR(PULS_170MS) |
192 PHY_M_LED_BLINK_RT(BLINK_84MS) |
196 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
197 PHY_M_LED_MO_RX(MO_LED_OFF) |
198 (skge->speed == SPEED_100 ?
199 PHY_M_LED_MO_100(MO_LED_ON) : 0));
202 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
203 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
204 PHY_M_LED_MO_DUP(MO_LED_ON) |
205 PHY_M_LED_MO_10(MO_LED_ON) |
206 PHY_M_LED_MO_100(MO_LED_ON) |
207 PHY_M_LED_MO_1000(MO_LED_ON) |
208 PHY_M_LED_MO_RX(MO_LED_ON));
214 * I've left in these EEPROM and VPD functions, as someone may desire to
215 * integrate them in the future. -mdeck
217 * static int skge_get_eeprom_len(struct net_device *dev)
219 * struct skge_port *skge = netdev_priv(dev);
222 * pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
223 * return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
226 * static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
230 * pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
233 * pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
234 * } while (!(offset & PCI_VPD_ADDR_F));
236 * pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
240 * static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
242 * pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
243 * pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
244 * offset | PCI_VPD_ADDR_F);
247 * pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
248 * } while (offset & PCI_VPD_ADDR_F);
251 * static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
254 * struct skge_port *skge = netdev_priv(dev);
255 * struct pci_dev *pdev = skge->hw->pdev;
256 * int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
257 * int length = eeprom->len;
258 * u16 offset = eeprom->offset;
263 * eeprom->magic = SKGE_EEPROM_MAGIC;
265 * while (length > 0) {
266 * u32 val = skge_vpd_read(pdev, cap, offset);
267 * int n = min_t(int, length, sizeof(val));
269 * memcpy(data, &val, n);
277 * static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
280 * struct skge_port *skge = netdev_priv(dev);
281 * struct pci_dev *pdev = skge->hw->pdev;
282 * int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
283 * int length = eeprom->len;
284 * u16 offset = eeprom->offset;
289 * if (eeprom->magic != SKGE_EEPROM_MAGIC)
292 * while (length > 0) {
294 * int n = min_t(int, length, sizeof(val));
296 * if (n < sizeof(val))
297 * val = skge_vpd_read(pdev, cap, offset);
298 * memcpy(&val, data, n);
300 * skge_vpd_write(pdev, cap, offset, val);
311 * Allocate ring elements and chain them together
312 * One-to-one association of board descriptors with ring elements
314 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base,
317 struct skge_tx_desc *d;
318 struct skge_element *e;
321 ring->start = zalloc(num*sizeof(*e));
325 for (i = 0, e = ring->start, d = vaddr; i < num; i++, e++, d++) {
328 e->next = ring->start;
329 d->next_offset = base;
332 d->next_offset = base + (i+1) * sizeof(*d);
335 ring->to_use = ring->to_clean = ring->start;
340 /* Allocate and setup a new buffer for receiving */
341 static void skge_rx_setup(struct skge_port *skge __unused,
342 struct skge_element *e,
343 struct io_buffer *iob, unsigned int bufsize)
345 struct skge_rx_desc *rd = e->desc;
348 map = ( iob != NULL ) ? virt_to_bus(iob->data) : 0;
351 rd->dma_hi = map >> 32;
353 rd->csum1_start = ETH_HLEN;
354 rd->csum2_start = ETH_HLEN;
360 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
363 /* Resume receiving using existing skb,
364 * Note: DMA address is not changed by chip.
365 * MTU not changed while receiver active.
367 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
369 struct skge_rx_desc *rd = e->desc;
372 rd->csum2_start = ETH_HLEN;
376 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
380 /* Free all buffers in receive ring, assumes receiver stopped */
381 static void skge_rx_clean(struct skge_port *skge)
383 struct skge_ring *ring = &skge->rx_ring;
384 struct skge_element *e;
388 struct skge_rx_desc *rd = e->desc;
394 } while ((e = e->next) != ring->start);
397 static void skge_link_up(struct skge_port *skge)
399 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
400 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
402 netdev_link_up(skge->netdev);
404 DBG2(PFX "%s: Link is up at %d Mbps, %s duplex\n",
405 skge->netdev->name, skge->speed,
406 skge->duplex == DUPLEX_FULL ? "full" : "half");
409 static void skge_link_down(struct skge_port *skge)
411 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
412 netdev_link_down(skge->netdev);
414 DBG2(PFX "%s: Link is down.\n", skge->netdev->name);
418 static void xm_link_down(struct skge_hw *hw, int port)
420 struct net_device *dev = hw->dev[port];
421 struct skge_port *skge = netdev_priv(dev);
423 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
425 if (netdev_link_ok(dev))
426 skge_link_down(skge);
429 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
433 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
434 *val = xm_read16(hw, port, XM_PHY_DATA);
436 if (hw->phy_type == SK_PHY_XMAC)
439 for (i = 0; i < PHY_RETRIES; i++) {
440 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
447 *val = xm_read16(hw, port, XM_PHY_DATA);
452 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
455 if (__xm_phy_read(hw, port, reg, &v))
456 DBG(PFX "%s: phy read timed out\n",
457 hw->dev[port]->name);
461 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
465 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
466 for (i = 0; i < PHY_RETRIES; i++) {
467 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
474 xm_write16(hw, port, XM_PHY_DATA, val);
475 for (i = 0; i < PHY_RETRIES; i++) {
476 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
483 static void genesis_init(struct skge_hw *hw)
485 /* set blink source counter */
486 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
487 skge_write8(hw, B2_BSC_CTRL, BSC_START);
489 /* configure mac arbiter */
490 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
492 /* configure mac arbiter timeout values */
493 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
494 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
495 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
496 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
498 skge_write8(hw, B3_MA_RCINI_RX1, 0);
499 skge_write8(hw, B3_MA_RCINI_RX2, 0);
500 skge_write8(hw, B3_MA_RCINI_TX1, 0);
501 skge_write8(hw, B3_MA_RCINI_TX2, 0);
503 /* configure packet arbiter timeout */
504 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
505 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
506 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
507 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
508 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
511 static void genesis_reset(struct skge_hw *hw, int port)
513 const u8 zero[8] = { 0 };
516 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
518 /* reset the statistics module */
519 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
520 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
521 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
522 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
523 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
525 /* disable Broadcom PHY IRQ */
526 if (hw->phy_type == SK_PHY_BCOM)
527 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
529 xm_outhash(hw, port, XM_HSM, zero);
531 /* Flush TX and RX fifo */
532 reg = xm_read32(hw, port, XM_MODE);
533 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
534 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
538 /* Convert mode to MII values */
539 static const u16 phy_pause_map[] = {
540 [FLOW_MODE_NONE] = 0,
541 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
542 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
543 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
546 /* special defines for FIBER (88E1011S only) */
547 static const u16 fiber_pause_map[] = {
548 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
549 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
550 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
551 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
555 /* Check status of Broadcom phy link */
556 static void bcom_check_link(struct skge_hw *hw, int port)
558 struct net_device *dev = hw->dev[port];
559 struct skge_port *skge = netdev_priv(dev);
562 /* read twice because of latch */
563 xm_phy_read(hw, port, PHY_BCOM_STAT);
564 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
566 if ((status & PHY_ST_LSYNC) == 0) {
567 xm_link_down(hw, port);
571 if (skge->autoneg == AUTONEG_ENABLE) {
574 if (!(status & PHY_ST_AN_OVER))
577 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
578 if (lpa & PHY_B_AN_RF) {
579 DBG(PFX "%s: remote fault\n",
584 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
586 /* Check Duplex mismatch */
587 switch (aux & PHY_B_AS_AN_RES_MSK) {
588 case PHY_B_RES_1000FD:
589 skge->duplex = DUPLEX_FULL;
591 case PHY_B_RES_1000HD:
592 skge->duplex = DUPLEX_HALF;
595 DBG(PFX "%s: duplex mismatch\n",
600 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
601 switch (aux & PHY_B_AS_PAUSE_MSK) {
602 case PHY_B_AS_PAUSE_MSK:
603 skge->flow_status = FLOW_STAT_SYMMETRIC;
606 skge->flow_status = FLOW_STAT_REM_SEND;
609 skge->flow_status = FLOW_STAT_LOC_SEND;
612 skge->flow_status = FLOW_STAT_NONE;
614 skge->speed = SPEED_1000;
617 if (!netdev_link_ok(dev))
618 genesis_link_up(skge);
621 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
622 * Phy on for 100 or 10Mbit operation
624 static void bcom_phy_init(struct skge_port *skge)
626 struct skge_hw *hw = skge->hw;
627 int port = skge->port;
629 u16 id1, r, ext, ctl;
631 /* magic workaround patterns for Broadcom */
632 static const struct {
636 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
637 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
638 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
639 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
641 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
642 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
645 /* read Id from external PHY (all have the same address) */
646 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
648 /* Optimize MDIO transfer by suppressing preamble. */
649 r = xm_read16(hw, port, XM_MMU_CMD);
651 xm_write16(hw, port, XM_MMU_CMD,r);
654 case PHY_BCOM_ID1_C0:
656 * Workaround BCOM Errata for the C0 type.
657 * Write magic patterns to reserved registers.
659 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
660 xm_phy_write(hw, port,
661 C0hack[i].reg, C0hack[i].val);
664 case PHY_BCOM_ID1_A1:
666 * Workaround BCOM Errata for the A1 type.
667 * Write magic patterns to reserved registers.
669 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
670 xm_phy_write(hw, port,
671 A1hack[i].reg, A1hack[i].val);
676 * Workaround BCOM Errata (#10523) for all BCom PHYs.
677 * Disable Power Management after reset.
679 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
680 r |= PHY_B_AC_DIS_PM;
681 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
684 xm_read16(hw, port, XM_ISRC);
686 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
687 ctl = PHY_CT_SP1000; /* always 1000mbit */
689 if (skge->autoneg == AUTONEG_ENABLE) {
691 * Workaround BCOM Errata #1 for the C5 type.
692 * 1000Base-T Link Acquisition Failure in Slave Mode
693 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
695 u16 adv = PHY_B_1000C_RD;
696 if (skge->advertising & ADVERTISED_1000baseT_Half)
697 adv |= PHY_B_1000C_AHD;
698 if (skge->advertising & ADVERTISED_1000baseT_Full)
699 adv |= PHY_B_1000C_AFD;
700 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
702 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
704 if (skge->duplex == DUPLEX_FULL)
705 ctl |= PHY_CT_DUP_MD;
707 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
710 /* Set autonegotiation pause parameters */
711 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
712 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
714 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
715 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
717 /* Use link status change interrupt */
718 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
721 static void xm_phy_init(struct skge_port *skge)
723 struct skge_hw *hw = skge->hw;
724 int port = skge->port;
727 if (skge->autoneg == AUTONEG_ENABLE) {
728 if (skge->advertising & ADVERTISED_1000baseT_Half)
730 if (skge->advertising & ADVERTISED_1000baseT_Full)
733 ctrl |= fiber_pause_map[skge->flow_control];
735 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
737 /* Restart Auto-negotiation */
738 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
740 /* Set DuplexMode in Config register */
741 if (skge->duplex == DUPLEX_FULL)
742 ctrl |= PHY_CT_DUP_MD;
744 * Do NOT enable Auto-negotiation here. This would hold
745 * the link down because no IDLEs are transmitted
749 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
751 /* Poll PHY for status changes */
752 skge->use_xm_link_timer = 1;
755 static int xm_check_link(struct net_device *dev)
757 struct skge_port *skge = netdev_priv(dev);
758 struct skge_hw *hw = skge->hw;
759 int port = skge->port;
762 /* read twice because of latch */
763 xm_phy_read(hw, port, PHY_XMAC_STAT);
764 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
766 if ((status & PHY_ST_LSYNC) == 0) {
767 xm_link_down(hw, port);
771 if (skge->autoneg == AUTONEG_ENABLE) {
774 if (!(status & PHY_ST_AN_OVER))
777 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
778 if (lpa & PHY_B_AN_RF) {
779 DBG(PFX "%s: remote fault\n",
784 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
786 /* Check Duplex mismatch */
787 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
789 skge->duplex = DUPLEX_FULL;
792 skge->duplex = DUPLEX_HALF;
795 DBG(PFX "%s: duplex mismatch\n",
800 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
801 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
802 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
803 (lpa & PHY_X_P_SYM_MD))
804 skge->flow_status = FLOW_STAT_SYMMETRIC;
805 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
806 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
807 /* Enable PAUSE receive, disable PAUSE transmit */
808 skge->flow_status = FLOW_STAT_REM_SEND;
809 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
810 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
811 /* Disable PAUSE receive, enable PAUSE transmit */
812 skge->flow_status = FLOW_STAT_LOC_SEND;
814 skge->flow_status = FLOW_STAT_NONE;
816 skge->speed = SPEED_1000;
819 if (!netdev_link_ok(dev))
820 genesis_link_up(skge);
824 /* Poll to check for link coming up.
826 * Since internal PHY is wired to a level triggered pin, can't
827 * get an interrupt when carrier is detected, need to poll for
830 static void xm_link_timer(struct skge_port *skge)
832 struct net_device *dev = skge->netdev;
833 struct skge_hw *hw = skge->hw;
834 int port = skge->port;
838 * Verify that the link by checking GPIO register three times.
839 * This pin has the signal from the link_sync pin connected to it.
841 for (i = 0; i < 3; i++) {
842 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
846 /* Re-enable interrupt to detect link down */
847 if (xm_check_link(dev)) {
848 u16 msk = xm_read16(hw, port, XM_IMSK);
849 msk &= ~XM_IS_INP_ASS;
850 xm_write16(hw, port, XM_IMSK, msk);
851 xm_read16(hw, port, XM_ISRC);
855 static void genesis_mac_init(struct skge_hw *hw, int port)
857 struct net_device *dev = hw->dev[port];
858 struct skge_port *skge = netdev_priv(dev);
861 const u8 zero[6] = { 0 };
863 for (i = 0; i < 10; i++) {
864 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
866 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
871 DBG(PFX "%s: genesis reset failed\n", dev->name);
874 /* Unreset the XMAC. */
875 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
878 * Perform additional initialization for external PHYs,
879 * namely for the 1000baseTX cards that use the XMAC's
882 if (hw->phy_type != SK_PHY_XMAC) {
883 /* Take external Phy out of reset */
884 r = skge_read32(hw, B2_GP_IO);
886 r |= GP_DIR_0|GP_IO_0;
888 r |= GP_DIR_2|GP_IO_2;
890 skge_write32(hw, B2_GP_IO, r);
892 /* Enable GMII interface */
893 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
897 switch(hw->phy_type) {
903 bcom_check_link(hw, port);
906 /* Set Station Address */
907 xm_outaddr(hw, port, XM_SA, dev->ll_addr);
909 /* We don't use match addresses so clear */
910 for (i = 1; i < 16; i++)
911 xm_outaddr(hw, port, XM_EXM(i), zero);
913 /* Clear MIB counters */
914 xm_write16(hw, port, XM_STAT_CMD,
915 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
916 /* Clear two times according to Errata #3 */
917 xm_write16(hw, port, XM_STAT_CMD,
918 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
920 /* configure Rx High Water Mark (XM_RX_HI_WM) */
921 xm_write16(hw, port, XM_RX_HI_WM, 1450);
923 /* We don't need the FCS appended to the packet. */
924 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
926 if (skge->duplex == DUPLEX_HALF) {
928 * If in manual half duplex mode the other side might be in
929 * full duplex mode, so ignore if a carrier extension is not seen
934 xm_write16(hw, port, XM_RX_CMD, r);
936 /* We want short frames padded to 60 bytes. */
937 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
939 xm_write16(hw, port, XM_TX_THR, 512);
942 * Enable the reception of all error frames. This is is
943 * a necessary evil due to the design of the XMAC. The
944 * XMAC's receive FIFO is only 8K in size, however jumbo
945 * frames can be up to 9000 bytes in length. When bad
946 * frame filtering is enabled, the XMAC's RX FIFO operates
947 * in 'store and forward' mode. For this to work, the
948 * entire frame has to fit into the FIFO, but that means
949 * that jumbo frames larger than 8192 bytes will be
950 * truncated. Disabling all bad frame filtering causes
951 * the RX FIFO to operate in streaming mode, in which
952 * case the XMAC will start transferring frames out of the
953 * RX FIFO as soon as the FIFO threshold is reached.
955 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
959 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
960 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
961 * and 'Octets Rx OK Hi Cnt Ov'.
963 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
966 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
967 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
968 * and 'Octets Tx OK Hi Cnt Ov'.
970 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
972 /* Configure MAC arbiter */
973 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
975 /* configure timeout values */
976 skge_write8(hw, B3_MA_TOINI_RX1, 72);
977 skge_write8(hw, B3_MA_TOINI_RX2, 72);
978 skge_write8(hw, B3_MA_TOINI_TX1, 72);
979 skge_write8(hw, B3_MA_TOINI_TX2, 72);
981 skge_write8(hw, B3_MA_RCINI_RX1, 0);
982 skge_write8(hw, B3_MA_RCINI_RX2, 0);
983 skge_write8(hw, B3_MA_RCINI_TX1, 0);
984 skge_write8(hw, B3_MA_RCINI_TX2, 0);
986 /* Configure Rx MAC FIFO */
987 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
988 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
989 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
991 /* Configure Tx MAC FIFO */
992 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
993 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
994 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
996 /* enable timeout timers */
997 skge_write16(hw, B3_PA_CTRL,
998 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1001 static void genesis_stop(struct skge_port *skge)
1003 struct skge_hw *hw = skge->hw;
1004 int port = skge->port;
1005 unsigned retries = 1000;
1008 /* Disable Tx and Rx */
1009 cmd = xm_read16(hw, port, XM_MMU_CMD);
1010 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1011 xm_write16(hw, port, XM_MMU_CMD, cmd);
1013 genesis_reset(hw, port);
1015 /* Clear Tx packet arbiter timeout IRQ */
1016 skge_write16(hw, B3_PA_CTRL,
1017 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1020 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1022 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1023 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1025 } while (--retries > 0);
1027 /* For external PHYs there must be special handling */
1028 if (hw->phy_type != SK_PHY_XMAC) {
1029 u32 reg = skge_read32(hw, B2_GP_IO);
1037 skge_write32(hw, B2_GP_IO, reg);
1038 skge_read32(hw, B2_GP_IO);
1041 xm_write16(hw, port, XM_MMU_CMD,
1042 xm_read16(hw, port, XM_MMU_CMD)
1043 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1045 xm_read16(hw, port, XM_MMU_CMD);
1048 static void genesis_link_up(struct skge_port *skge)
1050 struct skge_hw *hw = skge->hw;
1051 int port = skge->port;
1055 cmd = xm_read16(hw, port, XM_MMU_CMD);
1058 * enabling pause frame reception is required for 1000BT
1059 * because the XMAC is not reset if the link is going down
1061 if (skge->flow_status == FLOW_STAT_NONE ||
1062 skge->flow_status == FLOW_STAT_LOC_SEND)
1063 /* Disable Pause Frame Reception */
1064 cmd |= XM_MMU_IGN_PF;
1066 /* Enable Pause Frame Reception */
1067 cmd &= ~XM_MMU_IGN_PF;
1069 xm_write16(hw, port, XM_MMU_CMD, cmd);
1071 mode = xm_read32(hw, port, XM_MODE);
1072 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1073 skge->flow_status == FLOW_STAT_LOC_SEND) {
1075 * Configure Pause Frame Generation
1076 * Use internal and external Pause Frame Generation.
1077 * Sending pause frames is edge triggered.
1078 * Send a Pause frame with the maximum pause time if
1079 * internal oder external FIFO full condition occurs.
1080 * Send a zero pause time frame to re-start transmission.
1082 /* XM_PAUSE_DA = '010000C28001' (default) */
1083 /* XM_MAC_PTIME = 0xffff (maximum) */
1084 /* remember this value is defined in big endian (!) */
1085 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1087 mode |= XM_PAUSE_MODE;
1088 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1091 * disable pause frame generation is required for 1000BT
1092 * because the XMAC is not reset if the link is going down
1094 /* Disable Pause Mode in Mode Register */
1095 mode &= ~XM_PAUSE_MODE;
1097 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1100 xm_write32(hw, port, XM_MODE, mode);
1102 /* Turn on detection of Tx underrun */
1103 msk = xm_read16(hw, port, XM_IMSK);
1104 msk &= ~XM_IS_TXF_UR;
1105 xm_write16(hw, port, XM_IMSK, msk);
1107 xm_read16(hw, port, XM_ISRC);
1109 /* get MMU Command Reg. */
1110 cmd = xm_read16(hw, port, XM_MMU_CMD);
1111 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1112 cmd |= XM_MMU_GMII_FD;
1115 * Workaround BCOM Errata (#10523) for all BCom Phys
1116 * Enable Power Management after link up
1118 if (hw->phy_type == SK_PHY_BCOM) {
1119 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1120 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1121 & ~PHY_B_AC_DIS_PM);
1122 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1126 xm_write16(hw, port, XM_MMU_CMD,
1127 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1132 static inline void bcom_phy_intr(struct skge_port *skge)
1134 struct skge_hw *hw = skge->hw;
1135 int port = skge->port;
1138 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1139 DBGIO(PFX "%s: phy interrupt status 0x%x\n",
1140 skge->netdev->name, isrc);
1142 if (isrc & PHY_B_IS_PSE)
1143 DBG(PFX "%s: uncorrectable pair swap error\n",
1144 hw->dev[port]->name);
1146 /* Workaround BCom Errata:
1147 * enable and disable loopback mode if "NO HCD" occurs.
1149 if (isrc & PHY_B_IS_NO_HDCL) {
1150 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1151 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1152 ctrl | PHY_CT_LOOP);
1153 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1154 ctrl & ~PHY_CT_LOOP);
1157 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1158 bcom_check_link(hw, port);
1162 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1166 gma_write16(hw, port, GM_SMI_DATA, val);
1167 gma_write16(hw, port, GM_SMI_CTRL,
1168 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1169 for (i = 0; i < PHY_RETRIES; i++) {
1172 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1176 DBG(PFX "%s: phy write timeout port %x reg %x val %x\n",
1177 hw->dev[port]->name,
1182 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1186 gma_write16(hw, port, GM_SMI_CTRL,
1187 GM_SMI_CT_PHY_AD(hw->phy_addr)
1188 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1190 for (i = 0; i < PHY_RETRIES; i++) {
1192 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1198 *val = gma_read16(hw, port, GM_SMI_DATA);
1202 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1205 if (__gm_phy_read(hw, port, reg, &v))
1206 DBG(PFX "%s: phy read timeout port %x reg %x val %x\n",
1207 hw->dev[port]->name,
1212 /* Marvell Phy Initialization */
1213 static void yukon_init(struct skge_hw *hw, int port)
1215 struct skge_port *skge = netdev_priv(hw->dev[port]);
1216 u16 ctrl, ct1000, adv;
1218 if (skge->autoneg == AUTONEG_ENABLE) {
1219 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1221 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1222 PHY_M_EC_MAC_S_MSK);
1223 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1225 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1227 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1230 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1231 if (skge->autoneg == AUTONEG_DISABLE)
1232 ctrl &= ~PHY_CT_ANE;
1234 ctrl |= PHY_CT_RESET;
1235 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1241 if (skge->autoneg == AUTONEG_ENABLE) {
1243 if (skge->advertising & ADVERTISED_1000baseT_Full)
1244 ct1000 |= PHY_M_1000C_AFD;
1245 if (skge->advertising & ADVERTISED_1000baseT_Half)
1246 ct1000 |= PHY_M_1000C_AHD;
1247 if (skge->advertising & ADVERTISED_100baseT_Full)
1248 adv |= PHY_M_AN_100_FD;
1249 if (skge->advertising & ADVERTISED_100baseT_Half)
1250 adv |= PHY_M_AN_100_HD;
1251 if (skge->advertising & ADVERTISED_10baseT_Full)
1252 adv |= PHY_M_AN_10_FD;
1253 if (skge->advertising & ADVERTISED_10baseT_Half)
1254 adv |= PHY_M_AN_10_HD;
1256 /* Set Flow-control capabilities */
1257 adv |= phy_pause_map[skge->flow_control];
1259 if (skge->advertising & ADVERTISED_1000baseT_Full)
1260 adv |= PHY_M_AN_1000X_AFD;
1261 if (skge->advertising & ADVERTISED_1000baseT_Half)
1262 adv |= PHY_M_AN_1000X_AHD;
1264 adv |= fiber_pause_map[skge->flow_control];
1267 /* Restart Auto-negotiation */
1268 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1270 /* forced speed/duplex settings */
1271 ct1000 = PHY_M_1000C_MSE;
1273 if (skge->duplex == DUPLEX_FULL)
1274 ctrl |= PHY_CT_DUP_MD;
1276 switch (skge->speed) {
1278 ctrl |= PHY_CT_SP1000;
1281 ctrl |= PHY_CT_SP100;
1285 ctrl |= PHY_CT_RESET;
1288 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1290 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1291 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1293 /* Enable phy interrupt on autonegotiation complete (or link up) */
1294 if (skge->autoneg == AUTONEG_ENABLE)
1295 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1297 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1300 static void yukon_reset(struct skge_hw *hw, int port)
1302 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1303 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1304 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1305 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1306 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1308 gma_write16(hw, port, GM_RX_CTRL,
1309 gma_read16(hw, port, GM_RX_CTRL)
1310 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1313 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1314 static int is_yukon_lite_a0(struct skge_hw *hw)
1319 if (hw->chip_id != CHIP_ID_YUKON)
1322 reg = skge_read32(hw, B2_FAR);
1323 skge_write8(hw, B2_FAR + 3, 0xff);
1324 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1325 skge_write32(hw, B2_FAR, reg);
1329 static void yukon_mac_init(struct skge_hw *hw, int port)
1331 struct skge_port *skge = netdev_priv(hw->dev[port]);
1334 const u8 *addr = hw->dev[port]->ll_addr;
1336 /* WA code for COMA mode -- set PHY reset */
1337 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1338 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1339 reg = skge_read32(hw, B2_GP_IO);
1340 reg |= GP_DIR_9 | GP_IO_9;
1341 skge_write32(hw, B2_GP_IO, reg);
1345 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1346 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1348 /* WA code for COMA mode -- clear PHY reset */
1349 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1350 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1351 reg = skge_read32(hw, B2_GP_IO);
1354 skge_write32(hw, B2_GP_IO, reg);
1357 /* Set hardware config mode */
1358 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1359 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1360 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1362 /* Clear GMC reset */
1363 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1364 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1365 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1367 if (skge->autoneg == AUTONEG_DISABLE) {
1368 reg = GM_GPCR_AU_ALL_DIS;
1369 gma_write16(hw, port, GM_GP_CTRL,
1370 gma_read16(hw, port, GM_GP_CTRL) | reg);
1372 switch (skge->speed) {
1374 reg &= ~GM_GPCR_SPEED_100;
1375 reg |= GM_GPCR_SPEED_1000;
1378 reg &= ~GM_GPCR_SPEED_1000;
1379 reg |= GM_GPCR_SPEED_100;
1382 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1386 if (skge->duplex == DUPLEX_FULL)
1387 reg |= GM_GPCR_DUP_FULL;
1389 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1391 switch (skge->flow_control) {
1392 case FLOW_MODE_NONE:
1393 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1394 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1396 case FLOW_MODE_LOC_SEND:
1397 /* disable Rx flow-control */
1398 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1400 case FLOW_MODE_SYMMETRIC:
1401 case FLOW_MODE_SYM_OR_REM:
1402 /* enable Tx & Rx flow-control */
1406 gma_write16(hw, port, GM_GP_CTRL, reg);
1407 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1409 yukon_init(hw, port);
1412 reg = gma_read16(hw, port, GM_PHY_ADDR);
1413 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1415 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1416 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1417 gma_write16(hw, port, GM_PHY_ADDR, reg);
1419 /* transmit control */
1420 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1422 /* receive control reg: unicast + multicast + no FCS */
1423 gma_write16(hw, port, GM_RX_CTRL,
1424 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1426 /* transmit flow control */
1427 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1429 /* transmit parameter */
1430 gma_write16(hw, port, GM_TX_PARAM,
1431 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1432 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1433 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1435 /* configure the Serial Mode Register */
1436 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
1438 | IPG_DATA_VAL(IPG_DATA_DEF);
1440 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1442 /* physical address: used for pause frames */
1443 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1444 /* virtual address for data */
1445 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1447 /* enable interrupt mask for counter overflows */
1448 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1449 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1450 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1452 /* Initialize Mac Fifo */
1454 /* Configure Rx MAC FIFO */
1455 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1456 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1458 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1459 if (is_yukon_lite_a0(hw))
1460 reg &= ~GMF_RX_F_FL_ON;
1462 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1463 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1465 * because Pause Packet Truncation in GMAC is not working
1466 * we have to increase the Flush Threshold to 64 bytes
1467 * in order to flush pause packets in Rx FIFO on Yukon-1
1469 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1471 /* Configure Tx MAC FIFO */
1472 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1473 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1476 /* Go into power down mode */
1477 static void yukon_suspend(struct skge_hw *hw, int port)
1481 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1482 ctrl |= PHY_M_PC_POL_R_DIS;
1483 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1485 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1486 ctrl |= PHY_CT_RESET;
1487 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1489 /* switch IEEE compatible power down mode on */
1490 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1491 ctrl |= PHY_CT_PDOWN;
1492 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1495 static void yukon_stop(struct skge_port *skge)
1497 struct skge_hw *hw = skge->hw;
1498 int port = skge->port;
1500 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1501 yukon_reset(hw, port);
1503 gma_write16(hw, port, GM_GP_CTRL,
1504 gma_read16(hw, port, GM_GP_CTRL)
1505 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1506 gma_read16(hw, port, GM_GP_CTRL);
1508 yukon_suspend(hw, port);
1510 /* set GPHY Control reset */
1511 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1512 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1515 static u16 yukon_speed(const struct skge_hw *hw __unused, u16 aux)
1517 switch (aux & PHY_M_PS_SPEED_MSK) {
1518 case PHY_M_PS_SPEED_1000:
1520 case PHY_M_PS_SPEED_100:
1527 static void yukon_link_up(struct skge_port *skge)
1529 struct skge_hw *hw = skge->hw;
1530 int port = skge->port;
1533 /* Enable Transmit FIFO Underrun */
1534 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1536 reg = gma_read16(hw, port, GM_GP_CTRL);
1537 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1538 reg |= GM_GPCR_DUP_FULL;
1541 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1542 gma_write16(hw, port, GM_GP_CTRL, reg);
1544 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1548 static void yukon_link_down(struct skge_port *skge)
1550 struct skge_hw *hw = skge->hw;
1551 int port = skge->port;
1554 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1555 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1556 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1558 if (skge->flow_status == FLOW_STAT_REM_SEND) {
1559 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1560 ctrl |= PHY_M_AN_ASP;
1561 /* restore Asymmetric Pause bit */
1562 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
1565 skge_link_down(skge);
1567 yukon_init(hw, port);
1570 static void yukon_phy_intr(struct skge_port *skge)
1572 struct skge_hw *hw = skge->hw;
1573 int port = skge->port;
1574 const char *reason = NULL;
1575 u16 istatus, phystat;
1577 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1578 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1580 DBGIO(PFX "%s: phy interrupt status 0x%x 0x%x\n",
1581 skge->netdev->name, istatus, phystat);
1583 if (istatus & PHY_M_IS_AN_COMPL) {
1584 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1586 reason = "remote fault";
1590 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1591 reason = "master/slave fault";
1595 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1596 reason = "speed/duplex";
1600 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1601 ? DUPLEX_FULL : DUPLEX_HALF;
1602 skge->speed = yukon_speed(hw, phystat);
1604 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1605 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1606 case PHY_M_PS_PAUSE_MSK:
1607 skge->flow_status = FLOW_STAT_SYMMETRIC;
1609 case PHY_M_PS_RX_P_EN:
1610 skge->flow_status = FLOW_STAT_REM_SEND;
1612 case PHY_M_PS_TX_P_EN:
1613 skge->flow_status = FLOW_STAT_LOC_SEND;
1616 skge->flow_status = FLOW_STAT_NONE;
1619 if (skge->flow_status == FLOW_STAT_NONE ||
1620 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1621 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1623 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1624 yukon_link_up(skge);
1628 if (istatus & PHY_M_IS_LSP_CHANGE)
1629 skge->speed = yukon_speed(hw, phystat);
1631 if (istatus & PHY_M_IS_DUP_CHANGE)
1632 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1633 if (istatus & PHY_M_IS_LST_CHANGE) {
1634 if (phystat & PHY_M_PS_LINK_UP)
1635 yukon_link_up(skge);
1637 yukon_link_down(skge);
1641 DBG(PFX "%s: autonegotiation failed (%s)\n",
1642 skge->netdev->name, reason);
1644 /* XXX restart autonegotiation? */
1647 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
1653 end = start + len - 1;
1655 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1656 skge_write32(hw, RB_ADDR(q, RB_START), start);
1657 skge_write32(hw, RB_ADDR(q, RB_WP), start);
1658 skge_write32(hw, RB_ADDR(q, RB_RP), start);
1659 skge_write32(hw, RB_ADDR(q, RB_END), end);
1661 if (q == Q_R1 || q == Q_R2) {
1662 /* Set thresholds on receive queue's */
1663 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
1665 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
1668 /* Enable store & forward on Tx queue's because
1669 * Tx FIFO is only 4K on Genesis and 1K on Yukon
1671 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1674 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1677 /* Setup Bus Memory Interface */
1678 static void skge_qset(struct skge_port *skge, u16 q,
1679 const struct skge_element *e)
1681 struct skge_hw *hw = skge->hw;
1682 u32 watermark = 0x600;
1683 u64 base = skge->dma + (e->desc - skge->mem);
1685 /* optimization to reduce window on 32bit/33mhz */
1686 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
1689 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
1690 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
1691 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
1692 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
1695 void skge_free(struct net_device *dev)
1697 struct skge_port *skge = netdev_priv(dev);
1699 free(skge->rx_ring.start);
1700 skge->rx_ring.start = NULL;
1702 free(skge->tx_ring.start);
1703 skge->tx_ring.start = NULL;
1705 free_dma(skge->mem, RING_SIZE);
1710 static int skge_up(struct net_device *dev)
1712 struct skge_port *skge = netdev_priv(dev);
1713 struct skge_hw *hw = skge->hw;
1714 int port = skge->port;
1715 u32 chunk, ram_addr;
1718 DBG2(PFX "%s: enabling interface\n", dev->name);
1720 skge->mem = malloc_dma(RING_SIZE, SKGE_RING_ALIGN);
1721 skge->dma = virt_to_bus(skge->mem);
1724 memset(skge->mem, 0, RING_SIZE);
1726 assert(!(skge->dma & 7));
1728 /* FIXME: find out whether 64 bit iPXE will be loaded > 4GB */
1729 if ((u64)skge->dma >> 32 != ((u64) skge->dma + RING_SIZE) >> 32) {
1730 DBG(PFX "pci_alloc_consistent region crosses 4G boundary\n");
1735 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma, NUM_RX_DESC);
1739 /* this call relies on e->iob and d->control to be 0
1740 * This is assured by calling memset() on skge->mem and using zalloc()
1741 * for the skge_element structures.
1743 skge_rx_refill(dev);
1745 err = skge_ring_alloc(&skge->tx_ring, skge->mem + RX_RING_SIZE,
1746 skge->dma + RX_RING_SIZE, NUM_TX_DESC);
1750 /* Initialize MAC */
1751 if (hw->chip_id == CHIP_ID_GENESIS)
1752 genesis_mac_init(hw, port);
1754 yukon_mac_init(hw, port);
1756 /* Configure RAMbuffers - equally between ports and tx/rx */
1757 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
1758 ram_addr = hw->ram_offset + 2 * chunk * port;
1760 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
1761 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
1763 assert(!(skge->tx_ring.to_use != skge->tx_ring.to_clean));
1764 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
1765 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
1767 /* Start receiver BMU */
1769 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
1770 skge_led(skge, LED_MODE_ON);
1772 hw->intr_mask |= portmask[port];
1773 skge_write32(hw, B0_IMSK, hw->intr_mask);
1778 skge_rx_clean(skge);
1785 static void skge_rx_stop(struct skge_hw *hw, int port)
1787 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
1788 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
1789 RB_RST_SET|RB_DIS_OP_MD);
1790 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
1793 static void skge_down(struct net_device *dev)
1795 struct skge_port *skge = netdev_priv(dev);
1796 struct skge_hw *hw = skge->hw;
1797 int port = skge->port;
1799 if (skge->mem == NULL)
1802 DBG2(PFX "%s: disabling interface\n", dev->name);
1804 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
1805 skge->use_xm_link_timer = 0;
1807 netdev_link_down(dev);
1809 hw->intr_mask &= ~portmask[port];
1810 skge_write32(hw, B0_IMSK, hw->intr_mask);
1812 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1813 if (hw->chip_id == CHIP_ID_GENESIS)
1818 /* Stop transmitter */
1819 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
1820 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1821 RB_RST_SET|RB_DIS_OP_MD);
1824 /* Disable Force Sync bit and Enable Alloc bit */
1825 skge_write8(hw, SK_REG(port, TXA_CTRL),
1826 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1828 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1829 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1830 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1832 /* Reset PCI FIFO */
1833 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
1834 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1836 /* Reset the RAM Buffer async Tx queue */
1837 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
1839 skge_rx_stop(hw, port);
1841 if (hw->chip_id == CHIP_ID_GENESIS) {
1842 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
1843 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
1845 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1846 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1849 skge_led(skge, LED_MODE_OFF);
1853 skge_rx_clean(skge);
1859 static inline int skge_tx_avail(const struct skge_ring *ring)
1862 return ((ring->to_clean > ring->to_use) ? 0 : NUM_TX_DESC)
1863 + (ring->to_clean - ring->to_use) - 1;
1866 static int skge_xmit_frame(struct net_device *dev, struct io_buffer *iob)
1868 struct skge_port *skge = netdev_priv(dev);
1869 struct skge_hw *hw = skge->hw;
1870 struct skge_element *e;
1871 struct skge_tx_desc *td;
1875 if (skge_tx_avail(&skge->tx_ring) < 1)
1878 e = skge->tx_ring.to_use;
1880 assert(!(td->control & BMU_OWN));
1883 map = virt_to_bus(iob->data);
1886 td->dma_hi = map >> 32;
1888 control = BMU_CHECK;
1890 control |= BMU_EOF| BMU_IRQ_EOF;
1891 /* Make sure all the descriptors written */
1893 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
1896 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
1898 DBGIO(PFX "%s: tx queued, slot %td, len %d\n",
1899 dev->name, e - skge->tx_ring.start, (unsigned int)len);
1901 skge->tx_ring.to_use = e->next;
1904 if (skge_tx_avail(&skge->tx_ring) <= 1) {
1905 DBG(PFX "%s: transmit queue full\n", dev->name);
1911 /* Free all buffers in transmit ring */
1912 static void skge_tx_clean(struct net_device *dev)
1914 struct skge_port *skge = netdev_priv(dev);
1915 struct skge_element *e;
1917 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
1918 struct skge_tx_desc *td = e->desc;
1922 skge->tx_ring.to_clean = e;
1925 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
1927 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
1929 if (hw->chip_id == CHIP_ID_GENESIS)
1930 return status >> XMR_FS_LEN_SHIFT;
1932 return status >> GMR_FS_LEN_SHIFT;
1935 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
1937 if (hw->chip_id == CHIP_ID_GENESIS)
1938 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
1940 return (status & GMR_FS_ANY_ERR) ||
1941 (status & GMR_FS_RX_OK) == 0;
1944 /* Free all buffers in Tx ring which are no longer owned by device */
1945 static void skge_tx_done(struct net_device *dev)
1947 struct skge_port *skge = netdev_priv(dev);
1948 struct skge_ring *ring = &skge->tx_ring;
1949 struct skge_element *e;
1951 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
1953 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
1954 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
1956 if (control & BMU_OWN)
1959 netdev_tx_complete(dev, e->iob);
1961 skge->tx_ring.to_clean = e;
1963 /* Can run lockless until we need to synchronize to restart queue. */
1967 static void skge_rx_refill(struct net_device *dev)
1969 struct skge_port *skge = netdev_priv(dev);
1970 struct skge_ring *ring = &skge->rx_ring;
1971 struct skge_element *e;
1972 struct io_buffer *iob;
1973 struct skge_rx_desc *rd;
1977 for (i = 0; i < NUM_RX_DESC; i++) {
1981 control = rd->control;
1983 /* nothing to do here */
1984 if (iob || (control & BMU_OWN))
1987 DBG2("refilling rx desc %zd: ", (ring->to_clean - ring->start));
1989 iob = alloc_iob(RX_BUF_SIZE);
1991 skge_rx_setup(skge, e, iob, RX_BUF_SIZE);
1993 DBG("descr %zd: alloc_iob() failed\n",
1994 (ring->to_clean - ring->start));
1995 /* We pass the descriptor to the NIC even if the
1996 * allocation failed. The card will stop as soon as it
1997 * encounters a descriptor with the OWN bit set to 0,
1998 * thus never getting to the next descriptor that might
1999 * contain a valid io_buffer. This would effectively
2000 * stall the receive.
2002 skge_rx_setup(skge, e, NULL, 0);
2005 ring->to_clean = e->next;
2009 static void skge_rx_done(struct net_device *dev)
2011 struct skge_port *skge = netdev_priv(dev);
2012 struct skge_ring *ring = &skge->rx_ring;
2013 struct skge_rx_desc *rd;
2014 struct skge_element *e;
2015 struct io_buffer *iob;
2021 for (i = 0; i < NUM_RX_DESC; i++) {
2026 control = rd->control;
2028 if ((control & BMU_OWN))
2034 len = control & BMU_BBC;
2036 /* catch RX errors */
2037 if ((bad_phy_status(skge->hw, rd->status)) ||
2038 (phy_length(skge->hw, rd->status) != len)) {
2039 /* report receive errors */
2041 netdev_rx_err(dev, iob, -EIO);
2043 DBG2("received packet, len %d\n", len);
2045 netdev_rx(dev, iob);
2048 /* io_buffer passed to core, make sure we don't reuse it */
2053 skge_rx_refill(dev);
2056 static void skge_poll(struct net_device *dev)
2058 struct skge_port *skge = netdev_priv(dev);
2059 struct skge_hw *hw = skge->hw;
2062 /* reading this register ACKs interrupts */
2063 status = skge_read32(hw, B0_SP_ISRC);
2066 if (status & IS_EXT_REG) {
2068 if (skge->use_xm_link_timer)
2069 xm_link_timer(skge);
2074 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2078 /* restart receiver */
2080 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
2082 skge_read32(hw, B0_IMSK);
2087 static void skge_phyirq(struct skge_hw *hw)
2091 for (port = 0; port < hw->ports; port++) {
2092 struct net_device *dev = hw->dev[port];
2093 struct skge_port *skge = netdev_priv(dev);
2095 if (hw->chip_id != CHIP_ID_GENESIS)
2096 yukon_phy_intr(skge);
2097 else if (hw->phy_type == SK_PHY_BCOM)
2098 bcom_phy_intr(skge);
2101 hw->intr_mask |= IS_EXT_REG;
2102 skge_write32(hw, B0_IMSK, hw->intr_mask);
2103 skge_read32(hw, B0_IMSK);
2106 static const struct {
2110 { CHIP_ID_GENESIS, "Genesis" },
2111 { CHIP_ID_YUKON, "Yukon" },
2112 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2113 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2116 static const char *skge_board_name(const struct skge_hw *hw)
2119 static char buf[16];
2121 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2122 if (skge_chips[i].id == hw->chip_id)
2123 return skge_chips[i].name;
2125 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2131 * Setup the board data structure, but don't bring up
2134 static int skge_reset(struct skge_hw *hw)
2137 u16 ctst, pci_status;
2138 u8 t8, mac_cfg, pmd_type;
2141 ctst = skge_read16(hw, B0_CTST);
2144 skge_write8(hw, B0_CTST, CS_RST_SET);
2145 skge_write8(hw, B0_CTST, CS_RST_CLR);
2147 /* clear PCI errors, if any */
2148 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2149 skge_write8(hw, B2_TST_CTRL2, 0);
2151 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
2152 pci_write_config_word(hw->pdev, PCI_STATUS,
2153 pci_status | PCI_STATUS_ERROR_BITS);
2154 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2155 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2157 /* restore CLK_RUN bits (for Yukon-Lite) */
2158 skge_write16(hw, B0_CTST,
2159 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2161 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2162 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2163 pmd_type = skge_read8(hw, B2_PMD_TYP);
2164 hw->copper = (pmd_type == 'T' || pmd_type == '1');
2166 switch (hw->chip_id) {
2167 case CHIP_ID_GENESIS:
2168 switch (hw->phy_type) {
2170 hw->phy_addr = PHY_ADDR_XMAC;
2173 hw->phy_addr = PHY_ADDR_BCOM;
2176 DBG(PFX "unsupported phy type 0x%x\n",
2183 case CHIP_ID_YUKON_LITE:
2184 case CHIP_ID_YUKON_LP:
2185 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
2188 hw->phy_addr = PHY_ADDR_MARV;
2192 DBG(PFX "unsupported chip type 0x%x\n",
2197 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2198 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2199 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
2201 /* read the adapters RAM size */
2202 t8 = skge_read8(hw, B2_E_0);
2203 if (hw->chip_id == CHIP_ID_GENESIS) {
2205 /* special case: 4 x 64k x 36, offset = 0x80000 */
2206 hw->ram_size = 0x100000;
2207 hw->ram_offset = 0x80000;
2209 hw->ram_size = t8 * 512;
2212 hw->ram_size = 0x20000;
2214 hw->ram_size = t8 * 4096;
2216 hw->intr_mask = IS_HW_ERR;
2218 /* Use PHY IRQ for all but fiber based Genesis board */
2219 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
2220 hw->intr_mask |= IS_EXT_REG;
2222 if (hw->chip_id == CHIP_ID_GENESIS)
2225 /* switch power to VCC (WA for VAUX problem) */
2226 skge_write8(hw, B0_POWER_CTRL,
2227 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
2229 /* avoid boards with stuck Hardware error bits */
2230 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
2231 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
2232 DBG(PFX "stuck hardware sensor bit\n");
2233 hw->intr_mask &= ~IS_HW_ERR;
2236 /* Clear PHY COMA */
2237 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2238 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
2239 reg &= ~PCI_PHY_COMA;
2240 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
2241 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2244 for (i = 0; i < hw->ports; i++) {
2245 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2246 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2250 /* turn off hardware timer (unused) */
2251 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2252 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2253 skge_write8(hw, B0_LED, LED_STAT_ON);
2255 /* enable the Tx Arbiters */
2256 for (i = 0; i < hw->ports; i++)
2257 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2259 /* Initialize ram interface */
2260 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2262 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2263 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2264 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2265 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2266 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2267 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2268 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
2269 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
2270 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
2271 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
2272 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
2273 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
2275 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
2277 /* Set interrupt moderation for Transmit only
2278 * Receive interrupts avoided by NAPI
2280 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
2281 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
2282 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
2284 skge_write32(hw, B0_IMSK, hw->intr_mask);
2286 for (i = 0; i < hw->ports; i++) {
2287 if (hw->chip_id == CHIP_ID_GENESIS)
2288 genesis_reset(hw, i);
2296 /* Initialize network device */
2297 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
2298 int highmem __unused)
2300 struct skge_port *skge;
2301 struct net_device *dev = alloc_etherdev(sizeof(*skge));
2304 DBG(PFX "etherdev alloc failed\n");
2308 dev->dev = &hw->pdev->dev;
2310 skge = netdev_priv(dev);
2314 /* Auto speed and flow control */
2315 skge->autoneg = AUTONEG_ENABLE;
2316 skge->flow_control = FLOW_MODE_SYM_OR_REM;
2319 skge->advertising = skge_supported_modes(hw);
2321 hw->dev[port] = dev;
2325 /* read the mac address */
2326 memcpy(dev->hw_addr, (void *) (hw->regs + B2_MAC_1 + port*8), ETH_ALEN);
2331 static void skge_show_addr(struct net_device *dev)
2333 DBG2(PFX "%s: addr %s\n",
2334 dev->name, netdev_addr(dev));
2337 static int skge_probe(struct pci_device *pdev)
2339 struct net_device *dev, *dev1;
2341 int err, using_dac = 0;
2343 adjust_pci_device(pdev);
2346 hw = zalloc(sizeof(*hw));
2348 DBG(PFX "cannot allocate hardware struct\n");
2349 goto err_out_free_regions;
2354 hw->regs = (unsigned long)ioremap(pci_bar_start(pdev, PCI_BASE_ADDRESS_0),
2357 DBG(PFX "cannot map device registers\n");
2358 goto err_out_free_hw;
2361 err = skge_reset(hw);
2363 goto err_out_iounmap;
2365 DBG(PFX " addr 0x%llx irq %d chip %s rev %d\n",
2366 (unsigned long long)pdev->ioaddr, pdev->irq,
2367 skge_board_name(hw), hw->chip_rev);
2369 dev = skge_devinit(hw, 0, using_dac);
2371 goto err_out_led_off;
2373 netdev_init ( dev, &skge_operations );
2375 err = register_netdev(dev);
2377 DBG(PFX "cannot register net device\n");
2378 goto err_out_free_netdev;
2381 skge_show_addr(dev);
2383 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
2384 if (register_netdev(dev1) == 0)
2385 skge_show_addr(dev1);
2387 /* Failure to register second port need not be fatal */
2388 DBG(PFX "register of second port failed\n");
2390 netdev_nullify(dev1);
2394 pci_set_drvdata(pdev, hw);
2398 err_out_free_netdev:
2399 netdev_nullify(dev);
2402 skge_write16(hw, B0_LED, LED_STAT_OFF);
2404 iounmap((void*)hw->regs);
2407 err_out_free_regions:
2408 pci_set_drvdata(pdev, NULL);
2412 static void skge_remove(struct pci_device *pdev)
2414 struct skge_hw *hw = pci_get_drvdata(pdev);
2415 struct net_device *dev0, *dev1;
2420 if ((dev1 = hw->dev[1]))
2421 unregister_netdev(dev1);
2423 unregister_netdev(dev0);
2426 skge_write32(hw, B0_IMSK, 0);
2427 skge_read32(hw, B0_IMSK);
2429 skge_write16(hw, B0_LED, LED_STAT_OFF);
2430 skge_write8(hw, B0_CTST, CS_RST_SET);
2433 netdev_nullify(dev1);
2436 netdev_nullify(dev0);
2439 iounmap((void*)hw->regs);
2441 pci_set_drvdata(pdev, NULL);
2445 * Enable or disable IRQ masking.
2447 * @v netdev Device to control.
2448 * @v enable Zero to mask off IRQ, non-zero to enable IRQ.
2450 * This is a iPXE Network Driver API function.
2452 static void skge_net_irq ( struct net_device *dev, int enable ) {
2453 struct skge_port *skge = netdev_priv(dev);
2454 struct skge_hw *hw = skge->hw;
2457 hw->intr_mask |= portmask[skge->port];
2459 hw->intr_mask &= ~portmask[skge->port];
2460 skge_write32(hw, B0_IMSK, hw->intr_mask);
2463 struct pci_driver skge_driver __pci_driver = {
2464 .ids = skge_id_table,
2465 .id_count = ( sizeof (skge_id_table) / sizeof (skge_id_table[0]) ),
2466 .probe = skge_probe,
2467 .remove = skge_remove