6 * National Semiconductor "MacPhyter" network card driver
10 FILE_LICENCE ( GPL2_OR_LATER );
14 #include <ipxe/spi_bit.h>
17 #define NATSEMI_BAR_SIZE 0x100
19 /** A 32-bit packet descriptor */
20 struct natsemi_descriptor_32 {
21 /** Link to next descriptor */
23 /** Command / status */
27 } __attribute__ (( packed ));
29 /** A 64-bit packet descriptor */
30 struct natsemi_descriptor_64 {
31 /** Link to next descriptor */
35 /** Command / status */
37 /** Extended status */
39 } __attribute__ (( packed ));
41 /** A packet descriptor
43 * The 32-bit and 64-bit variants are overlaid such that "cmdsts" can
44 * be accessed as a common field, and the overall size is a power of
45 * two (to allow the descriptor ring length to be used as an
48 union natsemi_descriptor {
52 uint8_t reserved_a[16];
53 /** Command / status */
56 uint8_t reserved_b[12];
57 } __attribute__ (( packed )) common;
58 /** 64-bit descriptor */
59 struct natsemi_descriptor_64 d64;
60 /** 32-bit descriptor */
65 struct natsemi_descriptor_32 d32;
66 } __attribute__ (( packed )) d32pad;
69 /** Descriptor buffer size mask */
70 #define NATSEMI_DESC_SIZE_MASK 0xfff
72 /** Packet descriptor flags */
73 enum natsemi_descriptor_flags {
74 /** Descriptor is owned by NIC */
75 NATSEMI_DESC_OWN = 0x80000000UL,
76 /** Request descriptor interrupt */
77 NATSEMI_DESC_INTR = 0x20000000UL,
79 NATSEMI_DESC_OK = 0x08000000UL,
82 /** Command Register */
83 #define NATSEMI_CR 0x0000
84 #define NATSEMI_CR_RST 0x00000100UL /**< Reset */
85 #define NATSEMI_CR_RXR 0x00000020UL /**< Receiver reset */
86 #define NATSEMI_CR_TXR 0x00000010UL /**< Transmit reset */
87 #define NATSEMI_CR_RXE 0x00000004UL /**< Receiver enable */
88 #define NATSEMI_CR_TXE 0x00000001UL /**< Transmit enable */
90 /** Maximum time to wait for a reset, in milliseconds */
91 #define NATSEMI_RESET_MAX_WAIT_MS 100
93 /** Configuration and Media Status Register */
94 #define NATSEMI_CFG 0x0004
95 #define NATSEMI_CFG_LNKSTS 0x80000000UL /**< Link status */
96 #define NATSEMI_CFG_SPDSTS1 0x40000000UL /**< Speed status bit 1 */
97 #define NATSEMI_CFG_MODE_1000 0x00400000UL /**< 1000 Mb/s mode control */
98 #define NATSEMI_CFG_PCI64_DET 0x00002000UL /**< PCI 64-bit bus detected */
99 #define NATSEMI_CFG_DATA64_EN 0x00001000UL /**< 64-bit data enable */
100 #define NATSEMI_CFG_M64ADDR 0x00000800UL /**< 64-bit address enable */
101 #define NATSEMI_CFG_EXTSTS_EN 0x00000100UL /**< Extended status enable */
103 /** EEPROM Access Register */
104 #define NATSEMI_MEAR 0x0008
105 #define NATSEMI_MEAR_EESEL 0x00000008UL /**< EEPROM chip select */
106 #define NATSEMI_MEAR_EECLK 0x00000004UL /**< EEPROM serial clock */
107 #define NATSEMI_MEAR_EEDO 0x00000002UL /**< EEPROM data out */
108 #define NATSEMI_MEAR_EEDI 0x00000001UL /**< EEPROM data in */
110 /** Size of EEPROM (in bytes) */
111 #define NATSEMI_EEPROM_SIZE 32
113 /** Word offset of MAC address within sane EEPROM layout */
114 #define NATSEMI_EEPROM_MAC_SANE 0x0a
116 /** Word offset of MAC address within insane EEPROM layout */
117 #define NATSEMI_EEPROM_MAC_INSANE 0x06
119 /** PCI Test Control Register */
120 #define NATSEMI_PTSCR 0x000c
121 #define NATSEMI_PTSCR_EELOAD_EN 0x00000004UL /**< Enable EEPROM load */
123 /** Maximum time to wait for a configuration reload, in milliseconds */
124 #define NATSEMI_EELOAD_MAX_WAIT_MS 100
126 /** Interrupt Status Register */
127 #define NATSEMI_ISR 0x0010
128 #define NATSEMI_IRQ_TXDESC 0x00000080UL /**< TX descriptor */
129 #define NATSEMI_IRQ_RXDESC 0x00000002UL /**< RX descriptor */
131 /** Interrupt Mask Register */
132 #define NATSEMI_IMR 0x0014
134 /** Interrupt Enable Register */
135 #define NATSEMI_IER 0x0018
136 #define NATSEMI_IER_IE 0x00000001UL /**< Interrupt enable */
138 /** Transmit Descriptor Pointer */
139 #define NATSEMI_TXDP 0x0020
141 /** Transmit Descriptor Pointer High Dword (64-bit) */
142 #define NATSEMI_TXDP_HI_64 0x0024
144 /** Number of transmit descriptors */
145 #define NATSEMI_NUM_TX_DESC 4
147 /** Transmit configuration register (32-bit) */
148 #define NATSEMI_TXCFG_32 0x24
150 /** Transmit configuration register (64-bit) */
151 #define NATSEMI_TXCFG_64 0x28
152 #define NATSEMI_TXCFG_CSI 0x80000000UL /**< Carrier sense ignore */
153 #define NATSEMI_TXCFG_HBI 0x40000000UL /**< Heartbeat ignore */
154 #define NATSEMI_TXCFG_ATP 0x10000000UL /**< Automatic padding */
155 #define NATSEMI_TXCFG_ECRETRY 0x00800000UL /**< Excess collision retry */
156 #define NATSEMI_TXCFG_MXDMA(x) ( (x) << 20 ) /**< Max DMA burst size */
157 #define NATSEMI_TXCFG_FLTH(x) ( (x) << 8 ) /**< Fill threshold */
158 #define NATSEMI_TXCFG_DRTH(x) ( (x) << 0 ) /**< Drain threshold */
160 /** Max DMA burst size (encoded value)
162 * This represents 256-byte bursts on 83815 controllers and 512-byte
163 * bursts on 83820 controllers.
165 #define NATSEMI_TXCFG_MXDMA_DEFAULT NATSEMI_TXCFG_MXDMA ( 0x7 )
167 /** Fill threshold (in units of 32 bytes)
169 * Must be at least as large as the max DMA burst size, so use a value
172 #define NATSEMI_TXCFG_FLTH_DEFAULT NATSEMI_TXCFG_FLTH ( 512 / 32 )
174 /** Drain threshold (in units of 32 bytes)
176 * Start transmission once we receive a conservative 1024 bytes, to
177 * avoid FIFO underrun errors. (83815 does not allow us to specify a
178 * value of 0 for "wait until whole packet is present".)
180 * Fill threshold plus drain threshold must be less than the transmit
181 * FIFO size, which is 2kB on 83815 and 8kB on 83820.
183 #define NATSEMI_TXCFG_DRTH_DEFAULT NATSEMI_TXCFG_DRTH ( 1024 / 32 )
185 /** Receive Descriptor Pointer */
186 #define NATSEMI_RXDP 0x0030
188 /** Receive Descriptor Pointer High Dword (64-bit) */
189 #define NATSEMI_RXDP_HI_64 0x0034
191 /** Number of receive descriptors */
192 #define NATSEMI_NUM_RX_DESC 4
194 /** Receive buffer length */
195 #define NATSEMI_RX_MAX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
197 /** Receive configuration register (32-bit) */
198 #define NATSEMI_RXCFG_32 0x34
200 /** Receive configuration register (64-bit) */
201 #define NATSEMI_RXCFG_64 0x38
202 #define NATSEMI_RXCFG_ARP 0x40000000UL /**< Accept runt packets */
203 #define NATSEMI_RXCFG_ATX 0x10000000UL /**< Accept transmit packets */
204 #define NATSEMI_RXCFG_ALP 0x08000000UL /**< Accept long packets */
205 #define NATSEMI_RXCFG_MXDMA(x) ( (x) << 20 ) /**< Max DMA burst size */
206 #define NATSEMI_RXCFG_DRTH(x) ( (x) << 1 ) /**< Drain threshold */
208 /** Max DMA burst size (encoded value)
210 * This represents 256-byte bursts on 83815 controllers and 512-byte
211 * bursts on 83820 controllers.
213 #define NATSEMI_RXCFG_MXDMA_DEFAULT NATSEMI_RXCFG_MXDMA ( 0x7 )
215 /** Drain threshold (in units of 8 bytes)
217 * Start draining after 64 bytes.
219 * Must be large enough to allow packet's accept/reject status to be
220 * determined before draining begins.
222 #define NATSEMI_RXCFG_DRTH_DEFAULT NATSEMI_RXCFG_DRTH ( 64 / 8 )
224 /** Receive Filter/Match Control Register */
225 #define NATSEMI_RFCR 0x0048
226 #define NATSEMI_RFCR_RFEN 0x80000000UL /**< RX filter enable */
227 #define NATSEMI_RFCR_AAB 0x40000000UL /**< Accept all broadcast */
228 #define NATSEMI_RFCR_AAM 0x20000000UL /**< Accept all multicast */
229 #define NATSEMI_RFCR_AAU 0x10000000UL /**< Accept all unicast */
230 #define NATSEMI_RFCR_RFADDR( addr ) ( (addr) << 0 ) /**< Extended address */
231 #define NATSEMI_RFCR_RFADDR_MASK NATSEMI_RFCR_RFADDR ( 0x3ff )
233 /** Perfect match filter address base */
234 #define NATSEMI_RFADDR_PMATCH_BASE 0x000
236 /** Receive Filter/Match Data Register */
237 #define NATSEMI_RFDR 0x004c
238 #define NATSEMI_RFDR_BMASK 0x00030000UL /**< Byte mask */
239 #define NATSEMI_RFDR_DATA( value ) ( (value) & 0xffff ) /**< Filter data */
241 /** National Semiconductor network card flags */
242 enum natsemi_nic_flags {
243 /** EEPROM is little-endian */
244 NATSEMI_EEPROM_LITTLE_ENDIAN = 0x0001,
245 /** EEPROM layout is insane */
246 NATSEMI_EEPROM_INSANE = 0x0002,
247 /** Card supports 64-bit operation */
248 NATSEMI_64BIT = 0x0004,
249 /** Card supports 1000Mbps link */
250 NATSEMI_1000 = 0x0008,
253 /** A National Semiconductor descriptor ring */
254 struct natsemi_ring {
256 union natsemi_descriptor *desc;
257 /** Producer index */
259 /** Consumer index */
262 /** Number of descriptors */
264 /** Descriptor start address register */
269 * Initialise descriptor ring
271 * @v ring Descriptor ring
272 * @v count Number of descriptors
273 * @v reg Descriptor start address register
275 static inline __attribute__ (( always_inline)) void
276 natsemi_init_ring ( struct natsemi_ring *ring, unsigned int count,
282 /** A National Semiconductor network card */
288 /** SPI bit-bashing interface */
289 struct spi_bit_basher spibit;
291 struct spi_device eeprom;
293 /** Transmit descriptor ring */
294 struct natsemi_ring tx;
295 /** Receive descriptor ring */
296 struct natsemi_ring rx;
297 /** Receive I/O buffers */
298 struct io_buffer *rx_iobuf[NATSEMI_NUM_RX_DESC];
300 /** Link status (cache) */
305 * Check if card can access physical address
307 * @v natsemi National Semiconductor device
308 * @v address Physical address
309 * @v address_ok Card can access physical address
311 static inline __attribute__ (( always_inline )) int
312 natsemi_address_ok ( struct natsemi_nic *natsemi, physaddr_t address ) {
314 /* In a 32-bit build, all addresses can be accessed */
315 if ( sizeof ( physaddr_t ) <= sizeof ( uint32_t ) )
318 /* A 64-bit card can access all addresses */
319 if ( natsemi->flags & NATSEMI_64BIT )
322 /* A 32-bit card can access all addresses below 4GB */
323 if ( ( address & ~0xffffffffULL ) == 0 )
329 #endif /* _NATSEMI_H */