6 * Intel 10 Gigabit Ethernet virtual function network card driver
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
14 /** Control Register */
15 #define INTELXVF_CTRL 0x0000UL
16 #define INTELXVF_CTRL_RST 0x04000000UL /**< Function-level reset */
18 /** Link Status Register */
19 #define INTELXVF_LINKS 0x0010UL
20 #define INTELXVF_LINKS_UP 0x40000000UL /**< Link up */
22 /** Extended Interrupt Cause Read Register */
23 #define INTELXVF_EICR 0x0100UL
24 #define INTELXVF_EIRQ_RX0 0x00000001UL /**< RX queue 0 (via IVAR) */
25 #define INTELXVF_EIRQ_TX0 0x00000002UL /**< TX queue 0 (via IVAR) */
26 #define INTELXVF_EIRQ_MBOX 0x00000004UL /**< Mailbox (via IVARM) */
28 /** Extended Interrupt Mask Set/Read Register */
29 #define INTELXVF_EIMS 0x0108UL
31 /** Extended Interrupt Mask Clear Register */
32 #define INTELXVF_EIMC 0x010cUL
34 /** Interrupt Vector Allocation Register */
35 #define INTELXVF_IVAR 0x0120UL
36 #define INTELXVF_IVAR_RX0(bit) ( (bit) << 0 ) /**< RX queue 0 allocation */
37 #define INTELXVF_IVAR_RX0_DEFAULT INTELXVF_IVAR_RX0 ( 0x00 )
38 #define INTELXVF_IVAR_RX0_MASK INTELXVF_IVAR_RX0 ( 0x01 )
39 #define INTELXVF_IVAR_RX0_VALID 0x00000080UL /**< RX queue 0 valid */
40 #define INTELXVF_IVAR_TX0(bit) ( (bit) << 8 ) /**< TX queue 0 allocation */
41 #define INTELXVF_IVAR_TX0_DEFAULT INTELXVF_IVAR_TX0 ( 0x01 )
42 #define INTELXVF_IVAR_TX0_MASK INTELXVF_IVAR_TX0 ( 0x01 )
43 #define INTELXVF_IVAR_TX0_VALID 0x00008000UL /**< TX queue 0 valid */
45 /** Interrupt Vector Allocation Miscellaneous Register */
46 #define INTELXVF_IVARM 0x0140UL
47 #define INTELXVF_IVARM_MBOX(bit) ( (bit) << 0 ) /**< Mailbox allocation */
48 #define INTELXVF_IVARM_MBOX_DEFAULT INTELXVF_IVARM_MBOX ( 0x02 )
49 #define INTELXVF_IVARM_MBOX_MASK INTELXVF_IVARM_MBOX ( 0x03 )
50 #define INTELXVF_IVARM_MBOX_VALID 0x00000080UL /**< Mailbox valid */
52 /** Mailbox Memory Register Base */
53 #define INTELXVF_MBMEM 0x0200UL
55 /** Mailbox Control Register */
56 #define INTELXVF_MBCTRL 0x02fcUL
58 /** Receive Descriptor register block */
59 #define INTELXVF_RD 0x1000UL
61 /** RX DCA Control Register */
62 #define INTELXVF_DCA_RXCTRL 0x100cUL
63 #define INTELXVF_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL /**< Must be zero */
65 /** Split Receive Control Register */
66 #define INTELXVF_SRRCTL 0x1014UL
67 #define INTELXVF_SRRCTL_BSIZE(kb) ( (kb) << 0 ) /**< Receive buffer size */
68 #define INTELXVF_SRRCTL_BSIZE_DEFAULT INTELXVF_SRRCTL_BSIZE ( 0x02 )
69 #define INTELXVF_SRRCTL_BSIZE_MASK INTELXVF_SRRCTL_BSIZE ( 0x1f )
70 #define INTELXVF_SRRCTL_DESCTYPE(typ) ( (typ) << 25 ) /**< Descriptor type */
71 #define INTELXVF_SRRCTL_DESCTYPE_DEFAULT INTELXVF_SRRCTL_DESCTYPE ( 0x00 )
72 #define INTELXVF_SRRCTL_DESCTYPE_MASK INTELXVF_SRRCTL_DESCTYPE ( 0x07 )
74 /** Good Packets Received Count */
75 #define INTELXVF_GPRC 0x101c
77 /** Good Packets Received Count Low */
78 #define INTELXVF_GORCL 0x1020
80 /** Good Packets Received Count High */
81 #define INTELXVF_GORCH 0x1024
83 /* Multicast Packets Received Count */
84 #define INTELXVF_MPRC 0x1034
86 /** Transmit Descriptor register block */
87 #define INTELXVF_TD 0x2000UL
89 /** Good Packets Transmitted Count */
90 #define INTELXVF_GPTC 0x201c
92 /** Good Packets Transmitted Count Low */
93 #define INTELXVF_GOTCL 0x2020
95 /** Good Packets Transmitted Count High */
96 #define INTELXVF_GOTCH 0x2024
98 /** Negotiate API version mailbox message */
99 #define INTELXVF_MSG_TYPE_VERSION 0x00000008UL
101 /** API version 1.1 */
102 #define INTELXVF_MSG_VERSION_1_1 0x00000002UL
104 #endif /* _INTELXVF_H */