6 * Davicom DM96xx USB Ethernet driver
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
13 #include <ipxe/usbnet.h>
14 #include <ipxe/if_ether.h>
16 /** Read register(s) */
17 #define DM96XX_READ_REGISTER \
18 ( USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \
19 USB_REQUEST_TYPE ( 0x00 ) )
21 /** Write register(s) */
22 #define DM96XX_WRITE_REGISTER \
23 ( USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \
24 USB_REQUEST_TYPE ( 0x01 ) )
26 /** Write single register */
27 #define DM96XX_WRITE1_REGISTER \
28 ( USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE | \
29 USB_REQUEST_TYPE ( 0x03 ) )
31 /** Network control register */
32 #define DM96XX_NCR 0x00
33 #define DM96XX_NCR_RST 0x01 /**< Software reset */
35 /** Network status register */
36 #define DM96XX_NSR 0x01
37 #define DM96XX_NSR_LINKST 0x40 /**< Link status */
39 /** Receive control register */
40 #define DM96XX_RCR 0x05
41 #define DM96XX_RCR_ALL 0x08 /**< Pass all multicast */
42 #define DM96XX_RCR_RUNT 0x04 /**< Pass runt packet */
43 #define DM96XX_RCR_PRMSC 0x02 /**< Promiscuous mode */
44 #define DM96XX_RCR_RXEN 0x01 /**< RX enable */
46 /** Receive status register */
47 #define DM96XX_RSR 0x06
48 #define DM96XX_RSR_MF 0x40 /**< Multicast frame */
50 /** PHY address registers */
51 #define DM96XX_PAR 0x10
53 /** Chip revision register */
54 #define DM96XX_CHIPR 0x2c
55 #define DM96XX_CHIPR_9601 0x00 /**< DM9601 */
56 #define DM96XX_CHIPR_9620 0x01 /**< DM9620 */
58 /** RX header control/status register (DM9620+ only) */
59 #define DM96XX_MODE_CTL 0x91
60 #define DM96XX_MODE_CTL_MODE 0x80 /**< 4-byte header mode */
62 /** DM96xx interrupt data */
63 struct dm96xx_interrupt {
64 /** Network status register */
66 /** Transmit status registers */
68 /** Receive status register */
70 /** Receive overflow counter register */
72 /** Receive packet counter */
74 /** Transmit packet counter */
76 /** General purpose register */
78 } __attribute__ (( packed ));
80 /** DM96xx receive header */
81 struct dm96xx_rx_header {
84 /** Packet length (excluding this header, including CRC) */
86 } __attribute__ (( packed ));
88 /** DM96xx transmit header */
89 struct dm96xx_tx_header {
90 /** Packet length (excluding this header) */
92 } __attribute__ (( packed ));
94 /** A DM96xx network device */
95 struct dm96xx_device {
97 struct usb_device *usb;
100 /** Network device */
101 struct net_device *netdev;
102 /** USB network device */
103 struct usbnet_device usbnet;
109 * @v dm96xx DM96xx device
110 * @v offset Register offset
111 * @v data Data buffer
112 * @v len Length of data
113 * @ret rc Return status code
115 static inline __attribute__ (( always_inline )) int
116 dm96xx_read_registers ( struct dm96xx_device *dm96xx, unsigned int offset,
117 void *data, size_t len ) {
119 return usb_control ( dm96xx->usb, DM96XX_READ_REGISTER, 0, offset,
126 * @v dm96xx DM96xx device
127 * @v offset Register offset
128 * @ret value Register value, or negative error
130 static inline __attribute__ (( always_inline )) int
131 dm96xx_read_register ( struct dm96xx_device *dm96xx, unsigned int offset ) {
135 if ( ( rc = dm96xx_read_registers ( dm96xx, offset, &value,
136 sizeof ( value ) ) ) != 0 )
144 * @v dm96xx DM96xx device
145 * @v offset Register offset
146 * @v data Data buffer
147 * @v len Length of data
148 * @ret rc Return status code
150 static inline __attribute__ (( always_inline )) int
151 dm96xx_write_registers ( struct dm96xx_device *dm96xx, unsigned int offset,
152 void *data, size_t len ) {
154 return usb_control ( dm96xx->usb, DM96XX_WRITE_REGISTER, 0, offset,
161 * @v dm96xx DM96xx device
162 * @v offset Register offset
163 * @v value Register value
164 * @ret rc Return status code
166 static inline __attribute__ (( always_inline )) int
167 dm96xx_write_register ( struct dm96xx_device *dm96xx, unsigned int offset,
170 return usb_control ( dm96xx->usb, DM96XX_WRITE1_REGISTER, value,
174 /** Reset delay (in microseconds) */
175 #define DM96XX_RESET_DELAY_US 10
177 /** Interrupt maximum fill level
179 * This is a policy decision.
181 #define DM96XX_INTR_MAX_FILL 2
183 /** Bulk IN maximum fill level
185 * This is a policy decision.
187 #define DM96XX_IN_MAX_FILL 8
189 /** Bulk IN buffer size */
190 #define DM96XX_IN_MTU \
191 ( 4 /* DM96xx header */ + ETH_FRAME_LEN + \
192 4 /* possible VLAN header */ + 4 /* CRC */ )
194 #endif /* _DM96XX_H */