2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5 * Original from Linux kernel 3.0.1
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <ipxe/malloc.h>
26 #include "ar9002_phy.h"
28 /* All code below is for AR5008, AR9001, AR9002 */
30 static const int firstep_table[] =
31 /* level: 0 1 2 3 4 5 6 7 8 */
32 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
34 static const int cycpwrThr1_table[] =
35 /* level: 0 1 2 3 4 5 6 7 8 */
36 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
39 * register values to turn OFDM weak signal detection OFF
41 static const int m1ThreshLow_off = 127;
42 static const int m2ThreshLow_off = 127;
43 static const int m1Thresh_off = 127;
44 static const int m2Thresh_off = 127;
45 static const int m2CountThr_off = 31;
46 static const int m2CountThrLow_off = 63;
47 static const int m1ThreshLowExt_off = 127;
48 static const int m2ThreshLowExt_off = 127;
49 static const int m1ThreshExt_off = 127;
50 static const int m2ThreshExt_off = 127;
53 static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
58 for (i = 0; i < array->ia_rows; i++)
59 bank[i] = INI_RA(array, i, col);
63 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
64 ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
66 static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
67 u32 *data, unsigned int *writecnt)
71 ENABLE_REGWRITE_BUFFER(ah);
73 for (r = 0; r < array->ia_rows; r++) {
74 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
78 REGWRITE_BUFFER_FLUSH(ah);
82 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
89 * Performs analog "swizzling" of parameters into their location.
90 * Used on external AR2133/AR5133 radios.
92 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
93 u32 numBits, u32 firstBit,
96 u32 tmp32, mask, arrayEntry, lastBit;
97 int32_t bitPosition, bitsLeft;
99 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
100 arrayEntry = (firstBit - 1) / 8;
101 bitPosition = (firstBit - 1) % 8;
103 while (bitsLeft > 0) {
104 lastBit = (bitPosition + bitsLeft > 8) ?
105 8 : bitPosition + bitsLeft;
106 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
108 rfBuf[arrayEntry] &= ~mask;
109 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
110 (column * 8)) & mask;
111 bitsLeft -= 8 - bitPosition;
112 tmp32 = tmp32 >> (8 - bitPosition);
119 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
125 * if synth_freq < 2412
127 * else if 2412 <= synth_freq <= 2422
129 * else // synth_freq > 2422
131 * else if forceBias > 0
132 * bias = forceBias & 7
134 * no change, use value from ini file
136 * no change, invalid band
139 * 2422 also uses value of 2
143 * Less than 2412 uses value of 0, 2412 and above uses value of 2
145 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
148 unsigned int reg_writes = 0;
151 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
154 if (synth_freq < 2412)
156 else if (synth_freq < 2422)
161 /* pre-reverse this field */
162 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
164 DBG("ath9k: Force rf_pwd_icsyndiv to %1d on %4d\n",
165 new_bias, synth_freq);
167 /* swizzle rf_pwd_icsyndiv */
168 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
170 /* write Bank 6 with new params */
171 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
175 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
176 * @ah: atheros hardware structure
179 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
180 * the channel value. Assumes writes enabled to analog bus and bank6 register
181 * cache in ah->analogBank6Data.
183 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
190 struct chan_centers centers;
192 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
193 freq = centers.synth_center;
198 if (((freq - 2192) % 5) == 0) {
199 channelSel = ((freq - 672) * 2 - 3040) / 10;
201 } else if (((freq - 2224) % 5) == 0) {
202 channelSel = ((freq - 704) * 2 - 3040) / 10;
205 DBG("ath9k: Invalid channel %d MHz\n", freq);
209 channelSel = (channelSel << 2) & 0xff;
210 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
212 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
215 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
216 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
218 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
219 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
222 } else if ((freq % 20) == 0 && freq >= 5120) {
224 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
225 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
226 } else if ((freq % 10) == 0) {
228 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
229 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
230 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
232 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
233 } else if ((freq % 5) == 0) {
234 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
235 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
237 DBG("ath9k: Invalid channel %d MHz\n", freq);
241 ar5008_hw_force_bias(ah, freq);
244 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
247 REG_WRITE(ah, AR_PHY(0x37), reg32);
250 ah->curchan_rad_index = -1;
256 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
257 * @ah: atheros hardware structure
260 * For non single-chip solutions. Converts to baseband spur frequency given the
261 * input channel frequency and compute register settings below.
263 static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
264 struct ath9k_channel *chan)
266 int bb_spur = AR_NO_SPUR;
269 int spur_delta_phase;
271 int upper, lower, cur_vit_mask;
274 static int pilot_mask_reg[4] = {
275 AR_PHY_TIMING7, AR_PHY_TIMING8,
276 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
278 static int chan_mask_reg[4] = {
279 AR_PHY_TIMING9, AR_PHY_TIMING10,
280 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
282 static int inc[4] = { 0, 100, 0, 0 };
289 int is2GHz = IS_CHAN_2GHZ(chan);
291 memset(&mask_m, 0, sizeof(int8_t) * 123);
292 memset(&mask_p, 0, sizeof(int8_t) * 123);
294 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
295 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
296 if (AR_NO_SPUR == cur_bb_spur)
298 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
299 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
300 bb_spur = cur_bb_spur;
305 if (AR_NO_SPUR == bb_spur)
310 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
311 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
312 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
313 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
314 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
316 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
318 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
319 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
320 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
321 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
322 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
323 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
325 spur_delta_phase = ((bb_spur * 524288) / 100) &
326 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
328 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
329 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
331 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
332 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
333 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
334 REG_WRITE(ah, AR_PHY_TIMING11, new);
340 for (i = 0; i < 4; i++) {
344 for (bp = 0; bp < 30; bp++) {
345 if ((cur_bin > lower) && (cur_bin < upper)) {
346 pilot_mask = pilot_mask | 0x1 << bp;
347 chan_mask = chan_mask | 0x1 << bp;
352 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
353 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
360 for (i = 0; i < 123; i++) {
361 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
363 /* workaround for gcc bug #37014 */
364 volatile int tmp_v = abs(cur_vit_mask - bin);
370 if (cur_vit_mask < 0)
371 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
373 mask_p[cur_vit_mask / 100] = mask_amt;
378 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
379 | (mask_m[48] << 26) | (mask_m[49] << 24)
380 | (mask_m[50] << 22) | (mask_m[51] << 20)
381 | (mask_m[52] << 18) | (mask_m[53] << 16)
382 | (mask_m[54] << 14) | (mask_m[55] << 12)
383 | (mask_m[56] << 10) | (mask_m[57] << 8)
384 | (mask_m[58] << 6) | (mask_m[59] << 4)
385 | (mask_m[60] << 2) | (mask_m[61] << 0);
386 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
387 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
389 tmp_mask = (mask_m[31] << 28)
390 | (mask_m[32] << 26) | (mask_m[33] << 24)
391 | (mask_m[34] << 22) | (mask_m[35] << 20)
392 | (mask_m[36] << 18) | (mask_m[37] << 16)
393 | (mask_m[48] << 14) | (mask_m[39] << 12)
394 | (mask_m[40] << 10) | (mask_m[41] << 8)
395 | (mask_m[42] << 6) | (mask_m[43] << 4)
396 | (mask_m[44] << 2) | (mask_m[45] << 0);
397 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
398 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
400 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
401 | (mask_m[18] << 26) | (mask_m[18] << 24)
402 | (mask_m[20] << 22) | (mask_m[20] << 20)
403 | (mask_m[22] << 18) | (mask_m[22] << 16)
404 | (mask_m[24] << 14) | (mask_m[24] << 12)
405 | (mask_m[25] << 10) | (mask_m[26] << 8)
406 | (mask_m[27] << 6) | (mask_m[28] << 4)
407 | (mask_m[29] << 2) | (mask_m[30] << 0);
408 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
409 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
411 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
412 | (mask_m[2] << 26) | (mask_m[3] << 24)
413 | (mask_m[4] << 22) | (mask_m[5] << 20)
414 | (mask_m[6] << 18) | (mask_m[7] << 16)
415 | (mask_m[8] << 14) | (mask_m[9] << 12)
416 | (mask_m[10] << 10) | (mask_m[11] << 8)
417 | (mask_m[12] << 6) | (mask_m[13] << 4)
418 | (mask_m[14] << 2) | (mask_m[15] << 0);
419 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
420 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
422 tmp_mask = (mask_p[15] << 28)
423 | (mask_p[14] << 26) | (mask_p[13] << 24)
424 | (mask_p[12] << 22) | (mask_p[11] << 20)
425 | (mask_p[10] << 18) | (mask_p[9] << 16)
426 | (mask_p[8] << 14) | (mask_p[7] << 12)
427 | (mask_p[6] << 10) | (mask_p[5] << 8)
428 | (mask_p[4] << 6) | (mask_p[3] << 4)
429 | (mask_p[2] << 2) | (mask_p[1] << 0);
430 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
431 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
433 tmp_mask = (mask_p[30] << 28)
434 | (mask_p[29] << 26) | (mask_p[28] << 24)
435 | (mask_p[27] << 22) | (mask_p[26] << 20)
436 | (mask_p[25] << 18) | (mask_p[24] << 16)
437 | (mask_p[23] << 14) | (mask_p[22] << 12)
438 | (mask_p[21] << 10) | (mask_p[20] << 8)
439 | (mask_p[19] << 6) | (mask_p[18] << 4)
440 | (mask_p[17] << 2) | (mask_p[16] << 0);
441 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
442 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
444 tmp_mask = (mask_p[45] << 28)
445 | (mask_p[44] << 26) | (mask_p[43] << 24)
446 | (mask_p[42] << 22) | (mask_p[41] << 20)
447 | (mask_p[40] << 18) | (mask_p[39] << 16)
448 | (mask_p[38] << 14) | (mask_p[37] << 12)
449 | (mask_p[36] << 10) | (mask_p[35] << 8)
450 | (mask_p[34] << 6) | (mask_p[33] << 4)
451 | (mask_p[32] << 2) | (mask_p[31] << 0);
452 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
453 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
455 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
456 | (mask_p[59] << 26) | (mask_p[58] << 24)
457 | (mask_p[57] << 22) | (mask_p[56] << 20)
458 | (mask_p[55] << 18) | (mask_p[54] << 16)
459 | (mask_p[53] << 14) | (mask_p[52] << 12)
460 | (mask_p[51] << 10) | (mask_p[50] << 8)
461 | (mask_p[49] << 6) | (mask_p[48] << 4)
462 | (mask_p[47] << 2) | (mask_p[46] << 0);
463 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
464 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
468 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
469 * @ah: atheros hardware structure
471 * Only required for older devices with external AR2133/AR5133 radios.
473 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
475 #define ATH_ALLOC_BANK(bank, size) do { \
476 bank = zalloc((sizeof(u32) * size)); \
478 DBG("ath9k: Cannot allocate RF banks\n"); \
483 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
484 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
485 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
486 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
487 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
488 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
489 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
490 ATH_ALLOC_BANK(ah->addac5416_21,
491 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
492 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
495 #undef ATH_ALLOC_BANK
500 * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
501 * @ah: atheros hardware struture
502 * For the external AR2133/AR5133 radios banks.
504 static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
506 #define ATH_FREE_BANK(bank) do { \
511 ATH_FREE_BANK(ah->analogBank0Data);
512 ATH_FREE_BANK(ah->analogBank1Data);
513 ATH_FREE_BANK(ah->analogBank2Data);
514 ATH_FREE_BANK(ah->analogBank3Data);
515 ATH_FREE_BANK(ah->analogBank6Data);
516 ATH_FREE_BANK(ah->analogBank6TPCData);
517 ATH_FREE_BANK(ah->analogBank7Data);
518 ATH_FREE_BANK(ah->addac5416_21);
519 ATH_FREE_BANK(ah->bank6Temp);
525 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
526 * @ah: atheros hardware structure
530 * Used for the external AR2133/AR5133 radios.
532 * Reads the EEPROM header info from the device structure and programs
533 * all rf registers. This routine requires access to the analog
534 * rf device. This is not required for single-chip devices.
536 static int ar5008_hw_set_rf_regs(struct ath_hw *ah,
537 struct ath9k_channel *chan,
541 u32 ob5GHz = 0, db5GHz = 0;
542 u32 ob2GHz = 0, db2GHz = 0;
543 unsigned int regWrites = 0;
546 * Software does not need to program bank data
547 * for single chip devices, that is AR9280 or anything
550 if (AR_SREV_9280_20_OR_LATER(ah))
553 /* Setup rf parameters */
554 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
556 /* Setup Bank 0 Write */
557 ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
559 /* Setup Bank 1 Write */
560 ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
562 /* Setup Bank 2 Write */
563 ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
565 /* Setup Bank 6 Write */
566 ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
570 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
571 ah->analogBank6Data[i] =
572 INI_RA(&ah->iniBank6TPC, i, modesIndex);
576 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
577 if (eepMinorRev >= 2) {
578 if (IS_CHAN_2GHZ(chan)) {
579 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
580 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
581 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
583 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
586 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
587 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
588 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
590 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
595 /* Setup Bank 7 Setup */
596 ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
598 /* Write Analog registers */
599 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
601 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
603 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
605 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
607 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
609 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
615 static void ar5008_hw_init_bb(struct ath_hw *ah,
616 struct ath9k_channel *chan)
620 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
622 synthDelay = (4 * synthDelay) / 22;
626 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
628 udelay(synthDelay + BASE_ACTIVATE_DELAY);
631 static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
633 int rx_chainmask, tx_chainmask;
635 rx_chainmask = ah->rxchainmask;
636 tx_chainmask = ah->txchainmask;
639 switch (rx_chainmask) {
641 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
642 AR_PHY_SWAP_ALT_CHAIN);
644 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
645 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
646 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
652 ENABLE_REGWRITE_BUFFER(ah);
653 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
654 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
657 ENABLE_REGWRITE_BUFFER(ah);
661 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
663 REGWRITE_BUFFER_FLUSH(ah);
665 if (tx_chainmask == 0x5) {
666 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
667 AR_PHY_SWAP_ALT_CHAIN);
669 if (AR_SREV_9100(ah))
670 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
671 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
674 static void ar5008_hw_override_ini(struct ath_hw *ah,
675 struct ath9k_channel *chan __unused)
680 * Set the RX_ABORT and RX_DIS and clear if off only after
681 * RXE is set for MAC. This prevents frames with corrupted
684 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
686 if (AR_SREV_9280_20_OR_LATER(ah)) {
687 val = REG_READ(ah, AR_PCU_MISC_MODE2);
689 if (!AR_SREV_9271(ah))
690 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
692 if (AR_SREV_9287_11_OR_LATER(ah))
693 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
695 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
698 if (!AR_SREV_5416_20_OR_LATER(ah) ||
699 AR_SREV_9280_20_OR_LATER(ah))
702 * Disable BB clock gating
703 * Necessary to avoid issues on AR5416 2.0
705 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
708 * Disable RIFS search on some chips to avoid baseband
711 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
712 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
713 val &= ~AR_PHY_RIFS_INIT_DELAY;
714 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
718 static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
719 struct ath9k_channel *chan)
722 u32 enableDacFifo = 0;
724 if (AR_SREV_9285_12_OR_LATER(ah))
725 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
726 AR_PHY_FC_ENABLE_DAC_FIFO);
728 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
729 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
731 if (IS_CHAN_HT40(chan)) {
732 phymode |= AR_PHY_FC_DYN2040_EN;
734 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
735 (chan->chanmode == CHANNEL_G_HT40PLUS))
736 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
739 REG_WRITE(ah, AR_PHY_TURBO, phymode);
741 ath9k_hw_set11nmac2040(ah);
743 ENABLE_REGWRITE_BUFFER(ah);
745 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
746 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
748 REGWRITE_BUFFER_FLUSH(ah);
752 static int ar5008_hw_process_ini(struct ath_hw *ah,
753 struct ath9k_channel *chan)
755 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
756 struct ath_common *common = ath9k_hw_common(ah);
757 unsigned int i, regWrites = 0;
758 struct net80211_channel *channel = chan->chan;
759 u32 modesIndex, freqIndex;
761 switch (chan->chanmode) {
767 case CHANNEL_A_HT40PLUS:
768 case CHANNEL_A_HT40MINUS:
778 case CHANNEL_G_HT40PLUS:
779 case CHANNEL_G_HT40MINUS:
789 * Set correct baseband to analog shift setting to
790 * access analog chips.
792 REG_WRITE(ah, AR_PHY(0), 0x00000007);
794 /* Write ADDAC shifts */
795 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
796 ah->eep_ops->set_addac(ah, chan);
798 if (AR_SREV_5416_22_OR_LATER(ah)) {
799 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
801 struct ar5416IniArray temp;
803 sizeof(u32) * ah->iniAddac.ia_rows *
804 ah->iniAddac.ia_columns;
806 /* For AR5416 2.0/2.1 */
807 memcpy(ah->addac5416_21,
808 ah->iniAddac.ia_array, addacSize);
810 /* override CLKDRV value at [row, column] = [31, 1] */
811 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
813 temp.ia_array = ah->addac5416_21;
814 temp.ia_columns = ah->iniAddac.ia_columns;
815 temp.ia_rows = ah->iniAddac.ia_rows;
816 REG_WRITE_ARRAY(&temp, 1, regWrites);
819 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
821 ENABLE_REGWRITE_BUFFER(ah);
823 for (i = 0; i < ah->iniModes.ia_rows; i++) {
824 u32 reg = INI_RA(&ah->iniModes, i, 0);
825 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
827 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
828 val &= ~AR_AN_TOP2_PWDCLKIND;
830 REG_WRITE(ah, reg, val);
832 if (reg >= 0x7800 && reg < 0x78a0
833 && ah->config.analog_shiftreg
834 && (common->bus_ops->ath_bus_type != ATH_USB)) {
841 REGWRITE_BUFFER_FLUSH(ah);
843 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
844 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
846 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
847 AR_SREV_9287_11_OR_LATER(ah))
848 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
850 if (AR_SREV_9271_10(ah))
851 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
852 modesIndex, regWrites);
854 ENABLE_REGWRITE_BUFFER(ah);
856 /* Write common array parameters */
857 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
858 u32 reg = INI_RA(&ah->iniCommon, i, 0);
859 u32 val = INI_RA(&ah->iniCommon, i, 1);
861 REG_WRITE(ah, reg, val);
863 if (reg >= 0x7800 && reg < 0x78a0
864 && ah->config.analog_shiftreg
865 && (common->bus_ops->ath_bus_type != ATH_USB)) {
872 REGWRITE_BUFFER_FLUSH(ah);
874 if (AR_SREV_9271(ah)) {
875 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
876 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
877 modesIndex, regWrites);
879 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
880 modesIndex, regWrites);
883 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
885 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {
886 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
890 ar5008_hw_override_ini(ah, chan);
891 ar5008_hw_set_channel_regs(ah, chan);
892 ar5008_hw_init_chain_masks(ah);
896 ah->eep_ops->set_txpower(ah, chan,
897 ath9k_regd_get_ctl(regulatory, chan),
899 channel->maxpower * 2,
900 min((u32) MAX_RATE_POWER,
901 (u32) regulatory->power_limit), 0);
903 /* Write analog registers */
904 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
905 DBG("ath9k: ar5416SetRfRegs failed\n");
912 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
919 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
920 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
922 if (!AR_SREV_9280_20_OR_LATER(ah))
923 rfMode |= (IS_CHAN_5GHZ(chan)) ?
924 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
926 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
927 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
929 REG_WRITE(ah, AR_PHY_MODE, rfMode);
932 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
934 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
937 static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
938 struct ath9k_channel *chan)
940 u32 coef_scaled, ds_coef_exp, ds_coef_man;
941 u32 clockMhzScaled = 0x64000000;
942 struct chan_centers centers;
944 if (IS_CHAN_HALF_RATE(chan))
945 clockMhzScaled = clockMhzScaled >> 1;
946 else if (IS_CHAN_QUARTER_RATE(chan))
947 clockMhzScaled = clockMhzScaled >> 2;
949 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
950 coef_scaled = clockMhzScaled / centers.synth_center;
952 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
955 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
956 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
957 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
958 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
960 coef_scaled = (9 * coef_scaled) / 10;
962 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
965 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
966 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
967 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
968 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
971 static int ar5008_hw_rfbus_req(struct ath_hw *ah)
973 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
974 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
975 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
978 static void ar5008_hw_rfbus_done(struct ath_hw *ah)
980 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
981 if (IS_CHAN_B(ah->curchan))
982 synthDelay = (4 * synthDelay) / 22;
986 udelay(synthDelay + BASE_ACTIVATE_DELAY);
988 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
991 static void ar5008_restore_chainmask(struct ath_hw *ah)
993 int rx_chainmask = ah->rxchainmask;
995 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
996 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
997 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1001 static void ar5008_set_diversity(struct ath_hw *ah, int value)
1003 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1005 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1007 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1008 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1011 static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah __unused,
1012 struct ath9k_channel *chan)
1014 if (chan && IS_CHAN_5GHZ(chan))
1019 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah __unused,
1020 struct ath9k_channel *chan)
1024 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1026 if (chan && IS_CHAN_HALF_RATE(chan))
1027 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1028 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1029 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1031 if (chan && IS_CHAN_5GHZ(chan))
1032 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1034 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1039 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah __unused,
1040 struct ath9k_channel *chan)
1044 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1046 if (chan && IS_CHAN_HALF_RATE(chan))
1047 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1048 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1049 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1051 if (chan && IS_CHAN_5GHZ(chan))
1052 pll |= SM(0xa, AR_RTC_PLL_DIV);
1054 pll |= SM(0xb, AR_RTC_PLL_DIV);
1059 static int ar5008_hw_ani_control_old(struct ath_hw *ah,
1060 enum ath9k_ani_cmd cmd,
1063 struct ar5416AniState *aniState = &ah->curchan->ani;
1065 switch (cmd & ah->ani_function) {
1066 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
1069 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
1071 "level out of range (%d > %zd)\n",
1072 level, ARRAY_SIZE(ah->totalSizeDesired));
1076 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1077 AR_PHY_DESIRED_SZ_TOT_DES,
1078 ah->totalSizeDesired[level]);
1079 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1080 AR_PHY_AGC_CTL1_COARSE_LOW,
1081 ah->coarse_low[level]);
1082 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1083 AR_PHY_AGC_CTL1_COARSE_HIGH,
1084 ah->coarse_high[level]);
1085 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1086 AR_PHY_FIND_SIG_FIRPWR,
1089 if (level > aniState->noiseImmunityLevel)
1090 ah->stats.ast_ani_niup++;
1091 else if (level < aniState->noiseImmunityLevel)
1092 ah->stats.ast_ani_nidown++;
1093 aniState->noiseImmunityLevel = level;
1096 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1097 static const int m1ThreshLow[] = { 127, 50 };
1098 static const int m2ThreshLow[] = { 127, 40 };
1099 static const int m1Thresh[] = { 127, 0x4d };
1100 static const int m2Thresh[] = { 127, 0x40 };
1101 static const int m2CountThr[] = { 31, 16 };
1102 static const int m2CountThrLow[] = { 63, 48 };
1103 u32 on = param ? 1 : 0;
1105 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1106 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1108 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1109 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1111 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1112 AR_PHY_SFCORR_M1_THRESH,
1114 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1115 AR_PHY_SFCORR_M2_THRESH,
1117 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1118 AR_PHY_SFCORR_M2COUNT_THR,
1120 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1121 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1124 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1125 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1127 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1128 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1130 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1131 AR_PHY_SFCORR_EXT_M1_THRESH,
1133 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1134 AR_PHY_SFCORR_EXT_M2_THRESH,
1138 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1139 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1141 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1142 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1144 if (on != aniState->ofdmWeakSigDetect) {
1146 ah->stats.ast_ani_ofdmon++;
1148 ah->stats.ast_ani_ofdmoff++;
1149 aniState->ofdmWeakSigDetect = on;
1153 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
1154 static const int weakSigThrCck[] = { 8, 6 };
1155 u32 high = param ? 1 : 0;
1157 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
1158 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
1159 weakSigThrCck[high]);
1160 if (high != aniState->cckWeakSigThreshold) {
1162 ah->stats.ast_ani_cckhigh++;
1164 ah->stats.ast_ani_ccklow++;
1165 aniState->cckWeakSigThreshold = high;
1169 case ATH9K_ANI_FIRSTEP_LEVEL:{
1170 static const int firstep[] = { 0, 4, 8 };
1173 if (level >= ARRAY_SIZE(firstep)) {
1175 "level out of range (%d > %zd)\n",
1176 level, ARRAY_SIZE(firstep));
1179 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1180 AR_PHY_FIND_SIG_FIRSTEP,
1182 if (level > aniState->firstepLevel)
1183 ah->stats.ast_ani_stepup++;
1184 else if (level < aniState->firstepLevel)
1185 ah->stats.ast_ani_stepdown++;
1186 aniState->firstepLevel = level;
1189 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1190 static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1193 if (level >= ARRAY_SIZE(cycpwrThr1)) {
1195 "level out of range (%d > %zd)\n",
1196 level, ARRAY_SIZE(cycpwrThr1));
1199 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1200 AR_PHY_TIMING5_CYCPWR_THR1,
1202 if (level > aniState->spurImmunityLevel)
1203 ah->stats.ast_ani_spurup++;
1204 else if (level < aniState->spurImmunityLevel)
1205 ah->stats.ast_ani_spurdown++;
1206 aniState->spurImmunityLevel = level;
1209 case ATH9K_ANI_PRESENT:
1212 DBG("ath9k: invalid cmd %d\n", cmd);
1216 DBG2("ath9k: ANI parameters:\n");
1218 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetect=%d\n",
1219 aniState->noiseImmunityLevel,
1220 aniState->spurImmunityLevel,
1221 aniState->ofdmWeakSigDetect);
1223 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
1224 aniState->cckWeakSigThreshold,
1225 aniState->firstepLevel,
1226 aniState->listenTime);
1228 "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1229 aniState->ofdmPhyErrCount,
1230 aniState->cckPhyErrCount);
1235 static int ar5008_hw_ani_control_new(struct ath_hw *ah,
1236 enum ath9k_ani_cmd cmd,
1239 struct ath9k_channel *chan = ah->curchan;
1240 struct ar5416AniState *aniState = &chan->ani;
1243 switch (cmd & ah->ani_function) {
1244 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1246 * on == 1 means ofdm weak signal detection is ON
1247 * on == 1 is the default, for less noise immunity
1249 * on == 0 means ofdm weak signal detection is OFF
1250 * on == 0 means more noise imm
1252 u32 on = param ? 1 : 0;
1254 * make register setting for default
1255 * (weak sig detect ON) come from INI file
1257 int m1ThreshLow = on ?
1258 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1259 int m2ThreshLow = on ?
1260 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1262 aniState->iniDef.m1Thresh : m1Thresh_off;
1264 aniState->iniDef.m2Thresh : m2Thresh_off;
1265 int m2CountThr = on ?
1266 aniState->iniDef.m2CountThr : m2CountThr_off;
1267 int m2CountThrLow = on ?
1268 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1269 int m1ThreshLowExt = on ?
1270 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1271 int m2ThreshLowExt = on ?
1272 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1273 int m1ThreshExt = on ?
1274 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1275 int m2ThreshExt = on ?
1276 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1278 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1279 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1281 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1282 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1284 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1285 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
1286 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1287 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
1288 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1289 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
1290 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1291 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1294 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1295 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
1296 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1297 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
1298 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1299 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
1300 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1301 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
1304 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1305 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1307 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1308 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1310 if (on != aniState->ofdmWeakSigDetect) {
1312 "** ch %d: ofdm weak signal: %s=>%s\n",
1314 aniState->ofdmWeakSigDetect ?
1318 ah->stats.ast_ani_ofdmon++;
1320 ah->stats.ast_ani_ofdmoff++;
1321 aniState->ofdmWeakSigDetect = on;
1325 case ATH9K_ANI_FIRSTEP_LEVEL:{
1328 if (level >= ARRAY_SIZE(firstep_table)) {
1330 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%d > %zd)\n",
1331 level, ARRAY_SIZE(firstep_table));
1336 * make register setting relative to default
1337 * from INI file & cap value
1339 value = firstep_table[level] -
1340 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1341 aniState->iniDef.firstep;
1342 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1343 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1344 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1345 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1346 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1347 AR_PHY_FIND_SIG_FIRSTEP,
1350 * we need to set first step low register too
1351 * make register setting relative to default
1352 * from INI file & cap value
1354 value2 = firstep_table[level] -
1355 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1356 aniState->iniDef.firstepLow;
1357 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1358 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1359 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1360 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1362 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1363 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
1365 if (level != aniState->firstepLevel) {
1367 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1369 aniState->firstepLevel,
1371 ATH9K_ANI_FIRSTEP_LVL_NEW,
1373 aniState->iniDef.firstep);
1375 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1377 aniState->firstepLevel,
1379 ATH9K_ANI_FIRSTEP_LVL_NEW,
1381 aniState->iniDef.firstepLow);
1382 if (level > aniState->firstepLevel)
1383 ah->stats.ast_ani_stepup++;
1384 else if (level < aniState->firstepLevel)
1385 ah->stats.ast_ani_stepdown++;
1386 aniState->firstepLevel = level;
1390 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1393 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1395 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%d > %zd)\n",
1396 level, ARRAY_SIZE(cycpwrThr1_table));
1400 * make register setting relative to default
1401 * from INI file & cap value
1403 value = cycpwrThr1_table[level] -
1404 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1405 aniState->iniDef.cycpwrThr1;
1406 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1407 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1408 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1409 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1410 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1411 AR_PHY_TIMING5_CYCPWR_THR1,
1415 * set AR_PHY_EXT_CCA for extension channel
1416 * make register setting relative to default
1417 * from INI file & cap value
1419 value2 = cycpwrThr1_table[level] -
1420 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1421 aniState->iniDef.cycpwrThr1Ext;
1422 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1423 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1424 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1425 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1426 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1427 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
1429 if (level != aniState->spurImmunityLevel) {
1431 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1433 aniState->spurImmunityLevel,
1435 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1437 aniState->iniDef.cycpwrThr1);
1439 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1441 aniState->spurImmunityLevel,
1443 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1445 aniState->iniDef.cycpwrThr1Ext);
1446 if (level > aniState->spurImmunityLevel)
1447 ah->stats.ast_ani_spurup++;
1448 else if (level < aniState->spurImmunityLevel)
1449 ah->stats.ast_ani_spurdown++;
1450 aniState->spurImmunityLevel = level;
1454 case ATH9K_ANI_MRC_CCK:
1456 * You should not see this as AR5008, AR9001, AR9002
1457 * does not have hardware support for MRC CCK.
1460 case ATH9K_ANI_PRESENT:
1463 DBG("ath9k: invalid cmd %d\n", cmd);
1468 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1469 aniState->spurImmunityLevel,
1470 aniState->ofdmWeakSigDetect ? "on" : "off",
1471 aniState->firstepLevel,
1472 !aniState->mrcCCKOff ? "on" : "off",
1473 aniState->listenTime,
1474 aniState->ofdmPhyErrCount,
1475 aniState->cckPhyErrCount);
1479 static void ar5008_hw_do_getnf(struct ath_hw *ah,
1480 int16_t nfarray[NUM_NF_READINGS])
1484 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1485 nfarray[0] = sign_extend32(nf, 8);
1487 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
1488 nfarray[1] = sign_extend32(nf, 8);
1490 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
1491 nfarray[2] = sign_extend32(nf, 8);
1493 if (!IS_CHAN_HT40(ah->curchan))
1496 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1497 nfarray[3] = sign_extend32(nf, 8);
1499 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
1500 nfarray[4] = sign_extend32(nf, 8);
1502 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
1503 nfarray[5] = sign_extend32(nf, 8);
1507 * Initialize the ANI register values with default (ini) values.
1508 * This routine is called during a (full) hardware reset after
1509 * all the registers are initialised from the INI.
1511 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1513 struct ath9k_channel *chan = ah->curchan;
1514 struct ar5416AniState *aniState = &chan->ani;
1515 struct ath9k_ani_default *iniDef;
1518 iniDef = &aniState->iniDef;
1520 DBG2("ath9k: ver %d.%d chan %d Mhz/0x%x\n",
1521 ah->hw_version.macVersion,
1522 ah->hw_version.macRev,
1524 chan->channelFlags);
1526 val = REG_READ(ah, AR_PHY_SFCORR);
1527 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1528 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1529 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1531 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1532 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1533 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1534 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1536 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1537 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1538 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1539 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1540 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1541 iniDef->firstep = REG_READ_FIELD(ah,
1543 AR_PHY_FIND_SIG_FIRSTEP);
1544 iniDef->firstepLow = REG_READ_FIELD(ah,
1545 AR_PHY_FIND_SIG_LOW,
1546 AR_PHY_FIND_SIG_FIRSTEP_LOW);
1547 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1549 AR_PHY_TIMING5_CYCPWR_THR1);
1550 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1552 AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1554 /* these levels just got reset to defaults by the INI */
1555 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1556 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1557 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
1558 aniState->mrcCCKOff = 1; /* not available on pre AR9003 */
1561 static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1563 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1564 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1565 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1566 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1567 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1568 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1571 static void ar5008_hw_set_radar_params(struct ath_hw *ah,
1572 struct ath_hw_radar_conf *conf)
1574 u32 radar_0 = 0, radar_1 = 0;
1577 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1581 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1582 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1583 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1584 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1585 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1586 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1588 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1589 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1590 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1591 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1592 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1594 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1595 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1596 if (conf->ext_channel)
1597 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1599 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1602 static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1604 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1606 conf->fir_power = -33;
1607 conf->radar_rssi = 20;
1608 conf->pulse_height = 10;
1609 conf->pulse_rssi = 24;
1610 conf->pulse_inband = 15;
1611 conf->pulse_maxlen = 255;
1612 conf->pulse_inband_step = 12;
1613 conf->radar_inband = 8;
1616 void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1618 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1619 static const u32 ar5416_cca_regs[6] = {
1628 priv_ops->rf_set_freq = ar5008_hw_set_channel;
1629 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1631 priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
1632 priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
1633 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1634 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1635 priv_ops->init_bb = ar5008_hw_init_bb;
1636 priv_ops->process_ini = ar5008_hw_process_ini;
1637 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1638 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1639 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1640 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1641 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1642 priv_ops->restore_chainmask = ar5008_restore_chainmask;
1643 priv_ops->set_diversity = ar5008_set_diversity;
1644 priv_ops->do_getnf = ar5008_hw_do_getnf;
1645 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
1647 if (modparam_force_new_ani) {
1648 priv_ops->ani_control = ar5008_hw_ani_control_new;
1649 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1651 priv_ops->ani_control = ar5008_hw_ani_control_old;
1653 if (AR_SREV_9100(ah))
1654 priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
1655 else if (AR_SREV_9160_10_OR_LATER(ah))
1656 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1658 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
1660 ar5008_hw_set_nf_limits(ah);
1661 ar5008_hw_set_radar_conf(ah);
1662 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));