1 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
7 * Look for a PCI capability
9 * @v pci PCI device to query
10 * @v cap Capability code
11 * @ret address Address of capability, or 0 if not found
13 * Determine whether or not a device supports a given PCI capability.
14 * Returns the address of the requested capability structure within
15 * the device's PCI configuration space, or 0 if the device does not
18 int pci_find_capability ( struct pci_device *pci, int cap ) {
24 pci_read_config_word ( pci, PCI_STATUS, &status );
25 if ( ! ( status & PCI_STATUS_CAP_LIST ) )
28 pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdr_type );
29 switch ( hdr_type & PCI_HEADER_TYPE_MASK ) {
30 case PCI_HEADER_TYPE_NORMAL:
31 case PCI_HEADER_TYPE_BRIDGE:
33 pci_read_config_byte ( pci, PCI_CAPABILITY_LIST, &pos );
35 case PCI_HEADER_TYPE_CARDBUS:
36 pci_read_config_byte ( pci, PCI_CB_CAPABILITY_LIST, &pos );
39 while ( ttl-- && pos >= 0x40 ) {
41 pci_read_config_byte ( pci, pos + PCI_CAP_ID, &id );
42 DBG ( "PCI Capability: %d\n", id );
47 pci_read_config_byte ( pci, pos + PCI_CAP_NEXT, &pos );
53 * Find the size of a PCI BAR
56 * @v reg PCI register number
59 * It should not be necessary for any Etherboot code to call this
62 unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg ) {
66 /* Save the original command register */
67 pci_read_config_word ( pci, PCI_COMMAND, &cmd );
68 /* Save the original bar */
69 pci_read_config_dword ( pci, reg, &start );
70 /* Compute which bits can be set */
71 pci_write_config_dword ( pci, reg, ~0 );
72 pci_read_config_dword ( pci, reg, &size );
73 /* Restore the original size */
74 pci_write_config_dword ( pci, reg, start );
75 /* Find the significant bits */
76 /* Restore the original command register. This reenables decoding. */
77 pci_write_config_word ( pci, PCI_COMMAND, cmd );
78 if ( start & PCI_BASE_ADDRESS_SPACE_IO ) {
79 size &= ~PCI_BASE_ADDRESS_IO_MASK;
81 size &= ~PCI_BASE_ADDRESS_MEM_MASK;
83 /* Find the lowest bit set */
84 size = size & ~( size - 1 );