1 /******************************************************************************
2 * Copyright (c) 2004, 2011 IBM Corporation
4 * This program and the accompanying materials
5 * are made available under the terms of the BSD License
6 * which accompanies this distribution, and is available at
7 * http://www.opensource.org/licenses/bsd-license.php
10 * IBM Corporation - initial implementation
11 *****************************************************************************/
13 /* SLOF for QEMU -- boot code.
23 * __start loaded at 0x100
25 * CPU 0 starts at 0 with GPR3 pointing to the flat devtree
27 * All other CPUs are held in stopped state by qemu and are
37 .long relTag - __start
39 /* Some exception vectors
41 * FIXME: Also need 0280, 0380, 0f20, etc.
44 .irp i, 0x0100,0x0180,0x0200,0x0280,0x0300,0x0380,0x0400,0x0500, \
45 0x0600,0x0700,0x0800,0x0900,0x0a00,0x0b00,0x0c00,0x0d00, \
46 0x0e00,0x0f00,0x1000,0x1100,0x1200,0x1300,0x1400,0x1500, \
48 0x1800,0x1900,0x1a00,0x1b00,0x1c00,0x1d00,0x1e00,0x1f00, \
49 0x2000,0x2100,0x2200,0x2300,0x2400,0x2500,0x2600,0x2700, \
50 0x2800,0x2900,0x2a00,0x2b00,0x2c00,0x2d00,0x2e00
53 /* enable this if you get exceptions before the console works */
54 /* this will allow using the hardware debugger to see where */
55 /* it traps, and with what register values etc. */
74 . = XVECT_M_HANDLER - 0x100
78 /* Here's the startup code for the master CPU */
81 /* Save device-tree pointer */
84 /* Switch to 64-bit mode with 64-bit exceptions */
85 #define MSR_SF_LG 63 /* Enable 64 bit mode */
86 #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
87 #define __MASK(X) (1<<(X))
88 #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
89 #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode */
90 mfmsr r11 /* grab the current MSR */
91 li r12,(MSR_SF | MSR_ISF)@highest
121 /* write a character to the HV console */
122 putc: sldi r6,r3,(24+32)
134 C_ENTRY(proceedInterrupt)
136 ld r3,exception_stack_frame@got(r2)
139 .irp i, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, \
140 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
142 ld r\i, 0x30+\i*8 (r1)
154 ld 0,XVECT_M_HANDLER(0)
157 ld r0,0x30(r1); # restore vector number
163 mtctr r1 # save old stack pointer
166 .irp i, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, \
167 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
169 std r\i, 0x30+\i*8 (r1)
172 std r0,0x30(r1); # save vector number
175 std r14,0x38(r1); # save old r1
191 ld r3,exception_stack_frame@got(r2)
211 .irp i, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16, \
212 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \
214 ld r\i, 0x30+\i*8 (r1)
226 /* Set exception handler for given exception vector.
227 r3: exception vector offset
228 r4: exception handler
230 .globl .set_exception
235 .globl .set_exception_asm
237 .globl set_exception_asm
239 std r4, 0x60(r3) # fixme diff 1f - 0b