2 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
5 * Copyright (c) 2013 Hervé Poussineau
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/timer/m48t59.h"
28 #include "qapi/error.h"
29 #include "qemu/timer.h"
30 #include "sysemu/sysemu.h"
31 #include "hw/sysbus.h"
32 #include "hw/isa/isa.h"
33 #include "exec/address-spaces.h"
38 #if defined(DEBUG_NVRAM)
39 #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
41 #define NVRAM_PRINTF(fmt, ...) do { } while (0)
44 #define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
45 #define M48TXX_SYS_BUS_GET_CLASS(obj) \
46 OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
47 #define M48TXX_SYS_BUS_CLASS(klass) \
48 OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
49 #define M48TXX_SYS_BUS(obj) \
50 OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
52 #define TYPE_M48TXX_ISA "isa-m48txx"
53 #define M48TXX_ISA_GET_CLASS(obj) \
54 OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
55 #define M48TXX_ISA_CLASS(klass) \
56 OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
57 #define M48TXX_ISA(obj) \
58 OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
61 * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
62 * alarm and a watchdog timer and related control registers. In the
63 * PPC platform there is also a nvram lock function.
66 typedef struct M48txxInfo {
68 const char *sysbus_name;
69 uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
75 * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
76 * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
77 * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
80 typedef struct M48t59State {
81 /* Hardware parameters */
89 /* Alarm & watchdog */
91 QEMUTimer *alrm_timer;
95 /* Model parameters */
96 uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
102 typedef struct M48txxISAState {
103 ISADevice parent_obj;
109 typedef struct M48txxISADeviceClass {
110 ISADeviceClass parent_class;
112 } M48txxISADeviceClass;
114 typedef struct M48txxSysBusState {
115 SysBusDevice parent_obj;
120 typedef struct M48txxSysBusDeviceClass {
121 SysBusDeviceClass parent_class;
123 } M48txxSysBusDeviceClass;
125 static M48txxInfo m48txx_info[] = {
127 .sysbus_name = "sysbus-m48t02",
131 .sysbus_name = "sysbus-m48t08",
135 .sysbus_name = "sysbus-m48t59",
139 .isa_name = "isa-m48t59",
146 /* Fake timer functions */
148 /* Alarm management */
149 static void alarm_cb (void *opaque)
153 M48t59State *NVRAM = opaque;
155 qemu_set_irq(NVRAM->IRQ, 1);
156 if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
157 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
158 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
159 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
160 /* Repeat once a month */
161 qemu_get_timedate(&tm, NVRAM->time_offset);
163 if (tm.tm_mon == 13) {
167 next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
168 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
169 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
170 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
171 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
172 /* Repeat once a day */
173 next_time = 24 * 60 * 60;
174 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
175 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
176 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
177 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
178 /* Repeat once an hour */
180 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
181 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
182 (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
183 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
184 /* Repeat once a minute */
187 /* Repeat once a second */
190 timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +
192 qemu_set_irq(NVRAM->IRQ, 0);
195 static void set_alarm(M48t59State *NVRAM)
198 if (NVRAM->alrm_timer != NULL) {
199 timer_del(NVRAM->alrm_timer);
200 diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
202 timer_mod(NVRAM->alrm_timer, diff * 1000);
206 /* RTC management helpers */
207 static inline void get_time(M48t59State *NVRAM, struct tm *tm)
209 qemu_get_timedate(tm, NVRAM->time_offset);
212 static void set_time(M48t59State *NVRAM, struct tm *tm)
214 NVRAM->time_offset = qemu_timedate_diff(tm);
218 /* Watchdog management */
219 static void watchdog_cb (void *opaque)
221 M48t59State *NVRAM = opaque;
223 NVRAM->buffer[0x1FF0] |= 0x80;
224 if (NVRAM->buffer[0x1FF7] & 0x80) {
225 NVRAM->buffer[0x1FF7] = 0x00;
226 NVRAM->buffer[0x1FFC] &= ~0x40;
227 /* May it be a hw CPU Reset instead ? */
228 qemu_system_reset_request();
230 qemu_set_irq(NVRAM->IRQ, 1);
231 qemu_set_irq(NVRAM->IRQ, 0);
235 static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
237 uint64_t interval; /* in 1/16 seconds */
239 NVRAM->buffer[0x1FF0] &= ~0x80;
240 if (NVRAM->wd_timer != NULL) {
241 timer_del(NVRAM->wd_timer);
243 interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
244 timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
245 ((interval * 1000) >> 4));
250 /* Direct access to NVRAM */
251 static void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
256 if (addr > 0x1FF8 && addr < 0x2000)
257 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
259 /* check for NVRAM access */
260 if ((NVRAM->model == 2 && addr < 0x7f8) ||
261 (NVRAM->model == 8 && addr < 0x1ff8) ||
262 (NVRAM->model == 59 && addr < 0x1ff0)) {
269 /* flags register : read-only */
276 tmp = from_bcd(val & 0x7F);
277 if (tmp >= 0 && tmp <= 59) {
278 NVRAM->alarm.tm_sec = tmp;
279 NVRAM->buffer[0x1FF2] = val;
285 tmp = from_bcd(val & 0x7F);
286 if (tmp >= 0 && tmp <= 59) {
287 NVRAM->alarm.tm_min = tmp;
288 NVRAM->buffer[0x1FF3] = val;
294 tmp = from_bcd(val & 0x3F);
295 if (tmp >= 0 && tmp <= 23) {
296 NVRAM->alarm.tm_hour = tmp;
297 NVRAM->buffer[0x1FF4] = val;
303 tmp = from_bcd(val & 0x3F);
305 NVRAM->alarm.tm_mday = tmp;
306 NVRAM->buffer[0x1FF5] = val;
312 NVRAM->buffer[0x1FF6] = val;
316 NVRAM->buffer[0x1FF7] = val;
317 set_up_watchdog(NVRAM, val);
322 NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
327 tmp = from_bcd(val & 0x7F);
328 if (tmp >= 0 && tmp <= 59) {
329 get_time(NVRAM, &tm);
331 set_time(NVRAM, &tm);
333 if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
335 NVRAM->stop_time = time(NULL);
337 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
338 NVRAM->stop_time = 0;
341 NVRAM->buffer[addr] = val & 0x80;
346 tmp = from_bcd(val & 0x7F);
347 if (tmp >= 0 && tmp <= 59) {
348 get_time(NVRAM, &tm);
350 set_time(NVRAM, &tm);
356 tmp = from_bcd(val & 0x3F);
357 if (tmp >= 0 && tmp <= 23) {
358 get_time(NVRAM, &tm);
360 set_time(NVRAM, &tm);
365 /* day of the week / century */
366 tmp = from_bcd(val & 0x07);
367 get_time(NVRAM, &tm);
369 set_time(NVRAM, &tm);
370 NVRAM->buffer[addr] = val & 0x40;
375 tmp = from_bcd(val & 0x3F);
377 get_time(NVRAM, &tm);
379 set_time(NVRAM, &tm);
385 tmp = from_bcd(val & 0x1F);
386 if (tmp >= 1 && tmp <= 12) {
387 get_time(NVRAM, &tm);
389 set_time(NVRAM, &tm);
396 if (tmp >= 0 && tmp <= 99) {
397 get_time(NVRAM, &tm);
398 tm.tm_year = from_bcd(val) + NVRAM->base_year - 1900;
399 set_time(NVRAM, &tm);
403 /* Check lock registers state */
404 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
406 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
409 if (addr < NVRAM->size) {
410 NVRAM->buffer[addr] = val & 0xFF;
416 static uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
419 uint32_t retval = 0xFF;
421 /* check for NVRAM access */
422 if ((NVRAM->model == 2 && addr < 0x078f) ||
423 (NVRAM->model == 8 && addr < 0x1ff8) ||
424 (NVRAM->model == 59 && addr < 0x1ff0)) {
453 /* A read resets the watchdog */
454 set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
463 get_time(NVRAM, &tm);
464 retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
469 get_time(NVRAM, &tm);
470 retval = to_bcd(tm.tm_min);
475 get_time(NVRAM, &tm);
476 retval = to_bcd(tm.tm_hour);
480 /* day of the week / century */
481 get_time(NVRAM, &tm);
482 retval = NVRAM->buffer[addr] | tm.tm_wday;
487 get_time(NVRAM, &tm);
488 retval = to_bcd(tm.tm_mday);
493 get_time(NVRAM, &tm);
494 retval = to_bcd(tm.tm_mon + 1);
499 get_time(NVRAM, &tm);
500 retval = to_bcd((tm.tm_year + 1900 - NVRAM->base_year) % 100);
503 /* Check lock registers state */
504 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
506 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
509 if (addr < NVRAM->size) {
510 retval = NVRAM->buffer[addr];
514 if (addr > 0x1FF9 && addr < 0x2000)
515 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
520 static void m48t59_toggle_lock(M48t59State *NVRAM, int lock)
522 NVRAM->lock ^= 1 << lock;
525 /* IO access to NVRAM */
526 static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
529 M48t59State *NVRAM = opaque;
531 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
534 NVRAM->addr &= ~0x00FF;
538 NVRAM->addr &= ~0xFF00;
539 NVRAM->addr |= val << 8;
542 m48t59_write(NVRAM, NVRAM->addr, val);
543 NVRAM->addr = 0x0000;
550 static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)
552 M48t59State *NVRAM = opaque;
557 retval = m48t59_read(NVRAM, NVRAM->addr);
563 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
568 static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value)
570 M48t59State *NVRAM = opaque;
572 m48t59_write(NVRAM, addr, value & 0xff);
575 static void nvram_writew (void *opaque, hwaddr addr, uint32_t value)
577 M48t59State *NVRAM = opaque;
579 m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
580 m48t59_write(NVRAM, addr + 1, value & 0xff);
583 static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)
585 M48t59State *NVRAM = opaque;
587 m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
588 m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
589 m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
590 m48t59_write(NVRAM, addr + 3, value & 0xff);
593 static uint32_t nvram_readb (void *opaque, hwaddr addr)
595 M48t59State *NVRAM = opaque;
597 return m48t59_read(NVRAM, addr);
600 static uint32_t nvram_readw (void *opaque, hwaddr addr)
602 M48t59State *NVRAM = opaque;
605 retval = m48t59_read(NVRAM, addr) << 8;
606 retval |= m48t59_read(NVRAM, addr + 1);
610 static uint32_t nvram_readl (void *opaque, hwaddr addr)
612 M48t59State *NVRAM = opaque;
615 retval = m48t59_read(NVRAM, addr) << 24;
616 retval |= m48t59_read(NVRAM, addr + 1) << 16;
617 retval |= m48t59_read(NVRAM, addr + 2) << 8;
618 retval |= m48t59_read(NVRAM, addr + 3);
622 static const MemoryRegionOps nvram_ops = {
624 .read = { nvram_readb, nvram_readw, nvram_readl, },
625 .write = { nvram_writeb, nvram_writew, nvram_writel, },
627 .endianness = DEVICE_NATIVE_ENDIAN,
630 static const VMStateDescription vmstate_m48t59 = {
633 .minimum_version_id = 1,
634 .fields = (VMStateField[]) {
635 VMSTATE_UINT8(lock, M48t59State),
636 VMSTATE_UINT16(addr, M48t59State),
637 VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size),
638 VMSTATE_END_OF_LIST()
642 static void m48t59_reset_common(M48t59State *NVRAM)
646 if (NVRAM->alrm_timer != NULL)
647 timer_del(NVRAM->alrm_timer);
649 if (NVRAM->wd_timer != NULL)
650 timer_del(NVRAM->wd_timer);
653 static void m48t59_reset_isa(DeviceState *d)
655 M48txxISAState *isa = M48TXX_ISA(d);
656 M48t59State *NVRAM = &isa->state;
658 m48t59_reset_common(NVRAM);
661 static void m48t59_reset_sysbus(DeviceState *d)
663 M48txxSysBusState *sys = M48TXX_SYS_BUS(d);
664 M48t59State *NVRAM = &sys->state;
666 m48t59_reset_common(NVRAM);
669 static const MemoryRegionOps m48t59_io_ops = {
671 .write = NVRAM_writeb,
673 .min_access_size = 1,
674 .max_access_size = 1,
676 .endianness = DEVICE_LITTLE_ENDIAN,
679 /* Initialisation routine */
680 Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
681 uint32_t io_base, uint16_t size, int base_year,
688 for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
689 if (!m48txx_info[i].sysbus_name ||
690 m48txx_info[i].size != size ||
691 m48txx_info[i].model != model) {
695 dev = qdev_create(NULL, m48txx_info[i].sysbus_name);
696 qdev_prop_set_int32(dev, "base-year", base_year);
697 qdev_init_nofail(dev);
698 s = SYS_BUS_DEVICE(dev);
699 sysbus_connect_irq(s, 0, IRQ);
701 memory_region_add_subregion(get_system_io(), io_base,
702 sysbus_mmio_get_region(s, 1));
705 sysbus_mmio_map(s, 0, mem_base);
715 Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
716 int base_year, int model)
721 for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
722 if (!m48txx_info[i].isa_name ||
723 m48txx_info[i].size != size ||
724 m48txx_info[i].model != model) {
728 dev = DEVICE(isa_create(bus, m48txx_info[i].isa_name));
729 qdev_prop_set_uint32(dev, "iobase", io_base);
730 qdev_prop_set_int32(dev, "base-year", base_year);
731 qdev_init_nofail(dev);
739 static void m48t59_realize_common(M48t59State *s, Error **errp)
741 s->buffer = g_malloc0(s->size);
742 if (s->model == 59) {
743 s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);
744 s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
746 qemu_get_timedate(&s->alarm, 0);
748 vmstate_register(NULL, -1, &vmstate_m48t59, s);
751 static void m48t59_isa_realize(DeviceState *dev, Error **errp)
753 M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
754 ISADevice *isadev = ISA_DEVICE(dev);
755 M48txxISAState *d = M48TXX_ISA(dev);
756 M48t59State *s = &d->state;
758 s->model = u->info.model;
759 s->size = u->info.size;
760 isa_init_irq(isadev, &s->IRQ, 8);
761 m48t59_realize_common(s, errp);
762 memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
763 if (d->io_base != 0) {
764 isa_register_ioport(isadev, &d->io, d->io_base);
768 static int m48t59_init1(SysBusDevice *dev)
770 M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(dev);
771 M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
772 Object *o = OBJECT(dev);
773 M48t59State *s = &d->state;
776 s->model = u->info.model;
777 s->size = u->info.size;
778 sysbus_init_irq(dev, &s->IRQ);
780 memory_region_init_io(&s->iomem, o, &nvram_ops, s, "m48t59.nvram",
782 memory_region_init_io(&d->io, o, &m48t59_io_ops, s, "m48t59", 4);
783 sysbus_init_mmio(dev, &s->iomem);
784 sysbus_init_mmio(dev, &d->io);
785 m48t59_realize_common(s, &err);
794 static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
796 M48txxISAState *d = M48TXX_ISA(obj);
797 return m48t59_read(&d->state, addr);
800 static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
802 M48txxISAState *d = M48TXX_ISA(obj);
803 m48t59_write(&d->state, addr, val);
806 static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
808 M48txxISAState *d = M48TXX_ISA(obj);
809 m48t59_toggle_lock(&d->state, lock);
812 static Property m48t59_isa_properties[] = {
813 DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
814 DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
815 DEFINE_PROP_END_OF_LIST(),
818 static void m48txx_isa_class_init(ObjectClass *klass, void *data)
820 DeviceClass *dc = DEVICE_CLASS(klass);
821 NvramClass *nc = NVRAM_CLASS(klass);
823 dc->realize = m48t59_isa_realize;
824 dc->reset = m48t59_reset_isa;
825 dc->props = m48t59_isa_properties;
826 nc->read = m48txx_isa_read;
827 nc->write = m48txx_isa_write;
828 nc->toggle_lock = m48txx_isa_toggle_lock;
831 static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
833 M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
834 M48txxInfo *info = data;
839 static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr)
841 M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
842 return m48t59_read(&d->state, addr);
845 static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val)
847 M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
848 m48t59_write(&d->state, addr, val);
851 static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock)
853 M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
854 m48t59_toggle_lock(&d->state, lock);
857 static Property m48t59_sysbus_properties[] = {
858 DEFINE_PROP_INT32("base-year", M48txxSysBusState, state.base_year, 0),
859 DEFINE_PROP_END_OF_LIST(),
862 static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
864 DeviceClass *dc = DEVICE_CLASS(klass);
865 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
866 NvramClass *nc = NVRAM_CLASS(klass);
868 k->init = m48t59_init1;
869 dc->reset = m48t59_reset_sysbus;
870 dc->props = m48t59_sysbus_properties;
871 nc->read = m48txx_sysbus_read;
872 nc->write = m48txx_sysbus_write;
873 nc->toggle_lock = m48txx_sysbus_toggle_lock;
876 static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
878 M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass);
879 M48txxInfo *info = data;
884 static const TypeInfo nvram_info = {
886 .parent = TYPE_INTERFACE,
887 .class_size = sizeof(NvramClass),
890 static const TypeInfo m48txx_sysbus_type_info = {
891 .name = TYPE_M48TXX_SYS_BUS,
892 .parent = TYPE_SYS_BUS_DEVICE,
893 .instance_size = sizeof(M48txxSysBusState),
895 .class_init = m48txx_sysbus_class_init,
896 .interfaces = (InterfaceInfo[]) {
902 static const TypeInfo m48txx_isa_type_info = {
903 .name = TYPE_M48TXX_ISA,
904 .parent = TYPE_ISA_DEVICE,
905 .instance_size = sizeof(M48txxISAState),
907 .class_init = m48txx_isa_class_init,
908 .interfaces = (InterfaceInfo[]) {
914 static void m48t59_register_types(void)
916 TypeInfo sysbus_type_info = {
917 .parent = TYPE_M48TXX_SYS_BUS,
918 .class_size = sizeof(M48txxSysBusDeviceClass),
919 .class_init = m48txx_sysbus_concrete_class_init,
921 TypeInfo isa_type_info = {
922 .parent = TYPE_M48TXX_ISA,
923 .class_size = sizeof(M48txxISADeviceClass),
924 .class_init = m48txx_isa_concrete_class_init,
928 type_register_static(&nvram_info);
929 type_register_static(&m48txx_sysbus_type_info);
930 type_register_static(&m48txx_isa_type_info);
932 for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
933 if (m48txx_info[i].sysbus_name) {
934 sysbus_type_info.name = m48txx_info[i].sysbus_name;
935 sysbus_type_info.class_data = &m48txx_info[i];
936 type_register(&sysbus_type_info);
939 if (m48txx_info[i].isa_name) {
940 isa_type_info.name = m48txx_info[i].isa_name;
941 isa_type_info.class_data = &m48txx_info[i];
942 type_register(&isa_type_info);
947 type_init(m48t59_register_types)