2 * TI OMAP processor's Multichannel SPI emulation.
4 * Copyright (C) 2007-2009 Nokia Corporation
6 * Original code for OMAP2 by Andrzej Zaborowski <andrew@openedhand.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) any later version of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "qemu/osdep.h"
24 #include "hw/arm/omap.h"
26 /* Multichannel SPI */
39 struct omap_mcspi_ch_s {
42 uint32_t (*txrx)(void *opaque, uint32_t, int);
54 static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
56 qemu_set_irq(s->irq, s->irqst & s->irqen);
59 static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
61 qemu_set_irq(ch->txdrq,
62 (ch->control & 1) && /* EN */
63 (ch->config & (1 << 14)) && /* DMAW */
64 (ch->status & (1 << 1)) && /* TXS */
65 ((ch->config >> 12) & 3) != 1); /* TRM */
66 qemu_set_irq(ch->rxdrq,
67 (ch->control & 1) && /* EN */
68 (ch->config & (1 << 15)) && /* DMAW */
69 (ch->status & (1 << 0)) && /* RXS */
70 ((ch->config >> 12) & 3) != 2); /* TRM */
73 static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
75 struct omap_mcspi_ch_s *ch = s->ch + chnum;
77 if (!(ch->control & 1)) /* EN */
79 if ((ch->status & (1 << 0)) && /* RXS */
80 ((ch->config >> 12) & 3) != 2 && /* TRM */
81 !(ch->config & (1 << 19))) /* TURBO */
83 if ((ch->status & (1 << 1)) && /* TXS */
84 ((ch->config >> 12) & 3) != 1) /* TRM */
87 if (!(s->control & 1) || /* SINGLE */
88 (ch->config & (1 << 20))) { /* FORCE */
90 ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
91 1 + (0x1f & (ch->config >> 7)));
95 ch->status |= 1 << 2; /* EOT */
96 ch->status |= 1 << 1; /* TXS */
97 if (((ch->config >> 12) & 3) != 2) /* TRM */
98 ch->status |= 1 << 0; /* RXS */
101 if ((ch->status & (1 << 0)) && /* RXS */
102 ((ch->config >> 12) & 3) != 2 && /* TRM */
103 !(ch->config & (1 << 19))) /* TURBO */
104 s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */
105 if ((ch->status & (1 << 1)) && /* TXS */
106 ((ch->config >> 12) & 3) != 1) /* TRM */
107 s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */
108 omap_mcspi_interrupt_update(s);
109 omap_mcspi_dmarequest_update(ch);
112 void omap_mcspi_reset(struct omap_mcspi_s *s)
123 for (ch = 0; ch < 4; ch ++) {
124 s->ch[ch].config = 0x060000;
125 s->ch[ch].status = 2; /* TXS */
126 s->ch[ch].control = 0;
128 omap_mcspi_dmarequest_update(s->ch + ch);
131 omap_mcspi_interrupt_update(s);
134 static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
137 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
142 return omap_badwidth_read32(opaque, addr);
146 case 0x00: /* MCSPI_REVISION */
149 case 0x10: /* MCSPI_SYSCONFIG */
152 case 0x14: /* MCSPI_SYSSTATUS */
153 return 1; /* RESETDONE */
155 case 0x18: /* MCSPI_IRQSTATUS */
158 case 0x1c: /* MCSPI_IRQENABLE */
161 case 0x20: /* MCSPI_WAKEUPENABLE */
164 case 0x24: /* MCSPI_SYST */
167 case 0x28: /* MCSPI_MODULCTRL */
176 case 0x2c: /* MCSPI_CHCONF */
177 return s->ch[ch].config;
185 case 0x30: /* MCSPI_CHSTAT */
186 return s->ch[ch].status;
194 case 0x34: /* MCSPI_CHCTRL */
195 return s->ch[ch].control;
203 case 0x38: /* MCSPI_TX */
212 case 0x3c: /* MCSPI_RX */
213 s->ch[ch].status &= ~(1 << 0); /* RXS */
215 omap_mcspi_transfer_run(s, ch);
223 static void omap_mcspi_write(void *opaque, hwaddr addr,
224 uint64_t value, unsigned size)
226 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
230 omap_badwidth_write32(opaque, addr, value);
235 case 0x00: /* MCSPI_REVISION */
236 case 0x14: /* MCSPI_SYSSTATUS */
237 case 0x30: /* MCSPI_CHSTAT0 */
238 case 0x3c: /* MCSPI_RX0 */
239 case 0x44: /* MCSPI_CHSTAT1 */
240 case 0x50: /* MCSPI_RX1 */
241 case 0x58: /* MCSPI_CHSTAT2 */
242 case 0x64: /* MCSPI_RX2 */
243 case 0x6c: /* MCSPI_CHSTAT3 */
244 case 0x78: /* MCSPI_RX3 */
248 case 0x10: /* MCSPI_SYSCONFIG */
249 if (value & (1 << 1)) /* SOFTRESET */
251 s->sysconfig = value & 0x31d;
254 case 0x18: /* MCSPI_IRQSTATUS */
255 if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
257 omap_mcspi_interrupt_update(s);
261 case 0x1c: /* MCSPI_IRQENABLE */
262 s->irqen = value & 0x1777f;
263 omap_mcspi_interrupt_update(s);
266 case 0x20: /* MCSPI_WAKEUPENABLE */
270 case 0x24: /* MCSPI_SYST */
271 if (s->control & (1 << 3)) /* SYSTEM_TEST */
272 if (value & (1 << 11)) { /* SSB */
274 omap_mcspi_interrupt_update(s);
276 s->systest = value & 0xfff;
279 case 0x28: /* MCSPI_MODULCTRL */
280 if (value & (1 << 3)) /* SYSTEM_TEST */
281 if (s->systest & (1 << 11)) { /* SSB */
283 omap_mcspi_interrupt_update(s);
285 s->control = value & 0xf;
294 case 0x2c: /* MCSPI_CHCONF */
295 if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */
296 omap_mcspi_dmarequest_update(s->ch + ch);
297 if (((value >> 12) & 3) == 3) /* TRM */
298 fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
299 if (((value >> 7) & 0x1f) < 3) /* WL */
300 fprintf(stderr, "%s: invalid WL value (%" PRIx64 ")\n",
301 __FUNCTION__, (value >> 7) & 0x1f);
302 s->ch[ch].config = value & 0x7fffff;
311 case 0x34: /* MCSPI_CHCTRL */
312 if (value & ~s->ch[ch].control & 1) { /* EN */
313 s->ch[ch].control |= 1;
314 omap_mcspi_transfer_run(s, ch);
316 s->ch[ch].control = value & 1;
325 case 0x38: /* MCSPI_TX */
326 s->ch[ch].tx = value;
327 s->ch[ch].status &= ~(1 << 1); /* TXS */
328 omap_mcspi_transfer_run(s, ch);
337 static const MemoryRegionOps omap_mcspi_ops = {
338 .read = omap_mcspi_read,
339 .write = omap_mcspi_write,
340 .endianness = DEVICE_NATIVE_ENDIAN,
343 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
344 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
346 struct omap_mcspi_s *s = g_new0(struct omap_mcspi_s, 1);
347 struct omap_mcspi_ch_s *ch = s->ch;
358 memory_region_init_io(&s->iomem, NULL, &omap_mcspi_ops, s, "omap.mcspi",
359 omap_l4_region_size(ta, 0));
360 omap_l4_attach(ta, 0, &s->iomem);
365 void omap_mcspi_attach(struct omap_mcspi_s *s,
366 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
369 if (chipselect < 0 || chipselect >= s->chnum)
370 hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
372 s->ch[chipselect].txrx = txrx;
373 s->ch[chipselect].opaque = opaque;