2 * QEMU PPC PREP hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
26 #include "hw/timer/m48t59.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/block/fdc.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/isa/isa.h"
33 #include "hw/pci/pci.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/boards.h"
37 #include "qemu/error-report.h"
40 #include "hw/loader.h"
41 #include "hw/timer/mc146818rtc.h"
42 #include "hw/isa/pc87312.h"
43 #include "sysemu/block-backend.h"
44 #include "sysemu/arch_init.h"
45 #include "sysemu/qtest.h"
46 #include "exec/address-spaces.h"
49 #include "qemu/cutils.h"
51 /* SMP is not enabled, for now */
56 #define BIOS_SIZE (1024 * 1024)
57 #define BIOS_FILENAME "ppc_rom.bin"
58 #define KERNEL_LOAD_ADDR 0x01000000
59 #define INITRD_LOAD_ADDR 0x01800000
61 /* Constants for devices init */
62 static const int ide_iobase[2] = { 0x1f0, 0x170 };
63 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
64 static const int ide_irq[2] = { 13, 13 };
66 #define NE2000_NB_MAX 6
68 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
69 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
71 /* ISA IO ports bridge */
72 #define PPC_IO_BASE 0x80000000
74 /* PowerPC control and status registers */
80 /* Control and status */
85 /* General purpose registers */
98 /* Error diagnostic */
101 static void PPC_XCSR_writeb (void *opaque,
102 hwaddr addr, uint32_t value)
104 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
108 static void PPC_XCSR_writew (void *opaque,
109 hwaddr addr, uint32_t value)
111 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
115 static void PPC_XCSR_writel (void *opaque,
116 hwaddr addr, uint32_t value)
118 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
122 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
126 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
132 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
136 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
142 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
146 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
152 static const MemoryRegionOps PPC_XCSR_ops = {
154 .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
155 .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
157 .endianness = DEVICE_LITTLE_ENDIAN,
162 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
163 typedef struct sysctrl_t {
169 qemu_irq contiguous_map_irq;
174 STATE_HARDFILE = 0x01,
177 static sysctrl_t *sysctrl;
179 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
181 sysctrl_t *sysctrl = opaque;
183 trace_prep_io_800_writeb(addr - PPC_IO_BASE, val);
186 /* Special port 92 */
187 /* Check soft reset asked */
189 qemu_irq_raise(sysctrl->reset_irq);
191 qemu_irq_lower(sysctrl->reset_irq);
201 /* Motorola CPU configuration register : read-only */
204 /* Motorola base module feature register : read-only */
207 /* Motorola base module status register : read-only */
210 /* Hardfile light register */
212 sysctrl->state |= STATE_HARDFILE;
214 sysctrl->state &= ~STATE_HARDFILE;
217 /* Password protect 1 register */
218 if (sysctrl->nvram != NULL) {
219 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
220 (k->toggle_lock)(sysctrl->nvram, 1);
224 /* Password protect 2 register */
225 if (sysctrl->nvram != NULL) {
226 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
227 (k->toggle_lock)(sysctrl->nvram, 2);
231 /* L2 invalidate register */
232 // tlb_flush(first_cpu, 1);
235 /* system control register */
236 sysctrl->syscontrol = val & 0x0F;
239 /* I/O map type register */
240 sysctrl->contiguous_map = val & 0x01;
241 qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
244 printf("ERROR: unaffected IO port write: %04" PRIx32
245 " => %02" PRIx32"\n", addr, val);
250 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
252 sysctrl_t *sysctrl = opaque;
253 uint32_t retval = 0xFF;
257 /* Special port 92 */
258 retval = sysctrl->endian << 1;
261 /* Motorola CPU configuration register */
262 retval = 0xEF; /* MPC750 */
265 /* Motorola Base module feature register */
266 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
269 /* Motorola base module status register */
270 retval = 0xE0; /* Standard MPC750 */
273 /* Equipment present register:
275 * no upgrade processor
276 * no cards in PCI slots
282 /* Motorola base module extended feature register */
283 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
286 /* L2 invalidate: don't care */
293 /* system control register
294 * 7 - 6 / 1 - 0: L2 cache enable
296 retval = sysctrl->syscontrol;
300 retval = 0x03; /* no L2 cache */
303 /* I/O map type register */
304 retval = sysctrl->contiguous_map;
307 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
310 trace_prep_io_800_readb(addr - PPC_IO_BASE, retval);
316 #define NVRAM_SIZE 0x2000
318 static void ppc_prep_reset(void *opaque)
320 PowerPCCPU *cpu = opaque;
325 static const MemoryRegionPortio prep_portio_list[] = {
326 /* System control ports */
327 { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
329 .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
330 /* Special port to get debug messages from Open-Firmware */
331 { 0x0F00, 4, 1, .write = PPC_debug_write, },
332 PORTIO_END_OF_LIST(),
335 static PortioList prep_port_list;
337 /*****************************************************************************/
339 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
341 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
342 return (k->read)(nvram, addr);
345 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
347 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
348 (k->write)(nvram, addr, val);
351 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
353 nvram_write(nvram, addr, value);
356 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
358 return nvram_read(nvram, addr);
361 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
363 nvram_write(nvram, addr, value >> 8);
364 nvram_write(nvram, addr + 1, value & 0xFF);
367 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
371 tmp = nvram_read(nvram, addr) << 8;
372 tmp |= nvram_read(nvram, addr + 1);
377 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
379 nvram_write(nvram, addr, value >> 24);
380 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
381 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
382 nvram_write(nvram, addr + 3, value & 0xFF);
385 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
390 for (i = 0; i < max && str[i] != '\0'; i++) {
391 nvram_write(nvram, addr + i, str[i]);
393 nvram_write(nvram, addr + i, str[i]);
394 nvram_write(nvram, addr + max - 1, '\0');
397 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
400 uint16_t pd, pd1, pd2;
405 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
406 tmp ^= (pd1 << 3) | (pd1 << 8);
407 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
412 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
415 uint16_t crc = 0xFFFF;
420 for (i = 0; i != count; i++) {
421 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
424 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
430 #define CMDLINE_ADDR 0x017ff000
432 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
434 uint32_t RAM_size, int boot_device,
435 uint32_t kernel_image, uint32_t kernel_size,
437 uint32_t initrd_image, uint32_t initrd_size,
438 uint32_t NVRAM_image,
439 int width, int height, int depth)
443 /* Set parameters for Open Hack'Ware BIOS */
444 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
445 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
446 NVRAM_set_word(nvram, 0x14, NVRAM_size);
447 NVRAM_set_string(nvram, 0x20, arch, 16);
448 NVRAM_set_lword(nvram, 0x30, RAM_size);
449 NVRAM_set_byte(nvram, 0x34, boot_device);
450 NVRAM_set_lword(nvram, 0x38, kernel_image);
451 NVRAM_set_lword(nvram, 0x3C, kernel_size);
453 /* XXX: put the cmdline in NVRAM too ? */
454 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
456 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
457 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
459 NVRAM_set_lword(nvram, 0x40, 0);
460 NVRAM_set_lword(nvram, 0x44, 0);
462 NVRAM_set_lword(nvram, 0x48, initrd_image);
463 NVRAM_set_lword(nvram, 0x4C, initrd_size);
464 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
466 NVRAM_set_word(nvram, 0x54, width);
467 NVRAM_set_word(nvram, 0x56, height);
468 NVRAM_set_word(nvram, 0x58, depth);
469 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
470 NVRAM_set_word(nvram, 0xFC, crc);
475 /* PowerPC PREP hardware initialisation */
476 static void ppc_prep_init(MachineState *machine)
478 ram_addr_t ram_size = machine->ram_size;
479 const char *kernel_filename = machine->kernel_filename;
480 const char *kernel_cmdline = machine->kernel_cmdline;
481 const char *initrd_filename = machine->initrd_filename;
482 const char *boot_device = machine->boot_order;
483 MemoryRegion *sysmem = get_system_memory();
484 PowerPCCPU *cpu = NULL;
485 CPUPPCState *env = NULL;
488 MemoryRegion *xcsr = g_new(MemoryRegion, 1);
490 int linux_boot, i, nb_nics1;
491 MemoryRegion *ram = g_new(MemoryRegion, 1);
492 uint32_t kernel_base, initrd_base;
493 long kernel_size, initrd_size;
495 PCIHostState *pcihost;
501 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
503 sysctrl = g_malloc0(sizeof(sysctrl_t));
505 linux_boot = (kernel_filename != NULL);
508 if (machine->cpu_model == NULL)
509 machine->cpu_model = "602";
510 for (i = 0; i < smp_cpus; i++) {
511 cpu = cpu_ppc_init(machine->cpu_model);
513 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
518 if (env->flags & POWERPC_FLAG_RTC_CLK) {
519 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
520 cpu_ppc_tb_init(env, 7812500UL);
522 /* Set time-base frequency to 100 Mhz */
523 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
525 qemu_register_reset(ppc_prep_reset, cpu);
529 memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
530 memory_region_add_subregion(sysmem, 0, ram);
533 kernel_base = KERNEL_LOAD_ADDR;
534 /* now we can load the kernel */
535 kernel_size = load_image_targphys(kernel_filename, kernel_base,
536 ram_size - kernel_base);
537 if (kernel_size < 0) {
538 error_report("could not load kernel '%s'", kernel_filename);
542 if (initrd_filename) {
543 initrd_base = INITRD_LOAD_ADDR;
544 initrd_size = load_image_targphys(initrd_filename, initrd_base,
545 ram_size - initrd_base);
546 if (initrd_size < 0) {
547 error_report("could not load initial ram disk '%s'",
555 ppc_boot_device = 'm';
561 ppc_boot_device = '\0';
562 /* For now, OHW cannot boot from the network. */
563 for (i = 0; boot_device[i] != '\0'; i++) {
564 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
565 ppc_boot_device = boot_device[i];
569 if (ppc_boot_device == '\0') {
570 fprintf(stderr, "No valid boot device for Mac99 machine\n");
575 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
576 error_report("Only 6xx bus is supported on PREP machine");
580 dev = qdev_create(NULL, "raven-pcihost");
581 if (bios_name == NULL) {
582 bios_name = BIOS_FILENAME;
584 qdev_prop_set_string(dev, "bios-name", bios_name);
585 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
586 pcihost = PCI_HOST_BRIDGE(dev);
587 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
588 qdev_init_nofail(dev);
589 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
590 if (pci_bus == NULL) {
591 fprintf(stderr, "Couldn't create PCI host controller.\n");
594 sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
596 /* PCI -> ISA bridge */
597 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
598 cpu = POWERPC_CPU(first_cpu);
599 qdev_connect_gpio_out(&pci->qdev, 0,
600 cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
601 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
602 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
603 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
604 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
605 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
607 /* Super I/O (parallel + serial ports) */
608 isa = isa_create(isa_bus, TYPE_PC87312);
610 qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
611 qdev_init_nofail(dev);
613 /* init basic PC hardware */
614 pci_vga_init(pci_bus);
617 if (nb_nics1 > NE2000_NB_MAX)
618 nb_nics1 = NE2000_NB_MAX;
619 for(i = 0; i < nb_nics1; i++) {
620 if (nd_table[i].model == NULL) {
621 nd_table[i].model = g_strdup("ne2k_isa");
623 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
624 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
627 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
631 ide_drive_get(hd, ARRAY_SIZE(hd));
632 for(i = 0; i < MAX_IDE_BUS; i++) {
633 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
637 isa_create_simple(isa_bus, "i8042");
639 cpu = POWERPC_CPU(first_cpu);
640 sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
642 portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
643 portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
645 /* PowerPC control and status register group */
647 memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
648 memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
652 pci_create_simple(pci_bus, -1, "pci-ohci");
655 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
658 sysctrl->nvram = m48t59;
660 /* Initialise NVRAM */
661 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
663 kernel_base, kernel_size,
665 initrd_base, initrd_size,
666 /* XXX: need an option to load a NVRAM image */
668 graphic_width, graphic_height, graphic_depth);
671 static void prep_machine_init(MachineClass *mc)
673 mc->desc = "PowerPC PREP platform";
674 mc->init = ppc_prep_init;
675 mc->max_cpus = MAX_CPUS;
676 mc->default_boot_order = "cad";
679 DEFINE_MACHINE("prep", prep_machine_init)