2 * QEMU PowerPC 405 embedded processors emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/ppc/ppc.h"
26 #include "hw/boards.h"
28 #include "hw/char/serial.h"
29 #include "qemu/timer.h"
30 #include "sysemu/sysemu.h"
32 #include "exec/address-spaces.h"
37 //#define DEBUG_SERIAL
42 //#define DEBUG_CLOCKS
43 //#define DEBUG_CLOCKS_LL
45 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
48 CPUState *cs = CPU(ppc_env_get_cpu(env));
52 /* We put the bd structure at the top of memory */
53 if (bd->bi_memsize >= 0x01000000UL)
54 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
56 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
57 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
58 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
59 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
60 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
61 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
62 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
63 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
64 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
65 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
66 for (i = 0; i < 6; i++) {
67 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
69 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
70 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
71 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
72 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
73 for (i = 0; i < 4; i++) {
74 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
76 for (i = 0; i < 32; i++) {
77 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
79 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
80 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
81 for (i = 0; i < 6; i++) {
82 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
85 if (flags & 0x00000001) {
86 for (i = 0; i < 6; i++)
87 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
89 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
91 for (i = 0; i < 2; i++) {
92 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
99 /*****************************************************************************/
100 /* Shared peripherals */
102 /*****************************************************************************/
103 /* Peripheral local bus arbitrer */
110 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
111 struct ppc4xx_plb_t {
117 static uint32_t dcr_read_plb (void *opaque, int dcrn)
134 /* Avoid gcc warning */
142 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
149 /* We don't care about the actual parameters written as
150 * we don't manage any priorities on the bus
152 plb->acr = val & 0xF8000000;
164 static void ppc4xx_plb_reset (void *opaque)
169 plb->acr = 0x00000000;
170 plb->bear = 0x00000000;
171 plb->besr = 0x00000000;
174 static void ppc4xx_plb_init(CPUPPCState *env)
178 plb = g_malloc0(sizeof(ppc4xx_plb_t));
179 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
180 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
181 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
182 qemu_register_reset(ppc4xx_plb_reset, plb);
185 /*****************************************************************************/
186 /* PLB to OPB bridge */
193 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
194 struct ppc4xx_pob_t {
200 static uint32_t dcr_read_pob (void *opaque, int dcrn)
217 /* Avoid gcc warning */
225 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
245 static void ppc4xx_pob_reset (void *opaque)
251 pob->bear = 0x00000000;
252 pob->besr0 = 0x0000000;
253 pob->besr1 = 0x0000000;
256 static void ppc4xx_pob_init(CPUPPCState *env)
260 pob = g_malloc0(sizeof(ppc4xx_pob_t));
261 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
262 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
263 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
264 qemu_register_reset(ppc4xx_pob_reset, pob);
267 /*****************************************************************************/
269 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
270 struct ppc4xx_opba_t {
276 static uint32_t opba_readb (void *opaque, hwaddr addr)
282 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
300 static void opba_writeb (void *opaque,
301 hwaddr addr, uint32_t value)
306 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
312 opba->cr = value & 0xF8;
315 opba->pr = value & 0xFF;
322 static uint32_t opba_readw (void *opaque, hwaddr addr)
327 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
329 ret = opba_readb(opaque, addr) << 8;
330 ret |= opba_readb(opaque, addr + 1);
335 static void opba_writew (void *opaque,
336 hwaddr addr, uint32_t value)
339 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
342 opba_writeb(opaque, addr, value >> 8);
343 opba_writeb(opaque, addr + 1, value);
346 static uint32_t opba_readl (void *opaque, hwaddr addr)
351 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
353 ret = opba_readb(opaque, addr) << 24;
354 ret |= opba_readb(opaque, addr + 1) << 16;
359 static void opba_writel (void *opaque,
360 hwaddr addr, uint32_t value)
363 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
366 opba_writeb(opaque, addr, value >> 24);
367 opba_writeb(opaque, addr + 1, value >> 16);
370 static const MemoryRegionOps opba_ops = {
372 .read = { opba_readb, opba_readw, opba_readl, },
373 .write = { opba_writeb, opba_writew, opba_writel, },
375 .endianness = DEVICE_NATIVE_ENDIAN,
378 static void ppc4xx_opba_reset (void *opaque)
383 opba->cr = 0x00; /* No dynamic priorities - park disabled */
387 static void ppc4xx_opba_init(hwaddr base)
391 opba = g_malloc0(sizeof(ppc4xx_opba_t));
393 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
395 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
396 memory_region_add_subregion(get_system_memory(), base, &opba->io);
397 qemu_register_reset(ppc4xx_opba_reset, opba);
400 /*****************************************************************************/
401 /* Code decompression controller */
404 /*****************************************************************************/
405 /* Peripheral controller */
406 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
407 struct ppc4xx_ebc_t {
418 EBC0_CFGADDR = 0x012,
419 EBC0_CFGDATA = 0x013,
422 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
434 case 0x00: /* B0CR */
437 case 0x01: /* B1CR */
440 case 0x02: /* B2CR */
443 case 0x03: /* B3CR */
446 case 0x04: /* B4CR */
449 case 0x05: /* B5CR */
452 case 0x06: /* B6CR */
455 case 0x07: /* B7CR */
458 case 0x10: /* B0AP */
461 case 0x11: /* B1AP */
464 case 0x12: /* B2AP */
467 case 0x13: /* B3AP */
470 case 0x14: /* B4AP */
473 case 0x15: /* B5AP */
476 case 0x16: /* B6AP */
479 case 0x17: /* B7AP */
482 case 0x20: /* BEAR */
485 case 0x21: /* BESR0 */
488 case 0x22: /* BESR1 */
507 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
518 case 0x00: /* B0CR */
520 case 0x01: /* B1CR */
522 case 0x02: /* B2CR */
524 case 0x03: /* B3CR */
526 case 0x04: /* B4CR */
528 case 0x05: /* B5CR */
530 case 0x06: /* B6CR */
532 case 0x07: /* B7CR */
534 case 0x10: /* B0AP */
536 case 0x11: /* B1AP */
538 case 0x12: /* B2AP */
540 case 0x13: /* B3AP */
542 case 0x14: /* B4AP */
544 case 0x15: /* B5AP */
546 case 0x16: /* B6AP */
548 case 0x17: /* B7AP */
550 case 0x20: /* BEAR */
552 case 0x21: /* BESR0 */
554 case 0x22: /* BESR1 */
567 static void ebc_reset (void *opaque)
573 ebc->addr = 0x00000000;
574 ebc->bap[0] = 0x7F8FFE80;
575 ebc->bcr[0] = 0xFFE28000;
576 for (i = 0; i < 8; i++) {
577 ebc->bap[i] = 0x00000000;
578 ebc->bcr[i] = 0x00000000;
580 ebc->besr0 = 0x00000000;
581 ebc->besr1 = 0x00000000;
582 ebc->cfg = 0x80400000;
585 static void ppc405_ebc_init(CPUPPCState *env)
589 ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
590 qemu_register_reset(&ebc_reset, ebc);
591 ppc_dcr_register(env, EBC0_CFGADDR,
592 ebc, &dcr_read_ebc, &dcr_write_ebc);
593 ppc_dcr_register(env, EBC0_CFGDATA,
594 ebc, &dcr_read_ebc, &dcr_write_ebc);
597 /*****************************************************************************/
626 typedef struct ppc405_dma_t ppc405_dma_t;
627 struct ppc405_dma_t {
640 static uint32_t dcr_read_dma (void *opaque, int dcrn)
645 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
649 static void ppc405_dma_reset (void *opaque)
655 for (i = 0; i < 4; i++) {
656 dma->cr[i] = 0x00000000;
657 dma->ct[i] = 0x00000000;
658 dma->da[i] = 0x00000000;
659 dma->sa[i] = 0x00000000;
660 dma->sg[i] = 0x00000000;
662 dma->sr = 0x00000000;
663 dma->sgc = 0x00000000;
664 dma->slp = 0x7C000000;
665 dma->pol = 0x00000000;
668 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
672 dma = g_malloc0(sizeof(ppc405_dma_t));
673 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
674 qemu_register_reset(&ppc405_dma_reset, dma);
675 ppc_dcr_register(env, DMA0_CR0,
676 dma, &dcr_read_dma, &dcr_write_dma);
677 ppc_dcr_register(env, DMA0_CT0,
678 dma, &dcr_read_dma, &dcr_write_dma);
679 ppc_dcr_register(env, DMA0_DA0,
680 dma, &dcr_read_dma, &dcr_write_dma);
681 ppc_dcr_register(env, DMA0_SA0,
682 dma, &dcr_read_dma, &dcr_write_dma);
683 ppc_dcr_register(env, DMA0_SG0,
684 dma, &dcr_read_dma, &dcr_write_dma);
685 ppc_dcr_register(env, DMA0_CR1,
686 dma, &dcr_read_dma, &dcr_write_dma);
687 ppc_dcr_register(env, DMA0_CT1,
688 dma, &dcr_read_dma, &dcr_write_dma);
689 ppc_dcr_register(env, DMA0_DA1,
690 dma, &dcr_read_dma, &dcr_write_dma);
691 ppc_dcr_register(env, DMA0_SA1,
692 dma, &dcr_read_dma, &dcr_write_dma);
693 ppc_dcr_register(env, DMA0_SG1,
694 dma, &dcr_read_dma, &dcr_write_dma);
695 ppc_dcr_register(env, DMA0_CR2,
696 dma, &dcr_read_dma, &dcr_write_dma);
697 ppc_dcr_register(env, DMA0_CT2,
698 dma, &dcr_read_dma, &dcr_write_dma);
699 ppc_dcr_register(env, DMA0_DA2,
700 dma, &dcr_read_dma, &dcr_write_dma);
701 ppc_dcr_register(env, DMA0_SA2,
702 dma, &dcr_read_dma, &dcr_write_dma);
703 ppc_dcr_register(env, DMA0_SG2,
704 dma, &dcr_read_dma, &dcr_write_dma);
705 ppc_dcr_register(env, DMA0_CR3,
706 dma, &dcr_read_dma, &dcr_write_dma);
707 ppc_dcr_register(env, DMA0_CT3,
708 dma, &dcr_read_dma, &dcr_write_dma);
709 ppc_dcr_register(env, DMA0_DA3,
710 dma, &dcr_read_dma, &dcr_write_dma);
711 ppc_dcr_register(env, DMA0_SA3,
712 dma, &dcr_read_dma, &dcr_write_dma);
713 ppc_dcr_register(env, DMA0_SG3,
714 dma, &dcr_read_dma, &dcr_write_dma);
715 ppc_dcr_register(env, DMA0_SR,
716 dma, &dcr_read_dma, &dcr_write_dma);
717 ppc_dcr_register(env, DMA0_SGC,
718 dma, &dcr_read_dma, &dcr_write_dma);
719 ppc_dcr_register(env, DMA0_SLP,
720 dma, &dcr_read_dma, &dcr_write_dma);
721 ppc_dcr_register(env, DMA0_POL,
722 dma, &dcr_read_dma, &dcr_write_dma);
725 /*****************************************************************************/
727 typedef struct ppc405_gpio_t ppc405_gpio_t;
728 struct ppc405_gpio_t {
743 static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
746 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
752 static void ppc405_gpio_writeb (void *opaque,
753 hwaddr addr, uint32_t value)
756 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
761 static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
764 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
770 static void ppc405_gpio_writew (void *opaque,
771 hwaddr addr, uint32_t value)
774 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
779 static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
782 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
788 static void ppc405_gpio_writel (void *opaque,
789 hwaddr addr, uint32_t value)
792 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
797 static const MemoryRegionOps ppc405_gpio_ops = {
799 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
800 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
802 .endianness = DEVICE_NATIVE_ENDIAN,
805 static void ppc405_gpio_reset (void *opaque)
809 static void ppc405_gpio_init(hwaddr base)
813 gpio = g_malloc0(sizeof(ppc405_gpio_t));
815 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
817 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
818 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
819 qemu_register_reset(&ppc405_gpio_reset, gpio);
822 /*****************************************************************************/
826 OCM0_ISACNTL = 0x019,
828 OCM0_DSACNTL = 0x01B,
831 typedef struct ppc405_ocm_t ppc405_ocm_t;
832 struct ppc405_ocm_t {
834 MemoryRegion isarc_ram;
835 MemoryRegion dsarc_ram;
842 static void ocm_update_mappings (ppc405_ocm_t *ocm,
843 uint32_t isarc, uint32_t isacntl,
844 uint32_t dsarc, uint32_t dsacntl)
847 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
848 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
849 " (%08" PRIx32 " %08" PRIx32 ")\n",
850 isarc, isacntl, dsarc, dsacntl,
851 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
853 if (ocm->isarc != isarc ||
854 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
855 if (ocm->isacntl & 0x80000000) {
856 /* Unmap previously assigned memory region */
857 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
858 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
860 if (isacntl & 0x80000000) {
861 /* Map new instruction memory region */
863 printf("OCM map ISA %08" PRIx32 "\n", isarc);
865 memory_region_add_subregion(get_system_memory(), isarc,
869 if (ocm->dsarc != dsarc ||
870 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
871 if (ocm->dsacntl & 0x80000000) {
872 /* Beware not to unmap the region we just mapped */
873 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
874 /* Unmap previously assigned memory region */
876 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
878 memory_region_del_subregion(get_system_memory(),
882 if (dsacntl & 0x80000000) {
883 /* Beware not to remap the region we just mapped */
884 if (!(isacntl & 0x80000000) || dsarc != isarc) {
885 /* Map new data memory region */
887 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
889 memory_region_add_subregion(get_system_memory(), dsarc,
896 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
923 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
926 uint32_t isarc, dsarc, isacntl, dsacntl;
931 isacntl = ocm->isacntl;
932 dsacntl = ocm->dsacntl;
935 isarc = val & 0xFC000000;
938 isacntl = val & 0xC0000000;
941 isarc = val & 0xFC000000;
944 isacntl = val & 0xC0000000;
947 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
950 ocm->isacntl = isacntl;
951 ocm->dsacntl = dsacntl;
954 static void ocm_reset (void *opaque)
957 uint32_t isarc, dsarc, isacntl, dsacntl;
961 isacntl = 0x00000000;
963 dsacntl = 0x00000000;
964 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
967 ocm->isacntl = isacntl;
968 ocm->dsacntl = dsacntl;
971 static void ppc405_ocm_init(CPUPPCState *env)
975 ocm = g_malloc0(sizeof(ppc405_ocm_t));
976 /* XXX: Size is 4096 or 0x04000000 */
977 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096,
979 vmstate_register_ram_global(&ocm->isarc_ram);
980 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", &ocm->isarc_ram,
982 qemu_register_reset(&ocm_reset, ocm);
983 ppc_dcr_register(env, OCM0_ISARC,
984 ocm, &dcr_read_ocm, &dcr_write_ocm);
985 ppc_dcr_register(env, OCM0_ISACNTL,
986 ocm, &dcr_read_ocm, &dcr_write_ocm);
987 ppc_dcr_register(env, OCM0_DSARC,
988 ocm, &dcr_read_ocm, &dcr_write_ocm);
989 ppc_dcr_register(env, OCM0_DSACNTL,
990 ocm, &dcr_read_ocm, &dcr_write_ocm);
993 /*****************************************************************************/
995 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
996 struct ppc4xx_i2c_t {
1016 static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)
1022 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1027 // i2c_readbyte(&i2c->mdata);
1067 ret = i2c->xtcntlss;
1070 ret = i2c->directcntl;
1077 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1083 static void ppc4xx_i2c_writeb (void *opaque,
1084 hwaddr addr, uint32_t value)
1089 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1096 // i2c_sendbyte(&i2c->mdata);
1111 i2c->mdcntl = value & 0xDF;
1114 i2c->sts &= ~(value & 0x0A);
1117 i2c->extsts &= ~(value & 0x8F);
1126 i2c->clkdiv = value;
1129 i2c->intrmsk = value;
1132 i2c->xfrcnt = value & 0x77;
1135 i2c->xtcntlss = value;
1138 i2c->directcntl = value & 0x7;
1143 static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)
1148 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1150 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1151 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1156 static void ppc4xx_i2c_writew (void *opaque,
1157 hwaddr addr, uint32_t value)
1160 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1163 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1164 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1167 static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)
1172 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1174 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1175 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1176 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1177 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1182 static void ppc4xx_i2c_writel (void *opaque,
1183 hwaddr addr, uint32_t value)
1186 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1189 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1190 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1191 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1192 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1195 static const MemoryRegionOps i2c_ops = {
1197 .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
1198 .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
1200 .endianness = DEVICE_NATIVE_ENDIAN,
1203 static void ppc4xx_i2c_reset (void *opaque)
1216 i2c->directcntl = 0x0F;
1219 static void ppc405_i2c_init(hwaddr base, qemu_irq irq)
1223 i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
1226 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1228 memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, "i2c", 0x011);
1229 memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
1230 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1233 /*****************************************************************************/
1234 /* General purpose timers */
1235 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1236 struct ppc4xx_gpt_t {
1251 static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
1254 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1256 /* XXX: generate a bus fault */
1260 static void ppc4xx_gpt_writeb (void *opaque,
1261 hwaddr addr, uint32_t value)
1264 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1267 /* XXX: generate a bus fault */
1270 static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
1273 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1275 /* XXX: generate a bus fault */
1279 static void ppc4xx_gpt_writew (void *opaque,
1280 hwaddr addr, uint32_t value)
1283 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1286 /* XXX: generate a bus fault */
1289 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1295 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1300 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1306 for (i = 0; i < 5; i++) {
1307 if (gpt->oe & mask) {
1308 /* Output is enabled */
1309 if (ppc4xx_gpt_compare(gpt, i)) {
1310 /* Comparison is OK */
1311 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1313 /* Comparison is KO */
1314 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1321 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1327 for (i = 0; i < 5; i++) {
1328 if (gpt->is & gpt->im & mask)
1329 qemu_irq_raise(gpt->irqs[i]);
1331 qemu_irq_lower(gpt->irqs[i]);
1336 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1341 static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
1348 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1353 /* Time base counter */
1354 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset,
1355 gpt->tb_freq, get_ticks_per_sec());
1366 /* Interrupt mask */
1371 /* Interrupt status */
1375 /* Interrupt enable */
1380 idx = (addr - 0x80) >> 2;
1381 ret = gpt->comp[idx];
1385 idx = (addr - 0xC0) >> 2;
1386 ret = gpt->mask[idx];
1396 static void ppc4xx_gpt_writel (void *opaque,
1397 hwaddr addr, uint32_t value)
1403 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1409 /* Time base counter */
1410 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1411 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1412 ppc4xx_gpt_compute_timer(gpt);
1416 gpt->oe = value & 0xF8000000;
1417 ppc4xx_gpt_set_outputs(gpt);
1421 gpt->ol = value & 0xF8000000;
1422 ppc4xx_gpt_set_outputs(gpt);
1425 /* Interrupt mask */
1426 gpt->im = value & 0x0000F800;
1429 /* Interrupt status set */
1430 gpt->is |= value & 0x0000F800;
1431 ppc4xx_gpt_set_irqs(gpt);
1434 /* Interrupt status clear */
1435 gpt->is &= ~(value & 0x0000F800);
1436 ppc4xx_gpt_set_irqs(gpt);
1439 /* Interrupt enable */
1440 gpt->ie = value & 0x0000F800;
1441 ppc4xx_gpt_set_irqs(gpt);
1445 idx = (addr - 0x80) >> 2;
1446 gpt->comp[idx] = value & 0xF8000000;
1447 ppc4xx_gpt_compute_timer(gpt);
1451 idx = (addr - 0xC0) >> 2;
1452 gpt->mask[idx] = value & 0xF8000000;
1453 ppc4xx_gpt_compute_timer(gpt);
1458 static const MemoryRegionOps gpt_ops = {
1460 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
1461 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
1463 .endianness = DEVICE_NATIVE_ENDIAN,
1466 static void ppc4xx_gpt_cb (void *opaque)
1471 ppc4xx_gpt_set_irqs(gpt);
1472 ppc4xx_gpt_set_outputs(gpt);
1473 ppc4xx_gpt_compute_timer(gpt);
1476 static void ppc4xx_gpt_reset (void *opaque)
1482 timer_del(gpt->timer);
1483 gpt->oe = 0x00000000;
1484 gpt->ol = 0x00000000;
1485 gpt->im = 0x00000000;
1486 gpt->is = 0x00000000;
1487 gpt->ie = 0x00000000;
1488 for (i = 0; i < 5; i++) {
1489 gpt->comp[i] = 0x00000000;
1490 gpt->mask[i] = 0x00000000;
1494 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
1499 gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
1500 for (i = 0; i < 5; i++) {
1501 gpt->irqs[i] = irqs[i];
1503 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
1505 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1507 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
1508 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
1509 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1512 /*****************************************************************************/
1518 MAL0_TXCASR = 0x184,
1519 MAL0_TXCARR = 0x185,
1520 MAL0_TXEOBISR = 0x186,
1521 MAL0_TXDEIR = 0x187,
1522 MAL0_RXCASR = 0x190,
1523 MAL0_RXCARR = 0x191,
1524 MAL0_RXEOBISR = 0x192,
1525 MAL0_RXDEIR = 0x193,
1526 MAL0_TXCTP0R = 0x1A0,
1527 MAL0_TXCTP1R = 0x1A1,
1528 MAL0_TXCTP2R = 0x1A2,
1529 MAL0_TXCTP3R = 0x1A3,
1530 MAL0_RXCTP0R = 0x1C0,
1531 MAL0_RXCTP1R = 0x1C1,
1536 typedef struct ppc40x_mal_t ppc40x_mal_t;
1537 struct ppc40x_mal_t {
1555 static void ppc40x_mal_reset (void *opaque);
1557 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1580 ret = mal->txeobisr;
1592 ret = mal->rxeobisr;
1598 ret = mal->txctpr[0];
1601 ret = mal->txctpr[1];
1604 ret = mal->txctpr[2];
1607 ret = mal->txctpr[3];
1610 ret = mal->rxctpr[0];
1613 ret = mal->rxctpr[1];
1629 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1637 if (val & 0x80000000)
1638 ppc40x_mal_reset(mal);
1639 mal->cfg = val & 0x00FFC087;
1646 mal->ier = val & 0x0000001F;
1649 mal->txcasr = val & 0xF0000000;
1652 mal->txcarr = val & 0xF0000000;
1656 mal->txeobisr &= ~val;
1660 mal->txdeir &= ~val;
1663 mal->rxcasr = val & 0xC0000000;
1666 mal->rxcarr = val & 0xC0000000;
1670 mal->rxeobisr &= ~val;
1674 mal->rxdeir &= ~val;
1688 mal->txctpr[idx] = val;
1696 mal->rxctpr[idx] = val;
1700 goto update_rx_size;
1704 mal->rcbs[idx] = val & 0x000000FF;
1709 static void ppc40x_mal_reset (void *opaque)
1714 mal->cfg = 0x0007C000;
1715 mal->esr = 0x00000000;
1716 mal->ier = 0x00000000;
1717 mal->rxcasr = 0x00000000;
1718 mal->rxdeir = 0x00000000;
1719 mal->rxeobisr = 0x00000000;
1720 mal->txcasr = 0x00000000;
1721 mal->txdeir = 0x00000000;
1722 mal->txeobisr = 0x00000000;
1725 static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
1730 mal = g_malloc0(sizeof(ppc40x_mal_t));
1731 for (i = 0; i < 4; i++)
1732 mal->irqs[i] = irqs[i];
1733 qemu_register_reset(&ppc40x_mal_reset, mal);
1734 ppc_dcr_register(env, MAL0_CFG,
1735 mal, &dcr_read_mal, &dcr_write_mal);
1736 ppc_dcr_register(env, MAL0_ESR,
1737 mal, &dcr_read_mal, &dcr_write_mal);
1738 ppc_dcr_register(env, MAL0_IER,
1739 mal, &dcr_read_mal, &dcr_write_mal);
1740 ppc_dcr_register(env, MAL0_TXCASR,
1741 mal, &dcr_read_mal, &dcr_write_mal);
1742 ppc_dcr_register(env, MAL0_TXCARR,
1743 mal, &dcr_read_mal, &dcr_write_mal);
1744 ppc_dcr_register(env, MAL0_TXEOBISR,
1745 mal, &dcr_read_mal, &dcr_write_mal);
1746 ppc_dcr_register(env, MAL0_TXDEIR,
1747 mal, &dcr_read_mal, &dcr_write_mal);
1748 ppc_dcr_register(env, MAL0_RXCASR,
1749 mal, &dcr_read_mal, &dcr_write_mal);
1750 ppc_dcr_register(env, MAL0_RXCARR,
1751 mal, &dcr_read_mal, &dcr_write_mal);
1752 ppc_dcr_register(env, MAL0_RXEOBISR,
1753 mal, &dcr_read_mal, &dcr_write_mal);
1754 ppc_dcr_register(env, MAL0_RXDEIR,
1755 mal, &dcr_read_mal, &dcr_write_mal);
1756 ppc_dcr_register(env, MAL0_TXCTP0R,
1757 mal, &dcr_read_mal, &dcr_write_mal);
1758 ppc_dcr_register(env, MAL0_TXCTP1R,
1759 mal, &dcr_read_mal, &dcr_write_mal);
1760 ppc_dcr_register(env, MAL0_TXCTP2R,
1761 mal, &dcr_read_mal, &dcr_write_mal);
1762 ppc_dcr_register(env, MAL0_TXCTP3R,
1763 mal, &dcr_read_mal, &dcr_write_mal);
1764 ppc_dcr_register(env, MAL0_RXCTP0R,
1765 mal, &dcr_read_mal, &dcr_write_mal);
1766 ppc_dcr_register(env, MAL0_RXCTP1R,
1767 mal, &dcr_read_mal, &dcr_write_mal);
1768 ppc_dcr_register(env, MAL0_RCBS0,
1769 mal, &dcr_read_mal, &dcr_write_mal);
1770 ppc_dcr_register(env, MAL0_RCBS1,
1771 mal, &dcr_read_mal, &dcr_write_mal);
1774 /*****************************************************************************/
1776 void ppc40x_core_reset(PowerPCCPU *cpu)
1778 CPUPPCState *env = &cpu->env;
1781 printf("Reset PowerPC core\n");
1782 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1783 dbsr = env->spr[SPR_40x_DBSR];
1784 dbsr &= ~0x00000300;
1786 env->spr[SPR_40x_DBSR] = dbsr;
1789 void ppc40x_chip_reset(PowerPCCPU *cpu)
1791 CPUPPCState *env = &cpu->env;
1794 printf("Reset PowerPC chip\n");
1795 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1796 /* XXX: TODO reset all internal peripherals */
1797 dbsr = env->spr[SPR_40x_DBSR];
1798 dbsr &= ~0x00000300;
1800 env->spr[SPR_40x_DBSR] = dbsr;
1803 void ppc40x_system_reset(PowerPCCPU *cpu)
1805 printf("Reset PowerPC system\n");
1806 qemu_system_reset_request();
1809 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
1811 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1813 switch ((val >> 28) & 0x3) {
1819 ppc40x_core_reset(cpu);
1823 ppc40x_chip_reset(cpu);
1827 ppc40x_system_reset(cpu);
1832 /*****************************************************************************/
1835 PPC405CR_CPC0_PLLMR = 0x0B0,
1836 PPC405CR_CPC0_CR0 = 0x0B1,
1837 PPC405CR_CPC0_CR1 = 0x0B2,
1838 PPC405CR_CPC0_PSR = 0x0B4,
1839 PPC405CR_CPC0_JTAGID = 0x0B5,
1840 PPC405CR_CPC0_ER = 0x0B9,
1841 PPC405CR_CPC0_FR = 0x0BA,
1842 PPC405CR_CPC0_SR = 0x0BB,
1846 PPC405CR_CPU_CLK = 0,
1847 PPC405CR_TMR_CLK = 1,
1848 PPC405CR_PLB_CLK = 2,
1849 PPC405CR_SDRAM_CLK = 3,
1850 PPC405CR_OPB_CLK = 4,
1851 PPC405CR_EXT_CLK = 5,
1852 PPC405CR_UART_CLK = 6,
1853 PPC405CR_CLK_NB = 7,
1856 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1857 struct ppc405cr_cpc_t {
1858 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1869 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1871 uint64_t VCO_out, PLL_out;
1872 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1875 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1876 if (cpc->pllmr & 0x80000000) {
1877 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1878 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1880 VCO_out = cpc->sysclk * M;
1881 if (VCO_out < 400000000 || VCO_out > 800000000) {
1882 /* PLL cannot lock */
1883 cpc->pllmr &= ~0x80000000;
1886 PLL_out = VCO_out / D2;
1891 PLL_out = cpc->sysclk * M;
1894 if (cpc->cr1 & 0x00800000)
1895 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1898 PLB_clk = CPU_clk / D0;
1899 SDRAM_clk = PLB_clk;
1900 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1901 OPB_clk = PLB_clk / D0;
1902 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1903 EXT_clk = PLB_clk / D0;
1904 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1905 UART_clk = CPU_clk / D0;
1906 /* Setup CPU clocks */
1907 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1908 /* Setup time-base clock */
1909 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1910 /* Setup PLB clock */
1911 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1912 /* Setup SDRAM clock */
1913 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1914 /* Setup OPB clock */
1915 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1916 /* Setup external clock */
1917 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1918 /* Setup UART clock */
1919 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1922 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1924 ppc405cr_cpc_t *cpc;
1929 case PPC405CR_CPC0_PLLMR:
1932 case PPC405CR_CPC0_CR0:
1935 case PPC405CR_CPC0_CR1:
1938 case PPC405CR_CPC0_PSR:
1941 case PPC405CR_CPC0_JTAGID:
1944 case PPC405CR_CPC0_ER:
1947 case PPC405CR_CPC0_FR:
1950 case PPC405CR_CPC0_SR:
1951 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1954 /* Avoid gcc warning */
1962 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1964 ppc405cr_cpc_t *cpc;
1968 case PPC405CR_CPC0_PLLMR:
1969 cpc->pllmr = val & 0xFFF77C3F;
1971 case PPC405CR_CPC0_CR0:
1972 cpc->cr0 = val & 0x0FFFFFFE;
1974 case PPC405CR_CPC0_CR1:
1975 cpc->cr1 = val & 0x00800000;
1977 case PPC405CR_CPC0_PSR:
1980 case PPC405CR_CPC0_JTAGID:
1983 case PPC405CR_CPC0_ER:
1984 cpc->er = val & 0xBFFC0000;
1986 case PPC405CR_CPC0_FR:
1987 cpc->fr = val & 0xBFFC0000;
1989 case PPC405CR_CPC0_SR:
1995 static void ppc405cr_cpc_reset (void *opaque)
1997 ppc405cr_cpc_t *cpc;
2001 /* Compute PLLMR value from PSR settings */
2002 cpc->pllmr = 0x80000000;
2004 switch ((cpc->psr >> 30) & 3) {
2007 cpc->pllmr &= ~0x80000000;
2011 cpc->pllmr |= 5 << 16;
2015 cpc->pllmr |= 4 << 16;
2019 cpc->pllmr |= 2 << 16;
2023 D = (cpc->psr >> 28) & 3;
2024 cpc->pllmr |= (D + 1) << 20;
2026 D = (cpc->psr >> 25) & 7;
2041 D = (cpc->psr >> 23) & 3;
2042 cpc->pllmr |= D << 26;
2044 D = (cpc->psr >> 21) & 3;
2045 cpc->pllmr |= D << 10;
2047 D = (cpc->psr >> 17) & 3;
2048 cpc->pllmr |= D << 24;
2049 cpc->cr0 = 0x0000003C;
2050 cpc->cr1 = 0x2B0D8800;
2051 cpc->er = 0x00000000;
2052 cpc->fr = 0x00000000;
2053 ppc405cr_clk_setup(cpc);
2056 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2060 /* XXX: this should be read from IO pins */
2061 cpc->psr = 0x00000000; /* 8 bits ROM */
2063 D = 0x2; /* Divide by 4 */
2064 cpc->psr |= D << 30;
2066 D = 0x1; /* Divide by 2 */
2067 cpc->psr |= D << 28;
2069 D = 0x1; /* Divide by 2 */
2070 cpc->psr |= D << 23;
2072 D = 0x5; /* M = 16 */
2073 cpc->psr |= D << 25;
2075 D = 0x1; /* Divide by 2 */
2076 cpc->psr |= D << 21;
2078 D = 0x2; /* Divide by 4 */
2079 cpc->psr |= D << 17;
2082 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
2085 ppc405cr_cpc_t *cpc;
2087 cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
2088 memcpy(cpc->clk_setup, clk_setup,
2089 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2090 cpc->sysclk = sysclk;
2091 cpc->jtagid = 0x42051049;
2092 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2093 &dcr_read_crcpc, &dcr_write_crcpc);
2094 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2095 &dcr_read_crcpc, &dcr_write_crcpc);
2096 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2097 &dcr_read_crcpc, &dcr_write_crcpc);
2098 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2099 &dcr_read_crcpc, &dcr_write_crcpc);
2100 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2101 &dcr_read_crcpc, &dcr_write_crcpc);
2102 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2103 &dcr_read_crcpc, &dcr_write_crcpc);
2104 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2105 &dcr_read_crcpc, &dcr_write_crcpc);
2106 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2107 &dcr_read_crcpc, &dcr_write_crcpc);
2108 ppc405cr_clk_init(cpc);
2109 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2112 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
2113 MemoryRegion ram_memories[4],
2114 hwaddr ram_bases[4],
2115 hwaddr ram_sizes[4],
2116 uint32_t sysclk, qemu_irq **picp,
2119 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2120 qemu_irq dma_irqs[4];
2123 qemu_irq *pic, *irqs;
2125 memset(clk_setup, 0, sizeof(clk_setup));
2126 cpu = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2127 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2129 /* Memory mapped devices registers */
2131 ppc4xx_plb_init(env);
2132 /* PLB to OPB bridge */
2133 ppc4xx_pob_init(env);
2135 ppc4xx_opba_init(0xef600600);
2136 /* Universal interrupt controller */
2137 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2138 irqs[PPCUIC_OUTPUT_INT] =
2139 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2140 irqs[PPCUIC_OUTPUT_CINT] =
2141 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2142 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2144 /* SDRAM controller */
2145 ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
2146 ram_bases, ram_sizes, do_init);
2147 /* External bus controller */
2148 ppc405_ebc_init(env);
2149 /* DMA controller */
2150 dma_irqs[0] = pic[26];
2151 dma_irqs[1] = pic[25];
2152 dma_irqs[2] = pic[24];
2153 dma_irqs[3] = pic[23];
2154 ppc405_dma_init(env, dma_irqs);
2156 if (serial_hds[0] != NULL) {
2157 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2158 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2161 if (serial_hds[1] != NULL) {
2162 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2163 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2166 /* IIC controller */
2167 ppc405_i2c_init(0xef600500, pic[2]);
2169 ppc405_gpio_init(0xef600700);
2171 ppc405cr_cpc_init(env, clk_setup, sysclk);
2176 /*****************************************************************************/
2180 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2181 PPC405EP_CPC0_BOOT = 0x0F1,
2182 PPC405EP_CPC0_EPCTL = 0x0F3,
2183 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2184 PPC405EP_CPC0_UCR = 0x0F5,
2185 PPC405EP_CPC0_SRR = 0x0F6,
2186 PPC405EP_CPC0_JTAGID = 0x0F7,
2187 PPC405EP_CPC0_PCI = 0x0F9,
2189 PPC405EP_CPC0_ER = xxx,
2190 PPC405EP_CPC0_FR = xxx,
2191 PPC405EP_CPC0_SR = xxx,
2196 PPC405EP_CPU_CLK = 0,
2197 PPC405EP_PLB_CLK = 1,
2198 PPC405EP_OPB_CLK = 2,
2199 PPC405EP_EBC_CLK = 3,
2200 PPC405EP_MAL_CLK = 4,
2201 PPC405EP_PCI_CLK = 5,
2202 PPC405EP_UART0_CLK = 6,
2203 PPC405EP_UART1_CLK = 7,
2204 PPC405EP_CLK_NB = 8,
2207 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2208 struct ppc405ep_cpc_t {
2210 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2218 /* Clock and power management */
2224 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2226 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2227 uint32_t UART0_clk, UART1_clk;
2228 uint64_t VCO_out, PLL_out;
2232 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2233 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2234 #ifdef DEBUG_CLOCKS_LL
2235 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2237 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2238 #ifdef DEBUG_CLOCKS_LL
2239 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2241 VCO_out = cpc->sysclk * M * D;
2242 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2243 /* Error - unlock the PLL */
2244 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2246 cpc->pllmr[1] &= ~0x80000000;
2250 PLL_out = VCO_out / D;
2251 /* Pretend the PLL is locked */
2252 cpc->boot |= 0x00000001;
2257 PLL_out = cpc->sysclk;
2258 if (cpc->pllmr[1] & 0x40000000) {
2259 /* Pretend the PLL is not locked */
2260 cpc->boot &= ~0x00000001;
2263 /* Now, compute all other clocks */
2264 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2265 #ifdef DEBUG_CLOCKS_LL
2266 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2268 CPU_clk = PLL_out / D;
2269 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2270 #ifdef DEBUG_CLOCKS_LL
2271 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2273 PLB_clk = CPU_clk / D;
2274 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2275 #ifdef DEBUG_CLOCKS_LL
2276 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2278 OPB_clk = PLB_clk / D;
2279 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2280 #ifdef DEBUG_CLOCKS_LL
2281 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2283 EBC_clk = PLB_clk / D;
2284 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2285 #ifdef DEBUG_CLOCKS_LL
2286 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2288 MAL_clk = PLB_clk / D;
2289 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2290 #ifdef DEBUG_CLOCKS_LL
2291 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2293 PCI_clk = PLB_clk / D;
2294 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2295 #ifdef DEBUG_CLOCKS_LL
2296 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2298 UART0_clk = PLL_out / D;
2299 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2300 #ifdef DEBUG_CLOCKS_LL
2301 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2303 UART1_clk = PLL_out / D;
2305 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2306 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2307 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2308 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2309 " UART1 %" PRIu32 "\n",
2310 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2311 UART0_clk, UART1_clk);
2313 /* Setup CPU clocks */
2314 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2315 /* Setup PLB clock */
2316 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2317 /* Setup OPB clock */
2318 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2319 /* Setup external clock */
2320 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2321 /* Setup MAL clock */
2322 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2323 /* Setup PCI clock */
2324 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2325 /* Setup UART0 clock */
2326 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2327 /* Setup UART1 clock */
2328 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2331 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2333 ppc405ep_cpc_t *cpc;
2338 case PPC405EP_CPC0_BOOT:
2341 case PPC405EP_CPC0_EPCTL:
2344 case PPC405EP_CPC0_PLLMR0:
2345 ret = cpc->pllmr[0];
2347 case PPC405EP_CPC0_PLLMR1:
2348 ret = cpc->pllmr[1];
2350 case PPC405EP_CPC0_UCR:
2353 case PPC405EP_CPC0_SRR:
2356 case PPC405EP_CPC0_JTAGID:
2359 case PPC405EP_CPC0_PCI:
2363 /* Avoid gcc warning */
2371 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2373 ppc405ep_cpc_t *cpc;
2377 case PPC405EP_CPC0_BOOT:
2378 /* Read-only register */
2380 case PPC405EP_CPC0_EPCTL:
2381 /* Don't care for now */
2382 cpc->epctl = val & 0xC00000F3;
2384 case PPC405EP_CPC0_PLLMR0:
2385 cpc->pllmr[0] = val & 0x00633333;
2386 ppc405ep_compute_clocks(cpc);
2388 case PPC405EP_CPC0_PLLMR1:
2389 cpc->pllmr[1] = val & 0xC0F73FFF;
2390 ppc405ep_compute_clocks(cpc);
2392 case PPC405EP_CPC0_UCR:
2393 /* UART control - don't care for now */
2394 cpc->ucr = val & 0x003F7F7F;
2396 case PPC405EP_CPC0_SRR:
2399 case PPC405EP_CPC0_JTAGID:
2402 case PPC405EP_CPC0_PCI:
2408 static void ppc405ep_cpc_reset (void *opaque)
2410 ppc405ep_cpc_t *cpc = opaque;
2412 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2413 cpc->epctl = 0x00000000;
2414 cpc->pllmr[0] = 0x00011010;
2415 cpc->pllmr[1] = 0x40000000;
2416 cpc->ucr = 0x00000000;
2417 cpc->srr = 0x00040000;
2418 cpc->pci = 0x00000000;
2419 cpc->er = 0x00000000;
2420 cpc->fr = 0x00000000;
2421 cpc->sr = 0x00000000;
2422 ppc405ep_compute_clocks(cpc);
2425 /* XXX: sysclk should be between 25 and 100 MHz */
2426 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
2429 ppc405ep_cpc_t *cpc;
2431 cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
2432 memcpy(cpc->clk_setup, clk_setup,
2433 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2434 cpc->jtagid = 0x20267049;
2435 cpc->sysclk = sysclk;
2436 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2437 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2438 &dcr_read_epcpc, &dcr_write_epcpc);
2439 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2440 &dcr_read_epcpc, &dcr_write_epcpc);
2441 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2442 &dcr_read_epcpc, &dcr_write_epcpc);
2443 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2444 &dcr_read_epcpc, &dcr_write_epcpc);
2445 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2446 &dcr_read_epcpc, &dcr_write_epcpc);
2447 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2448 &dcr_read_epcpc, &dcr_write_epcpc);
2449 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2450 &dcr_read_epcpc, &dcr_write_epcpc);
2451 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2452 &dcr_read_epcpc, &dcr_write_epcpc);
2454 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2455 &dcr_read_epcpc, &dcr_write_epcpc);
2456 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2457 &dcr_read_epcpc, &dcr_write_epcpc);
2458 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2459 &dcr_read_epcpc, &dcr_write_epcpc);
2463 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
2464 MemoryRegion ram_memories[2],
2465 hwaddr ram_bases[2],
2466 hwaddr ram_sizes[2],
2467 uint32_t sysclk, qemu_irq **picp,
2470 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2471 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2474 qemu_irq *pic, *irqs;
2476 memset(clk_setup, 0, sizeof(clk_setup));
2478 cpu = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2479 &tlb_clk_setup, sysclk);
2481 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2482 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2483 /* Internal devices init */
2484 /* Memory mapped devices registers */
2486 ppc4xx_plb_init(env);
2487 /* PLB to OPB bridge */
2488 ppc4xx_pob_init(env);
2490 ppc4xx_opba_init(0xef600600);
2491 /* Initialize timers */
2492 ppc_booke_timers_init(cpu, sysclk, 0);
2493 /* Universal interrupt controller */
2494 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2495 irqs[PPCUIC_OUTPUT_INT] =
2496 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2497 irqs[PPCUIC_OUTPUT_CINT] =
2498 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2499 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2501 /* SDRAM controller */
2502 /* XXX 405EP has no ECC interrupt */
2503 ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
2504 ram_bases, ram_sizes, do_init);
2505 /* External bus controller */
2506 ppc405_ebc_init(env);
2507 /* DMA controller */
2508 dma_irqs[0] = pic[5];
2509 dma_irqs[1] = pic[6];
2510 dma_irqs[2] = pic[7];
2511 dma_irqs[3] = pic[8];
2512 ppc405_dma_init(env, dma_irqs);
2513 /* IIC controller */
2514 ppc405_i2c_init(0xef600500, pic[2]);
2516 ppc405_gpio_init(0xef600700);
2518 if (serial_hds[0] != NULL) {
2519 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2520 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2523 if (serial_hds[1] != NULL) {
2524 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2525 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2529 ppc405_ocm_init(env);
2531 gpt_irqs[0] = pic[19];
2532 gpt_irqs[1] = pic[20];
2533 gpt_irqs[2] = pic[21];
2534 gpt_irqs[3] = pic[22];
2535 gpt_irqs[4] = pic[23];
2536 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2538 /* Uses pic[3], pic[16], pic[18] */
2540 mal_irqs[0] = pic[11];
2541 mal_irqs[1] = pic[12];
2542 mal_irqs[2] = pic[13];
2543 mal_irqs[3] = pic[14];
2544 ppc405_mal_init(env, mal_irqs);
2546 /* Uses pic[9], pic[15], pic[17] */
2548 ppc405ep_cpc_init(env, clk_setup, sysclk);