4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2011-2013 Andreas Färber
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "qapi/error.h"
29 #include "hw/pci/pci.h"
30 #include "hw/pci/pci_bus.h"
31 #include "hw/pci/pci_host.h"
32 #include "hw/i386/pc.h"
33 #include "hw/loader.h"
34 #include "exec/address-spaces.h"
37 #define TYPE_RAVEN_PCI_DEVICE "raven"
38 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
40 #define RAVEN_PCI_DEVICE(obj) \
41 OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
43 typedef struct RavenPCIState {
51 #define RAVEN_PCI_HOST_BRIDGE(obj) \
52 OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
54 typedef struct PRePPCIState {
55 PCIHostState parent_obj;
57 qemu_irq irq[PCI_NUM_PINS];
59 AddressSpace pci_io_as;
61 MemoryRegion pci_io_non_contiguous;
62 MemoryRegion pci_memory;
63 MemoryRegion pci_intack;
65 MemoryRegion bm_ram_alias;
66 MemoryRegion bm_pci_memory_alias;
68 RavenPCIState pci_dev;
73 #define BIOS_SIZE (1024 * 1024)
75 static inline uint32_t raven_pci_io_config(hwaddr addr)
79 for (i = 0; i < 11; i++) {
80 if ((addr & (1 << (11 + i))) != 0) {
84 return (addr & 0x7ff) | (i << 11);
87 static void raven_pci_io_write(void *opaque, hwaddr addr,
88 uint64_t val, unsigned int size)
90 PREPPCIState *s = opaque;
91 PCIHostState *phb = PCI_HOST_BRIDGE(s);
92 pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
95 static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
98 PREPPCIState *s = opaque;
99 PCIHostState *phb = PCI_HOST_BRIDGE(s);
100 return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
103 static const MemoryRegionOps raven_pci_io_ops = {
104 .read = raven_pci_io_read,
105 .write = raven_pci_io_write,
106 .endianness = DEVICE_LITTLE_ENDIAN,
109 static uint64_t raven_intack_read(void *opaque, hwaddr addr,
112 return pic_read_irq(isa_pic);
115 static const MemoryRegionOps raven_intack_ops = {
116 .read = raven_intack_read,
118 .max_access_size = 1,
122 static inline hwaddr raven_io_address(PREPPCIState *s,
125 if (s->contiguous_map == 0) {
126 /* 64 KB contiguous space for IOs */
129 /* 8 MB non-contiguous space for IOs */
130 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
133 /* FIXME: handle endianness switch */
138 static uint64_t raven_io_read(void *opaque, hwaddr addr,
141 PREPPCIState *s = opaque;
144 addr = raven_io_address(s, addr);
145 address_space_read(&s->pci_io_as, addr + 0x80000000,
146 MEMTXATTRS_UNSPECIFIED, buf, size);
150 } else if (size == 2) {
151 return lduw_le_p(buf);
152 } else if (size == 4) {
153 return ldl_le_p(buf);
155 g_assert_not_reached();
159 static void raven_io_write(void *opaque, hwaddr addr,
160 uint64_t val, unsigned int size)
162 PREPPCIState *s = opaque;
165 addr = raven_io_address(s, addr);
169 } else if (size == 2) {
171 } else if (size == 4) {
174 g_assert_not_reached();
177 address_space_write(&s->pci_io_as, addr + 0x80000000,
178 MEMTXATTRS_UNSPECIFIED, buf, size);
181 static const MemoryRegionOps raven_io_ops = {
182 .read = raven_io_read,
183 .write = raven_io_write,
184 .endianness = DEVICE_LITTLE_ENDIAN,
185 .impl.max_access_size = 4,
186 .valid.unaligned = true,
189 static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
191 return (irq_num + (pci_dev->devfn >> 3)) & 1;
194 static void raven_set_irq(void *opaque, int irq_num, int level)
196 qemu_irq *pic = opaque;
198 qemu_set_irq(pic[irq_num] , level);
201 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
204 PREPPCIState *s = opaque;
209 static void raven_change_gpio(void *opaque, int n, int level)
211 PREPPCIState *s = opaque;
213 s->contiguous_map = level;
216 static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
218 SysBusDevice *dev = SYS_BUS_DEVICE(d);
219 PCIHostState *h = PCI_HOST_BRIDGE(dev);
220 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
221 MemoryRegion *address_space_mem = get_system_memory();
224 for (i = 0; i < PCI_NUM_PINS; i++) {
225 sysbus_init_irq(dev, &s->irq[i]);
228 qdev_init_gpio_in(d, raven_change_gpio, 1);
230 pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s->irq,
233 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
235 memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
237 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
239 memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
241 memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
242 "pciio", 0x00400000);
243 memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
245 memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
247 memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
249 /* TODO Remove once realize propagates to child devices. */
250 object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
253 static void raven_pcihost_initfn(Object *obj)
255 PCIHostState *h = PCI_HOST_BRIDGE(obj);
256 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
257 MemoryRegion *address_space_mem = get_system_memory();
258 DeviceState *pci_dev;
260 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
261 memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
262 "pci-io-non-contiguous", 0x00800000);
263 memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
264 address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
266 /* CPU address space */
267 memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
268 memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
269 &s->pci_io_non_contiguous, 1);
270 memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
271 pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
272 &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
274 /* Bus master address space */
275 memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX);
276 memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
278 memory_region_size(&s->pci_memory));
279 memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
280 get_system_memory(), 0, 0x80000000);
281 memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias);
282 memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
283 address_space_init(&s->bm_as, &s->bm, "raven-bm");
284 pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
286 h->bus = &s->pci_bus;
288 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
289 pci_dev = DEVICE(&s->pci_dev);
290 qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
291 object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
293 qdev_prop_set_bit(pci_dev, "multifunction", false);
296 static void raven_realize(PCIDevice *d, Error **errp)
298 RavenPCIState *s = RAVEN_PCI_DEVICE(d);
302 d->config[0x0C] = 0x08; // cache_line_size
303 d->config[0x0D] = 0x10; // latency_timer
304 d->config[0x34] = 0x00; // capabilities_pointer
306 memory_region_init_ram(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
308 memory_region_set_readonly(&s->bios, true);
309 memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
311 vmstate_register_ram_global(&s->bios);
313 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
315 if (s->elf_machine != EM_NONE) {
316 bios_size = load_elf(filename, NULL, NULL, NULL,
317 NULL, NULL, 1, s->elf_machine, 0, 0);
320 bios_size = get_image_size(filename);
321 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
323 bios_size = (bios_size + 0xfff) & ~0xfff;
324 bios_addr = (uint32_t)(-BIOS_SIZE);
325 bios_size = load_image_targphys(filename, bios_addr,
330 if (bios_size < 0 || bios_size > BIOS_SIZE) {
331 /* FIXME should error_setg() */
332 hw_error("qemu: could not load bios image '%s'\n", s->bios_name);
338 static const VMStateDescription vmstate_raven = {
341 .minimum_version_id = 0,
342 .fields = (VMStateField[]) {
343 VMSTATE_PCI_DEVICE(dev, RavenPCIState),
344 VMSTATE_END_OF_LIST()
348 static void raven_class_init(ObjectClass *klass, void *data)
350 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
351 DeviceClass *dc = DEVICE_CLASS(klass);
353 k->realize = raven_realize;
354 k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
355 k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
357 k->class_id = PCI_CLASS_BRIDGE_HOST;
358 dc->desc = "PReP Host Bridge - Motorola Raven";
359 dc->vmsd = &vmstate_raven;
361 * Reason: PCI-facing part of the host bridge, not usable without
362 * the host-facing part, which can't be device_add'ed, yet.
363 * Reason: realize() method uses hw_error().
365 dc->cannot_instantiate_with_device_add_yet = true;
368 static const TypeInfo raven_info = {
369 .name = TYPE_RAVEN_PCI_DEVICE,
370 .parent = TYPE_PCI_DEVICE,
371 .instance_size = sizeof(RavenPCIState),
372 .class_init = raven_class_init,
375 static Property raven_pcihost_properties[] = {
376 DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
378 DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
379 DEFINE_PROP_END_OF_LIST()
382 static void raven_pcihost_class_init(ObjectClass *klass, void *data)
384 DeviceClass *dc = DEVICE_CLASS(klass);
386 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
387 dc->realize = raven_pcihost_realizefn;
388 dc->props = raven_pcihost_properties;
392 static const TypeInfo raven_pcihost_info = {
393 .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
394 .parent = TYPE_PCI_HOST_BRIDGE,
395 .instance_size = sizeof(PREPPCIState),
396 .instance_init = raven_pcihost_initfn,
397 .class_init = raven_pcihost_class_init,
400 static void raven_register_types(void)
402 type_register_static(&raven_pcihost_info);
403 type_register_static(&raven_info);
406 type_init(raven_register_types)