2 * QEMU models for LatticeMico32 uclinux and evr32 boards.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
23 #include "hw/sysbus.h"
25 #include "hw/block/flash.h"
26 #include "hw/devices.h"
27 #include "hw/boards.h"
28 #include "hw/loader.h"
29 #include "sysemu/block-backend.h"
31 #include "lm32_hwsetup.h"
33 #include "exec/address-spaces.h"
45 static void cpu_irq_handler(void *opaque, int irq, int level)
47 LM32CPU *cpu = opaque;
48 CPUState *cs = CPU(cpu);
51 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
53 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
57 static void main_cpu_reset(void *opaque)
59 ResetInfo *reset_info = opaque;
60 CPULM32State *env = &reset_info->cpu->env;
62 cpu_reset(CPU(reset_info->cpu));
65 env->pc = (uint32_t)reset_info->bootstrap_pc;
66 env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
67 env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
68 env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
69 env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
70 reset_info->initrd_size);
71 env->eba = reset_info->flash_base;
72 env->deba = reset_info->flash_base;
75 static void lm32_evr_init(MachineState *machine)
77 const char *cpu_model = machine->cpu_model;
78 const char *kernel_filename = machine->kernel_filename;
82 MemoryRegion *address_space_mem = get_system_memory();
83 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
85 ResetInfo *reset_info;
89 hwaddr flash_base = 0x04000000;
90 size_t flash_sector_size = 256 * 1024;
91 size_t flash_size = 32 * 1024 * 1024;
92 hwaddr ram_base = 0x08000000;
93 size_t ram_size = 64 * 1024 * 1024;
94 hwaddr timer0_base = 0x80002000;
95 hwaddr uart0_base = 0x80006000;
96 hwaddr timer1_base = 0x8000a000;
101 reset_info = g_malloc0(sizeof(ResetInfo));
103 if (cpu_model == NULL) {
104 cpu_model = "lm32-full";
106 cpu = cpu_lm32_init(cpu_model);
108 fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
113 reset_info->cpu = cpu;
115 reset_info->flash_base = flash_base;
117 memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
119 memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
121 dinfo = drive_get(IF_PFLASH, 0, 0);
122 /* Spansion S29NS128P */
123 pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
124 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
125 flash_sector_size, flash_size / flash_sector_size,
126 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
128 /* create irq lines */
129 env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
130 for (i = 0; i < 32; i++) {
131 irq[i] = qdev_get_gpio_in(env->pic_state, i);
134 sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
135 sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
136 sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
138 /* make sure juart isn't the first chardev */
139 env->juart_state = lm32_juart_init();
141 reset_info->bootstrap_pc = flash_base;
143 if (kernel_filename) {
147 kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
148 1, EM_LATTICEMICO32, 0, 0);
149 reset_info->bootstrap_pc = entry;
151 if (kernel_size < 0) {
152 kernel_size = load_image_targphys(kernel_filename, ram_base,
154 reset_info->bootstrap_pc = ram_base;
157 if (kernel_size < 0) {
158 fprintf(stderr, "qemu: could not load kernel '%s'\n",
164 qemu_register_reset(main_cpu_reset, reset_info);
167 static void lm32_uclinux_init(MachineState *machine)
169 const char *cpu_model = machine->cpu_model;
170 const char *kernel_filename = machine->kernel_filename;
171 const char *kernel_cmdline = machine->kernel_cmdline;
172 const char *initrd_filename = machine->initrd_filename;
176 MemoryRegion *address_space_mem = get_system_memory();
177 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
180 ResetInfo *reset_info;
184 hwaddr flash_base = 0x04000000;
185 size_t flash_sector_size = 256 * 1024;
186 size_t flash_size = 32 * 1024 * 1024;
187 hwaddr ram_base = 0x08000000;
188 size_t ram_size = 64 * 1024 * 1024;
189 hwaddr uart0_base = 0x80000000;
190 hwaddr timer0_base = 0x80002000;
191 hwaddr timer1_base = 0x80010000;
192 hwaddr timer2_base = 0x80012000;
197 hwaddr hwsetup_base = 0x0bffe000;
198 hwaddr cmdline_base = 0x0bfff000;
199 hwaddr initrd_base = 0x08400000;
200 size_t initrd_max = 0x01000000;
202 reset_info = g_malloc0(sizeof(ResetInfo));
204 if (cpu_model == NULL) {
205 cpu_model = "lm32-full";
207 cpu = cpu_lm32_init(cpu_model);
209 fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
214 reset_info->cpu = cpu;
216 reset_info->flash_base = flash_base;
218 memory_region_allocate_system_memory(phys_ram, NULL,
219 "lm32_uclinux.sdram", ram_size);
220 memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
222 dinfo = drive_get(IF_PFLASH, 0, 0);
223 /* Spansion S29NS128P */
224 pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
225 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
226 flash_sector_size, flash_size / flash_sector_size,
227 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
229 /* create irq lines */
230 env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
231 for (i = 0; i < 32; i++) {
232 irq[i] = qdev_get_gpio_in(env->pic_state, i);
235 sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
236 sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
237 sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
238 sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
240 /* make sure juart isn't the first chardev */
241 env->juart_state = lm32_juart_init();
243 reset_info->bootstrap_pc = flash_base;
245 if (kernel_filename) {
249 kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
250 1, EM_LATTICEMICO32, 0, 0);
251 reset_info->bootstrap_pc = entry;
253 if (kernel_size < 0) {
254 kernel_size = load_image_targphys(kernel_filename, ram_base,
256 reset_info->bootstrap_pc = ram_base;
259 if (kernel_size < 0) {
260 fprintf(stderr, "qemu: could not load kernel '%s'\n",
266 /* generate a rom with the hardware description */
268 hwsetup_add_cpu(hw, "LM32", 75000000);
269 hwsetup_add_flash(hw, "flash", flash_base, flash_size);
270 hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
271 hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
272 hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
273 hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
274 hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
275 hwsetup_add_trailer(hw);
276 hwsetup_create_rom(hw, hwsetup_base);
279 reset_info->hwsetup_base = hwsetup_base;
281 if (kernel_cmdline && strlen(kernel_cmdline)) {
282 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
284 reset_info->cmdline_base = cmdline_base;
287 if (initrd_filename) {
289 initrd_size = load_image_targphys(initrd_filename, initrd_base,
291 reset_info->initrd_base = initrd_base;
292 reset_info->initrd_size = initrd_size;
295 qemu_register_reset(main_cpu_reset, reset_info);
298 static void lm32_evr_class_init(ObjectClass *oc, void *data)
300 MachineClass *mc = MACHINE_CLASS(oc);
302 mc->desc = "LatticeMico32 EVR32 eval system";
303 mc->init = lm32_evr_init;
307 static const TypeInfo lm32_evr_type = {
308 .name = MACHINE_TYPE_NAME("lm32-evr"),
309 .parent = TYPE_MACHINE,
310 .class_init = lm32_evr_class_init,
313 static void lm32_uclinux_class_init(ObjectClass *oc, void *data)
315 MachineClass *mc = MACHINE_CLASS(oc);
317 mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
318 mc->init = lm32_uclinux_init;
322 static const TypeInfo lm32_uclinux_type = {
323 .name = MACHINE_TYPE_NAME("lm32-uclinux"),
324 .parent = TYPE_MACHINE,
325 .class_init = lm32_uclinux_class_init,
328 static void lm32_machine_init(void)
330 type_register_static(&lm32_evr_type);
331 type_register_static(&lm32_uclinux_type);
334 type_init(lm32_machine_init)