4 * Copyright (c) 2004 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Based on OpenPic implementations:
28 * - Intel GW80314 I/O companion chip developer's manual
29 * - Motorola MPC8245 & MPC8540 user manuals.
30 * - Motorola MCP750 (aka Raven) programmer manual.
31 * - Motorola Harrier programmer manuel
33 * Serial interrupts, as implemented in Raven chipset are not supported yet.
36 #include "qemu/osdep.h"
38 #include "hw/ppc/mac.h"
39 #include "hw/pci/pci.h"
40 #include "hw/ppc/openpic.h"
41 #include "hw/ppc/ppc_e500.h"
42 #include "hw/sysbus.h"
43 #include "hw/pci/msi.h"
44 #include "qapi/error.h"
45 #include "qemu/bitops.h"
46 #include "qapi/qmp/qerror.h"
48 //#define DEBUG_OPENPIC
51 static const int debug_openpic = 1;
53 static const int debug_openpic = 0;
56 #define DPRINTF(fmt, ...) do { \
57 if (debug_openpic) { \
58 printf(fmt , ## __VA_ARGS__); \
64 #define VID 0x03 /* MPIC version ID */
66 /* OpenPIC capability flags */
67 #define OPENPIC_FLAG_IDR_CRIT (1 << 0)
68 #define OPENPIC_FLAG_ILR (2 << 0)
70 /* OpenPIC address map */
71 #define OPENPIC_GLB_REG_START 0x0
72 #define OPENPIC_GLB_REG_SIZE 0x10F0
73 #define OPENPIC_TMR_REG_START 0x10F0
74 #define OPENPIC_TMR_REG_SIZE 0x220
75 #define OPENPIC_MSI_REG_START 0x1600
76 #define OPENPIC_MSI_REG_SIZE 0x200
77 #define OPENPIC_SUMMARY_REG_START 0x3800
78 #define OPENPIC_SUMMARY_REG_SIZE 0x800
79 #define OPENPIC_SRC_REG_START 0x10000
80 #define OPENPIC_SRC_REG_SIZE (OPENPIC_MAX_SRC * 0x20)
81 #define OPENPIC_CPU_REG_START 0x20000
82 #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
85 #define RAVEN_MAX_CPU 2
86 #define RAVEN_MAX_EXT 48
87 #define RAVEN_MAX_IRQ 64
88 #define RAVEN_MAX_TMR OPENPIC_MAX_TMR
89 #define RAVEN_MAX_IPI OPENPIC_MAX_IPI
91 /* Interrupt definitions */
92 #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */
93 #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */
94 #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */
95 #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
96 /* First doorbell IRQ */
97 #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
99 typedef struct FslMpicInfo {
103 static FslMpicInfo fsl_mpic_20 = {
107 static FslMpicInfo fsl_mpic_42 = {
111 #define FRR_NIRQ_SHIFT 16
112 #define FRR_NCPU_SHIFT 8
113 #define FRR_VID_SHIFT 0
115 #define VID_REVISION_1_2 2
116 #define VID_REVISION_1_3 3
118 #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */
120 #define GCR_RESET 0x80000000
121 #define GCR_MODE_PASS 0x00000000
122 #define GCR_MODE_MIXED 0x20000000
123 #define GCR_MODE_PROXY 0x60000000
125 #define TBCR_CI 0x80000000 /* count inhibit */
126 #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */
128 #define IDR_EP_SHIFT 31
129 #define IDR_EP_MASK (1U << IDR_EP_SHIFT)
130 #define IDR_CI0_SHIFT 30
131 #define IDR_CI1_SHIFT 29
132 #define IDR_P1_SHIFT 1
133 #define IDR_P0_SHIFT 0
135 #define ILR_INTTGT_MASK 0x000000ff
136 #define ILR_INTTGT_INT 0x00
137 #define ILR_INTTGT_CINT 0x01 /* critical */
138 #define ILR_INTTGT_MCP 0x02 /* machine check */
140 /* The currently supported INTTGT values happen to be the same as QEMU's
141 * openpic output codes, but don't depend on this. The output codes
142 * could change (unlikely, but...) or support could be added for
143 * more INTTGT values.
145 static const int inttgt_output[][2] = {
146 { ILR_INTTGT_INT, OPENPIC_OUTPUT_INT },
147 { ILR_INTTGT_CINT, OPENPIC_OUTPUT_CINT },
148 { ILR_INTTGT_MCP, OPENPIC_OUTPUT_MCK },
151 static int inttgt_to_output(int inttgt)
155 for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) {
156 if (inttgt_output[i][0] == inttgt) {
157 return inttgt_output[i][1];
161 fprintf(stderr, "%s: unsupported inttgt %d\n", __func__, inttgt);
162 return OPENPIC_OUTPUT_INT;
165 static int output_to_inttgt(int output)
169 for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) {
170 if (inttgt_output[i][1] == output) {
171 return inttgt_output[i][0];
178 #define MSIIR_OFFSET 0x140
179 #define MSIIR_SRS_SHIFT 29
180 #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT)
181 #define MSIIR_IBS_SHIFT 24
182 #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT)
184 static int get_current_cpu(void)
190 return current_cpu->cpu_index;
193 static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
195 static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
196 uint32_t val, int idx);
197 static void openpic_reset(DeviceState *d);
199 typedef enum IRQType {
201 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
202 IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */
205 /* Round up to the nearest 64 IRQs so that the queue length
206 * won't change when moving between 32 and 64 bit hosts.
208 #define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63)
210 typedef struct IRQQueue {
211 unsigned long *queue;
212 int32_t queue_size; /* Only used for VMSTATE_BITMAP */
217 typedef struct IRQSource {
218 uint32_t ivpr; /* IRQ vector/priority register */
219 uint32_t idr; /* IRQ destination register */
220 uint32_t destmask; /* bitmap of CPU destinations */
222 int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */
223 int pending; /* TRUE if IRQ is pending */
225 bool level:1; /* level-triggered */
226 bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */
229 #define IVPR_MASK_SHIFT 31
230 #define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT)
231 #define IVPR_ACTIVITY_SHIFT 30
232 #define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT)
233 #define IVPR_MODE_SHIFT 29
234 #define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT)
235 #define IVPR_POLARITY_SHIFT 23
236 #define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT)
237 #define IVPR_SENSE_SHIFT 22
238 #define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT)
240 #define IVPR_PRIORITY_MASK (0xFU << 16)
241 #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
242 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
244 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
245 #define IDR_EP 0x80000000 /* external pin */
246 #define IDR_CI 0x40000000 /* critical interrupt */
248 typedef struct OpenPICTimer {
249 uint32_t tccr; /* Global timer current count register */
250 uint32_t tbcr; /* Global timer base count register */
253 typedef struct OpenPICMSI {
254 uint32_t msir; /* Shared Message Signaled Interrupt Register */
257 typedef struct IRQDest {
258 int32_t ctpr; /* CPU current task priority */
263 /* Count of IRQ sources asserting on non-INT outputs */
264 uint32_t outputs_active[OPENPIC_OUTPUT_NB];
267 #define OPENPIC(obj) OBJECT_CHECK(OpenPICState, (obj), TYPE_OPENPIC)
269 typedef struct OpenPICState {
271 SysBusDevice parent_obj;
276 /* Behavior control */
282 uint32_t vir; /* Vendor identification register */
283 uint32_t vector_mask;
288 uint32_t mpic_mode_mask;
291 MemoryRegion sub_io_mem[6];
293 /* Global registers */
294 uint32_t frr; /* Feature reporting register */
295 uint32_t gcr; /* Global configuration register */
296 uint32_t pir; /* Processor initialization register */
297 uint32_t spve; /* Spurious vector register */
298 uint32_t tfrr; /* Timer frequency reporting register */
299 /* Source registers */
300 IRQSource src[OPENPIC_MAX_IRQ];
301 /* Local registers per output pin */
302 IRQDest dst[MAX_CPU];
304 /* Timer registers */
305 OpenPICTimer timers[OPENPIC_MAX_TMR];
306 /* Shared MSI registers */
307 OpenPICMSI msi[MAX_MSI];
314 static inline void IRQ_setbit(IRQQueue *q, int n_IRQ)
316 set_bit(n_IRQ, q->queue);
319 static inline void IRQ_resetbit(IRQQueue *q, int n_IRQ)
321 clear_bit(n_IRQ, q->queue);
324 static void IRQ_check(OpenPICState *opp, IRQQueue *q)
331 irq = find_next_bit(q->queue, opp->max_irq, irq + 1);
332 if (irq == opp->max_irq) {
336 DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n",
337 irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority);
339 if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) {
341 priority = IVPR_PRIORITY(opp->src[irq].ivpr);
346 q->priority = priority;
349 static int IRQ_get_next(OpenPICState *opp, IRQQueue *q)
357 static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ,
358 bool active, bool was_active)
364 dst = &opp->dst[n_CPU];
365 src = &opp->src[n_IRQ];
367 DPRINTF("%s: IRQ %d active %d was %d\n",
368 __func__, n_IRQ, active, was_active);
370 if (src->output != OPENPIC_OUTPUT_INT) {
371 DPRINTF("%s: output %d irq %d active %d was %d count %d\n",
372 __func__, src->output, n_IRQ, active, was_active,
373 dst->outputs_active[src->output]);
375 /* On Freescale MPIC, critical interrupts ignore priority,
376 * IACK, EOI, etc. Before MPIC v4.1 they also ignore
380 if (!was_active && dst->outputs_active[src->output]++ == 0) {
381 DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n",
382 __func__, src->output, n_CPU, n_IRQ);
383 qemu_irq_raise(dst->irqs[src->output]);
386 if (was_active && --dst->outputs_active[src->output] == 0) {
387 DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n",
388 __func__, src->output, n_CPU, n_IRQ);
389 qemu_irq_lower(dst->irqs[src->output]);
396 priority = IVPR_PRIORITY(src->ivpr);
398 /* Even if the interrupt doesn't have enough priority,
399 * it is still raised, in case ctpr is lowered later.
402 IRQ_setbit(&dst->raised, n_IRQ);
404 IRQ_resetbit(&dst->raised, n_IRQ);
407 IRQ_check(opp, &dst->raised);
409 if (active && priority <= dst->ctpr) {
410 DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n",
411 __func__, n_IRQ, priority, dst->ctpr, n_CPU);
416 if (IRQ_get_next(opp, &dst->servicing) >= 0 &&
417 priority <= dst->servicing.priority) {
418 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
419 __func__, n_IRQ, dst->servicing.next, n_CPU);
421 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n",
422 __func__, n_CPU, n_IRQ, dst->raised.next);
423 qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
426 IRQ_get_next(opp, &dst->servicing);
427 if (dst->raised.priority > dst->ctpr &&
428 dst->raised.priority > dst->servicing.priority) {
429 DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n",
430 __func__, n_IRQ, dst->raised.next, dst->raised.priority,
431 dst->ctpr, dst->servicing.priority, n_CPU);
432 /* IRQ line stays asserted */
434 DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n",
435 __func__, n_IRQ, dst->ctpr, dst->servicing.priority, n_CPU);
436 qemu_irq_lower(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
441 /* update pic state because registers for n_IRQ have changed value */
442 static void openpic_update_irq(OpenPICState *opp, int n_IRQ)
445 bool active, was_active;
448 src = &opp->src[n_IRQ];
449 active = src->pending;
451 if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) {
452 /* Interrupt source is disabled */
453 DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
457 was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK);
460 * We don't have a similar check for already-active because
461 * ctpr may have changed and we need to withdraw the interrupt.
463 if (!active && !was_active) {
464 DPRINTF("%s: IRQ %d is already inactive\n", __func__, n_IRQ);
469 src->ivpr |= IVPR_ACTIVITY_MASK;
471 src->ivpr &= ~IVPR_ACTIVITY_MASK;
474 if (src->destmask == 0) {
476 DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
480 if (src->destmask == (1 << src->last_cpu)) {
481 /* Only one CPU is allowed to receive this IRQ */
482 IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active);
483 } else if (!(src->ivpr & IVPR_MODE_MASK)) {
484 /* Directed delivery mode */
485 for (i = 0; i < opp->nb_cpus; i++) {
486 if (src->destmask & (1 << i)) {
487 IRQ_local_pipe(opp, i, n_IRQ, active, was_active);
491 /* Distributed delivery mode */
492 for (i = src->last_cpu + 1; i != src->last_cpu; i++) {
493 if (i == opp->nb_cpus) {
496 if (src->destmask & (1 << i)) {
497 IRQ_local_pipe(opp, i, n_IRQ, active, was_active);
505 static void openpic_set_irq(void *opaque, int n_IRQ, int level)
507 OpenPICState *opp = opaque;
510 if (n_IRQ >= OPENPIC_MAX_IRQ) {
511 fprintf(stderr, "%s: IRQ %d out of range\n", __func__, n_IRQ);
515 src = &opp->src[n_IRQ];
516 DPRINTF("openpic: set irq %d = %d ivpr=0x%08x\n",
517 n_IRQ, level, src->ivpr);
519 /* level-sensitive irq */
520 src->pending = level;
521 openpic_update_irq(opp, n_IRQ);
523 /* edge-sensitive irq */
526 openpic_update_irq(opp, n_IRQ);
529 if (src->output != OPENPIC_OUTPUT_INT) {
530 /* Edge-triggered interrupts shouldn't be used
531 * with non-INT delivery, but just in case,
532 * try to make it do something sane rather than
533 * cause an interrupt storm. This is close to
534 * what you'd probably see happen in real hardware.
537 openpic_update_irq(opp, n_IRQ);
542 static inline uint32_t read_IRQreg_idr(OpenPICState *opp, int n_IRQ)
544 return opp->src[n_IRQ].idr;
547 static inline uint32_t read_IRQreg_ilr(OpenPICState *opp, int n_IRQ)
549 if (opp->flags & OPENPIC_FLAG_ILR) {
550 return output_to_inttgt(opp->src[n_IRQ].output);
556 static inline uint32_t read_IRQreg_ivpr(OpenPICState *opp, int n_IRQ)
558 return opp->src[n_IRQ].ivpr;
561 static inline void write_IRQreg_idr(OpenPICState *opp, int n_IRQ, uint32_t val)
563 IRQSource *src = &opp->src[n_IRQ];
564 uint32_t normal_mask = (1UL << opp->nb_cpus) - 1;
565 uint32_t crit_mask = 0;
566 uint32_t mask = normal_mask;
567 int crit_shift = IDR_EP_SHIFT - opp->nb_cpus;
570 if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
571 crit_mask = mask << crit_shift;
572 mask |= crit_mask | IDR_EP;
575 src->idr = val & mask;
576 DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ, src->idr);
578 if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
579 if (src->idr & crit_mask) {
580 if (src->idr & normal_mask) {
581 DPRINTF("%s: IRQ configured for multiple output types, using "
582 "critical\n", __func__);
585 src->output = OPENPIC_OUTPUT_CINT;
589 for (i = 0; i < opp->nb_cpus; i++) {
590 int n_ci = IDR_CI0_SHIFT - i;
592 if (src->idr & (1UL << n_ci)) {
593 src->destmask |= 1UL << i;
597 src->output = OPENPIC_OUTPUT_INT;
599 src->destmask = src->idr & normal_mask;
602 src->destmask = src->idr;
606 static inline void write_IRQreg_ilr(OpenPICState *opp, int n_IRQ, uint32_t val)
608 if (opp->flags & OPENPIC_FLAG_ILR) {
609 IRQSource *src = &opp->src[n_IRQ];
611 src->output = inttgt_to_output(val & ILR_INTTGT_MASK);
612 DPRINTF("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr,
615 /* TODO: on MPIC v4.0 only, set nomask for non-INT */
619 static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val)
623 /* NOTE when implementing newer FSL MPIC models: starting with v4.0,
624 * the polarity bit is read-only on internal interrupts.
626 mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK |
627 IVPR_POLARITY_MASK | opp->vector_mask;
629 /* ACTIVITY bit is read-only */
630 opp->src[n_IRQ].ivpr =
631 (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);
633 /* For FSL internal interrupts, The sense bit is reserved and zero,
634 * and the interrupt is always level-triggered. Timers and IPIs
635 * have no sense or polarity bits, and are edge-triggered.
637 switch (opp->src[n_IRQ].type) {
638 case IRQ_TYPE_NORMAL:
639 opp->src[n_IRQ].level = !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK);
642 case IRQ_TYPE_FSLINT:
643 opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK;
646 case IRQ_TYPE_FSLSPECIAL:
647 opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK);
651 openpic_update_irq(opp, n_IRQ);
652 DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
653 opp->src[n_IRQ].ivpr);
656 static void openpic_gcr_write(OpenPICState *opp, uint64_t val)
658 bool mpic_proxy = false;
660 if (val & GCR_RESET) {
661 openpic_reset(DEVICE(opp));
665 opp->gcr &= ~opp->mpic_mode_mask;
666 opp->gcr |= val & opp->mpic_mode_mask;
668 /* Set external proxy mode */
669 if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) {
673 ppce500_set_mpic_proxy(mpic_proxy);
676 static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
679 OpenPICState *opp = opaque;
683 DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
684 __func__, addr, val);
689 case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
699 openpic_cpu_write_internal(opp, addr, val, get_current_cpu());
701 case 0x1000: /* FRR */
703 case 0x1020: /* GCR */
704 openpic_gcr_write(opp, val);
706 case 0x1080: /* VIR */
708 case 0x1090: /* PIR */
709 for (idx = 0; idx < opp->nb_cpus; idx++) {
710 if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) {
711 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
712 dst = &opp->dst[idx];
713 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]);
714 } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) {
715 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
716 dst = &opp->dst[idx];
717 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]);
722 case 0x10A0: /* IPI_IVPR */
728 idx = (addr - 0x10A0) >> 4;
729 write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val);
732 case 0x10E0: /* SPVE */
733 opp->spve = val & opp->vector_mask;
740 static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
742 OpenPICState *opp = opaque;
745 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
751 case 0x1000: /* FRR */
754 case 0x1020: /* GCR */
757 case 0x1080: /* VIR */
760 case 0x1090: /* PIR */
763 case 0x00: /* Block Revision Register1 (BRR1) */
774 retval = openpic_cpu_read_internal(opp, addr, get_current_cpu());
776 case 0x10A0: /* IPI_IVPR */
782 idx = (addr - 0x10A0) >> 4;
783 retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx);
786 case 0x10E0: /* SPVE */
792 DPRINTF("%s: => 0x%08x\n", __func__, retval);
797 static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,
800 OpenPICState *opp = opaque;
805 DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
806 __func__, addr, val);
811 if (addr == 0x10f0) {
817 idx = (addr >> 6) & 0x3;
820 switch (addr & 0x30) {
821 case 0x00: /* TCCR */
823 case 0x10: /* TBCR */
824 if ((opp->timers[idx].tccr & TCCR_TOG) != 0 &&
825 (val & TBCR_CI) == 0 &&
826 (opp->timers[idx].tbcr & TBCR_CI) != 0) {
827 opp->timers[idx].tccr &= ~TCCR_TOG;
829 opp->timers[idx].tbcr = val;
831 case 0x20: /* TVPR */
832 write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val);
835 write_IRQreg_idr(opp, opp->irq_tim0 + idx, val);
840 static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len)
842 OpenPICState *opp = opaque;
843 uint32_t retval = -1;
846 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
850 idx = (addr >> 6) & 0x3;
856 switch (addr & 0x30) {
857 case 0x00: /* TCCR */
858 retval = opp->timers[idx].tccr;
860 case 0x10: /* TBCR */
861 retval = opp->timers[idx].tbcr;
863 case 0x20: /* TIPV */
864 retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx);
866 case 0x30: /* TIDE (TIDR) */
867 retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx);
872 DPRINTF("%s: => 0x%08x\n", __func__, retval);
877 static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val,
880 OpenPICState *opp = opaque;
883 DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
884 __func__, addr, val);
886 addr = addr & 0xffff;
889 switch (addr & 0x1f) {
891 write_IRQreg_ivpr(opp, idx, val);
894 write_IRQreg_idr(opp, idx, val);
897 write_IRQreg_ilr(opp, idx, val);
902 static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
904 OpenPICState *opp = opaque;
908 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
911 addr = addr & 0xffff;
914 switch (addr & 0x1f) {
916 retval = read_IRQreg_ivpr(opp, idx);
919 retval = read_IRQreg_idr(opp, idx);
922 retval = read_IRQreg_ilr(opp, idx);
926 DPRINTF("%s: => 0x%08x\n", __func__, retval);
930 static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val,
933 OpenPICState *opp = opaque;
934 int idx = opp->irq_msi;
937 DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n",
938 __func__, addr, val);
945 srs = val >> MSIIR_SRS_SHIFT;
947 ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT;
948 opp->msi[srs].msir |= 1 << ibs;
949 openpic_set_irq(opp, idx, 1);
952 /* most registers are read-only, thus ignored */
957 static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size)
959 OpenPICState *opp = opaque;
963 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
978 case 0x70: /* MSIRs */
979 r = opp->msi[srs].msir;
981 opp->msi[srs].msir = 0;
982 openpic_set_irq(opp, opp->irq_msi + srs, 0);
984 case 0x120: /* MSISR */
985 for (i = 0; i < MAX_MSI; i++) {
986 r |= (opp->msi[i].msir ? 1 : 0) << i;
994 static uint64_t openpic_summary_read(void *opaque, hwaddr addr, unsigned size)
998 DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
1000 /* TODO: EISR/EIMR */
1005 static void openpic_summary_write(void *opaque, hwaddr addr, uint64_t val,
1008 DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n",
1009 __func__, addr, val);
1011 /* TODO: EISR/EIMR */
1014 static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
1015 uint32_t val, int idx)
1017 OpenPICState *opp = opaque;
1022 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <= 0x%08x\n", __func__, idx,
1025 if (idx < 0 || idx >= opp->nb_cpus) {
1032 dst = &opp->dst[idx];
1035 case 0x40: /* IPIDR */
1039 idx = (addr - 0x40) >> 4;
1040 /* we use IDE as mask which CPUs to deliver the IPI to still. */
1041 opp->src[opp->irq_ipi0 + idx].destmask |= val;
1042 openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
1043 openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
1045 case 0x80: /* CTPR */
1046 dst->ctpr = val & 0x0000000F;
1048 DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n",
1049 __func__, idx, dst->ctpr, dst->raised.priority,
1050 dst->servicing.priority);
1052 if (dst->raised.priority <= dst->ctpr) {
1053 DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n",
1055 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
1056 } else if (dst->raised.priority > dst->servicing.priority) {
1057 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n",
1058 __func__, idx, dst->raised.next);
1059 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]);
1063 case 0x90: /* WHOAMI */
1064 /* Read-only register */
1066 case 0xA0: /* IACK */
1067 /* Read-only register */
1069 case 0xB0: /* EOI */
1071 s_IRQ = IRQ_get_next(opp, &dst->servicing);
1074 DPRINTF("%s: EOI with no interrupt in service\n", __func__);
1078 IRQ_resetbit(&dst->servicing, s_IRQ);
1079 /* Set up next servicing IRQ */
1080 s_IRQ = IRQ_get_next(opp, &dst->servicing);
1081 /* Check queued interrupts. */
1082 n_IRQ = IRQ_get_next(opp, &dst->raised);
1083 src = &opp->src[n_IRQ];
1086 IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) {
1087 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
1089 qemu_irq_raise(opp->dst[idx].irqs[OPENPIC_OUTPUT_INT]);
1097 static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val,
1100 openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
1104 static uint32_t openpic_iack(OpenPICState *opp, IRQDest *dst, int cpu)
1109 DPRINTF("Lower OpenPIC INT output\n");
1110 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
1112 irq = IRQ_get_next(opp, &dst->raised);
1113 DPRINTF("IACK: irq=%d\n", irq);
1116 /* No more interrupt pending */
1120 src = &opp->src[irq];
1121 if (!(src->ivpr & IVPR_ACTIVITY_MASK) ||
1122 !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) {
1123 fprintf(stderr, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n",
1124 __func__, irq, dst->ctpr, src->ivpr);
1125 openpic_update_irq(opp, irq);
1128 /* IRQ enter servicing state */
1129 IRQ_setbit(&dst->servicing, irq);
1130 retval = IVPR_VECTOR(opp, src->ivpr);
1134 /* edge-sensitive IRQ */
1135 src->ivpr &= ~IVPR_ACTIVITY_MASK;
1137 IRQ_resetbit(&dst->raised, irq);
1140 if ((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + OPENPIC_MAX_IPI))) {
1141 src->destmask &= ~(1 << cpu);
1142 if (src->destmask && !src->level) {
1143 /* trigger on CPUs that didn't know about it yet */
1144 openpic_set_irq(opp, irq, 1);
1145 openpic_set_irq(opp, irq, 0);
1146 /* if all CPUs knew about it, set active bit again */
1147 src->ivpr |= IVPR_ACTIVITY_MASK;
1154 static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
1157 OpenPICState *opp = opaque;
1161 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx "\n", __func__, idx, addr);
1162 retval = 0xFFFFFFFF;
1164 if (idx < 0 || idx >= opp->nb_cpus) {
1171 dst = &opp->dst[idx];
1174 case 0x80: /* CTPR */
1177 case 0x90: /* WHOAMI */
1180 case 0xA0: /* IACK */
1181 retval = openpic_iack(opp, dst, idx);
1183 case 0xB0: /* EOI */
1189 DPRINTF("%s: => 0x%08x\n", __func__, retval);
1194 static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
1196 return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
1199 static const MemoryRegionOps openpic_glb_ops_le = {
1200 .write = openpic_gbl_write,
1201 .read = openpic_gbl_read,
1202 .endianness = DEVICE_LITTLE_ENDIAN,
1204 .min_access_size = 4,
1205 .max_access_size = 4,
1209 static const MemoryRegionOps openpic_glb_ops_be = {
1210 .write = openpic_gbl_write,
1211 .read = openpic_gbl_read,
1212 .endianness = DEVICE_BIG_ENDIAN,
1214 .min_access_size = 4,
1215 .max_access_size = 4,
1219 static const MemoryRegionOps openpic_tmr_ops_le = {
1220 .write = openpic_tmr_write,
1221 .read = openpic_tmr_read,
1222 .endianness = DEVICE_LITTLE_ENDIAN,
1224 .min_access_size = 4,
1225 .max_access_size = 4,
1229 static const MemoryRegionOps openpic_tmr_ops_be = {
1230 .write = openpic_tmr_write,
1231 .read = openpic_tmr_read,
1232 .endianness = DEVICE_BIG_ENDIAN,
1234 .min_access_size = 4,
1235 .max_access_size = 4,
1239 static const MemoryRegionOps openpic_cpu_ops_le = {
1240 .write = openpic_cpu_write,
1241 .read = openpic_cpu_read,
1242 .endianness = DEVICE_LITTLE_ENDIAN,
1244 .min_access_size = 4,
1245 .max_access_size = 4,
1249 static const MemoryRegionOps openpic_cpu_ops_be = {
1250 .write = openpic_cpu_write,
1251 .read = openpic_cpu_read,
1252 .endianness = DEVICE_BIG_ENDIAN,
1254 .min_access_size = 4,
1255 .max_access_size = 4,
1259 static const MemoryRegionOps openpic_src_ops_le = {
1260 .write = openpic_src_write,
1261 .read = openpic_src_read,
1262 .endianness = DEVICE_LITTLE_ENDIAN,
1264 .min_access_size = 4,
1265 .max_access_size = 4,
1269 static const MemoryRegionOps openpic_src_ops_be = {
1270 .write = openpic_src_write,
1271 .read = openpic_src_read,
1272 .endianness = DEVICE_BIG_ENDIAN,
1274 .min_access_size = 4,
1275 .max_access_size = 4,
1279 static const MemoryRegionOps openpic_msi_ops_be = {
1280 .read = openpic_msi_read,
1281 .write = openpic_msi_write,
1282 .endianness = DEVICE_BIG_ENDIAN,
1284 .min_access_size = 4,
1285 .max_access_size = 4,
1289 static const MemoryRegionOps openpic_summary_ops_be = {
1290 .read = openpic_summary_read,
1291 .write = openpic_summary_write,
1292 .endianness = DEVICE_BIG_ENDIAN,
1294 .min_access_size = 4,
1295 .max_access_size = 4,
1299 static void openpic_reset(DeviceState *d)
1301 OpenPICState *opp = OPENPIC(d);
1304 opp->gcr = GCR_RESET;
1305 /* Initialise controller registers */
1306 opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) |
1307 ((opp->nb_cpus - 1) << FRR_NCPU_SHIFT) |
1308 (opp->vid << FRR_VID_SHIFT);
1311 opp->spve = -1 & opp->vector_mask;
1312 opp->tfrr = opp->tfrr_reset;
1313 /* Initialise IRQ sources */
1314 for (i = 0; i < opp->max_irq; i++) {
1315 opp->src[i].ivpr = opp->ivpr_reset;
1316 switch (opp->src[i].type) {
1317 case IRQ_TYPE_NORMAL:
1318 opp->src[i].level = !!(opp->ivpr_reset & IVPR_SENSE_MASK);
1321 case IRQ_TYPE_FSLINT:
1322 opp->src[i].ivpr |= IVPR_POLARITY_MASK;
1325 case IRQ_TYPE_FSLSPECIAL:
1329 write_IRQreg_idr(opp, i, opp->idr_reset);
1331 /* Initialise IRQ destinations */
1332 for (i = 0; i < opp->nb_cpus; i++) {
1333 opp->dst[i].ctpr = 15;
1334 opp->dst[i].raised.next = -1;
1335 opp->dst[i].raised.priority = 0;
1336 bitmap_clear(opp->dst[i].raised.queue, 0, IRQQUEUE_SIZE_BITS);
1337 opp->dst[i].servicing.next = -1;
1338 opp->dst[i].servicing.priority = 0;
1339 bitmap_clear(opp->dst[i].servicing.queue, 0, IRQQUEUE_SIZE_BITS);
1341 /* Initialise timers */
1342 for (i = 0; i < OPENPIC_MAX_TMR; i++) {
1343 opp->timers[i].tccr = 0;
1344 opp->timers[i].tbcr = TBCR_CI;
1346 /* Go out of RESET state */
1350 typedef struct MemReg {
1352 MemoryRegionOps const *ops;
1357 static void fsl_common_init(OpenPICState *opp)
1360 int virq = OPENPIC_MAX_SRC;
1362 opp->vid = VID_REVISION_1_2;
1363 opp->vir = VIR_GENERIC;
1364 opp->vector_mask = 0xFFFF;
1365 opp->tfrr_reset = 0;
1366 opp->ivpr_reset = IVPR_MASK_MASK;
1367 opp->idr_reset = 1 << 0;
1368 opp->max_irq = OPENPIC_MAX_IRQ;
1370 opp->irq_ipi0 = virq;
1371 virq += OPENPIC_MAX_IPI;
1372 opp->irq_tim0 = virq;
1373 virq += OPENPIC_MAX_TMR;
1375 assert(virq <= OPENPIC_MAX_IRQ);
1379 msi_nonbroken = true;
1380 for (i = 0; i < opp->fsl->max_ext; i++) {
1381 opp->src[i].level = false;
1384 /* Internal interrupts, including message and MSI */
1385 for (i = 16; i < OPENPIC_MAX_SRC; i++) {
1386 opp->src[i].type = IRQ_TYPE_FSLINT;
1387 opp->src[i].level = true;
1390 /* timers and IPIs */
1391 for (i = OPENPIC_MAX_SRC; i < virq; i++) {
1392 opp->src[i].type = IRQ_TYPE_FSLSPECIAL;
1393 opp->src[i].level = false;
1397 static void map_list(OpenPICState *opp, const MemReg *list, int *count)
1399 while (list->name) {
1400 assert(*count < ARRAY_SIZE(opp->sub_io_mem));
1402 memory_region_init_io(&opp->sub_io_mem[*count], OBJECT(opp), list->ops,
1403 opp, list->name, list->size);
1405 memory_region_add_subregion(&opp->mem, list->start_addr,
1406 &opp->sub_io_mem[*count]);
1413 static const VMStateDescription vmstate_openpic_irq_queue = {
1414 .name = "openpic_irq_queue",
1416 .minimum_version_id = 0,
1417 .fields = (VMStateField[]) {
1418 VMSTATE_BITMAP(queue, IRQQueue, 0, queue_size),
1419 VMSTATE_INT32(next, IRQQueue),
1420 VMSTATE_INT32(priority, IRQQueue),
1421 VMSTATE_END_OF_LIST()
1425 static const VMStateDescription vmstate_openpic_irqdest = {
1426 .name = "openpic_irqdest",
1428 .minimum_version_id = 0,
1429 .fields = (VMStateField[]) {
1430 VMSTATE_INT32(ctpr, IRQDest),
1431 VMSTATE_STRUCT(raised, IRQDest, 0, vmstate_openpic_irq_queue,
1433 VMSTATE_STRUCT(servicing, IRQDest, 0, vmstate_openpic_irq_queue,
1435 VMSTATE_UINT32_ARRAY(outputs_active, IRQDest, OPENPIC_OUTPUT_NB),
1436 VMSTATE_END_OF_LIST()
1440 static const VMStateDescription vmstate_openpic_irqsource = {
1441 .name = "openpic_irqsource",
1443 .minimum_version_id = 0,
1444 .fields = (VMStateField[]) {
1445 VMSTATE_UINT32(ivpr, IRQSource),
1446 VMSTATE_UINT32(idr, IRQSource),
1447 VMSTATE_UINT32(destmask, IRQSource),
1448 VMSTATE_INT32(last_cpu, IRQSource),
1449 VMSTATE_INT32(pending, IRQSource),
1450 VMSTATE_END_OF_LIST()
1454 static const VMStateDescription vmstate_openpic_timer = {
1455 .name = "openpic_timer",
1457 .minimum_version_id = 0,
1458 .fields = (VMStateField[]) {
1459 VMSTATE_UINT32(tccr, OpenPICTimer),
1460 VMSTATE_UINT32(tbcr, OpenPICTimer),
1461 VMSTATE_END_OF_LIST()
1465 static const VMStateDescription vmstate_openpic_msi = {
1466 .name = "openpic_msi",
1468 .minimum_version_id = 0,
1469 .fields = (VMStateField[]) {
1470 VMSTATE_UINT32(msir, OpenPICMSI),
1471 VMSTATE_END_OF_LIST()
1475 static int openpic_post_load(void *opaque, int version_id)
1477 OpenPICState *opp = (OpenPICState *)opaque;
1480 /* Update internal ivpr and idr variables */
1481 for (i = 0; i < opp->max_irq; i++) {
1482 write_IRQreg_idr(opp, i, opp->src[i].idr);
1483 write_IRQreg_ivpr(opp, i, opp->src[i].ivpr);
1489 static const VMStateDescription vmstate_openpic = {
1492 .minimum_version_id = 3,
1493 .post_load = openpic_post_load,
1494 .fields = (VMStateField[]) {
1495 VMSTATE_UINT32(gcr, OpenPICState),
1496 VMSTATE_UINT32(vir, OpenPICState),
1497 VMSTATE_UINT32(pir, OpenPICState),
1498 VMSTATE_UINT32(spve, OpenPICState),
1499 VMSTATE_UINT32(tfrr, OpenPICState),
1500 VMSTATE_UINT32(max_irq, OpenPICState),
1501 VMSTATE_STRUCT_VARRAY_UINT32(src, OpenPICState, max_irq, 0,
1502 vmstate_openpic_irqsource, IRQSource),
1503 VMSTATE_UINT32_EQUAL(nb_cpus, OpenPICState),
1504 VMSTATE_STRUCT_VARRAY_UINT32(dst, OpenPICState, nb_cpus, 0,
1505 vmstate_openpic_irqdest, IRQDest),
1506 VMSTATE_STRUCT_ARRAY(timers, OpenPICState, OPENPIC_MAX_TMR, 0,
1507 vmstate_openpic_timer, OpenPICTimer),
1508 VMSTATE_STRUCT_ARRAY(msi, OpenPICState, MAX_MSI, 0,
1509 vmstate_openpic_msi, OpenPICMSI),
1510 VMSTATE_UINT32(irq_ipi0, OpenPICState),
1511 VMSTATE_UINT32(irq_tim0, OpenPICState),
1512 VMSTATE_UINT32(irq_msi, OpenPICState),
1513 VMSTATE_END_OF_LIST()
1517 static void openpic_init(Object *obj)
1519 OpenPICState *opp = OPENPIC(obj);
1521 memory_region_init(&opp->mem, obj, "openpic", 0x40000);
1524 static void openpic_realize(DeviceState *dev, Error **errp)
1526 SysBusDevice *d = SYS_BUS_DEVICE(dev);
1527 OpenPICState *opp = OPENPIC(dev);
1530 static const MemReg list_le[] = {
1531 {"glb", &openpic_glb_ops_le,
1532 OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
1533 {"tmr", &openpic_tmr_ops_le,
1534 OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
1535 {"src", &openpic_src_ops_le,
1536 OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
1537 {"cpu", &openpic_cpu_ops_le,
1538 OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
1541 static const MemReg list_be[] = {
1542 {"glb", &openpic_glb_ops_be,
1543 OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
1544 {"tmr", &openpic_tmr_ops_be,
1545 OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
1546 {"src", &openpic_src_ops_be,
1547 OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
1548 {"cpu", &openpic_cpu_ops_be,
1549 OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
1552 static const MemReg list_fsl[] = {
1553 {"msi", &openpic_msi_ops_be,
1554 OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE},
1555 {"summary", &openpic_summary_ops_be,
1556 OPENPIC_SUMMARY_REG_START, OPENPIC_SUMMARY_REG_SIZE},
1560 if (opp->nb_cpus > MAX_CPU) {
1561 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
1562 TYPE_OPENPIC, "nb_cpus", (uint64_t)opp->nb_cpus,
1563 (uint64_t)0, (uint64_t)MAX_CPU);
1567 switch (opp->model) {
1568 case OPENPIC_MODEL_FSL_MPIC_20:
1570 opp->fsl = &fsl_mpic_20;
1571 opp->brr1 = 0x00400200;
1572 opp->flags |= OPENPIC_FLAG_IDR_CRIT;
1574 opp->mpic_mode_mask = GCR_MODE_MIXED;
1576 fsl_common_init(opp);
1577 map_list(opp, list_be, &list_count);
1578 map_list(opp, list_fsl, &list_count);
1582 case OPENPIC_MODEL_FSL_MPIC_42:
1583 opp->fsl = &fsl_mpic_42;
1584 opp->brr1 = 0x00400402;
1585 opp->flags |= OPENPIC_FLAG_ILR;
1587 opp->mpic_mode_mask = GCR_MODE_PROXY;
1589 fsl_common_init(opp);
1590 map_list(opp, list_be, &list_count);
1591 map_list(opp, list_fsl, &list_count);
1595 case OPENPIC_MODEL_RAVEN:
1596 opp->nb_irqs = RAVEN_MAX_EXT;
1597 opp->vid = VID_REVISION_1_3;
1598 opp->vir = VIR_GENERIC;
1599 opp->vector_mask = 0xFF;
1600 opp->tfrr_reset = 4160000;
1601 opp->ivpr_reset = IVPR_MASK_MASK | IVPR_MODE_MASK;
1603 opp->max_irq = RAVEN_MAX_IRQ;
1604 opp->irq_ipi0 = RAVEN_IPI_IRQ;
1605 opp->irq_tim0 = RAVEN_TMR_IRQ;
1607 opp->mpic_mode_mask = GCR_MODE_MIXED;
1609 if (opp->nb_cpus != 1) {
1610 error_setg(errp, "Only UP supported today");
1614 map_list(opp, list_le, &list_count);
1618 for (i = 0; i < opp->nb_cpus; i++) {
1619 opp->dst[i].irqs = g_new0(qemu_irq, OPENPIC_OUTPUT_NB);
1620 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
1621 sysbus_init_irq(d, &opp->dst[i].irqs[j]);
1624 opp->dst[i].raised.queue_size = IRQQUEUE_SIZE_BITS;
1625 opp->dst[i].raised.queue = bitmap_new(IRQQUEUE_SIZE_BITS);
1626 opp->dst[i].servicing.queue_size = IRQQUEUE_SIZE_BITS;
1627 opp->dst[i].servicing.queue = bitmap_new(IRQQUEUE_SIZE_BITS);
1630 sysbus_init_mmio(d, &opp->mem);
1631 qdev_init_gpio_in(dev, openpic_set_irq, opp->max_irq);
1634 static Property openpic_properties[] = {
1635 DEFINE_PROP_UINT32("model", OpenPICState, model, OPENPIC_MODEL_FSL_MPIC_20),
1636 DEFINE_PROP_UINT32("nb_cpus", OpenPICState, nb_cpus, 1),
1637 DEFINE_PROP_END_OF_LIST(),
1640 static void openpic_class_init(ObjectClass *oc, void *data)
1642 DeviceClass *dc = DEVICE_CLASS(oc);
1644 dc->realize = openpic_realize;
1645 dc->props = openpic_properties;
1646 dc->reset = openpic_reset;
1647 dc->vmsd = &vmstate_openpic;
1648 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
1651 static const TypeInfo openpic_info = {
1652 .name = TYPE_OPENPIC,
1653 .parent = TYPE_SYS_BUS_DEVICE,
1654 .instance_size = sizeof(OpenPICState),
1655 .instance_init = openpic_init,
1656 .class_init = openpic_class_init,
1659 static void openpic_register_types(void)
1661 type_register_static(&openpic_info);
1664 type_init(openpic_register_types)