2 * TI OMAP interrupt controller emulation.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "hw/arm/omap.h"
23 #include "hw/sysbus.h"
24 #include "qemu/error-report.h"
26 /* Interrupt Handlers */
27 struct omap_intr_handler_bank_s {
34 unsigned char priority[32];
37 #define TYPE_OMAP_INTC "common-omap-intc"
38 #define OMAP_INTC(obj) \
39 OBJECT_CHECK(struct omap_intr_handler_s, (obj), TYPE_OMAP_INTC)
41 struct omap_intr_handler_s {
42 SysBusDevice parent_obj;
45 qemu_irq parent_intr[2];
60 struct omap_intr_handler_bank_s bank[3];
63 static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
65 int i, j, sir_intr, p_intr, p;
70 /* Find the interrupt line with the highest dynamic priority.
71 * Note: 0 denotes the hightest priority.
72 * If all interrupts have the same priority, the default order is IRQ_N,
73 * IRQ_N-1,...,IRQ_0. */
74 for (j = 0; j < s->nbanks; ++j) {
75 level = s->bank[j].irqs & ~s->bank[j].mask &
76 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
80 p = s->bank[j].priority[i];
83 sir_intr = 32 * j + i;
88 s->sir_intr[is_fiq] = sir_intr;
91 static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
94 uint32_t has_intr = 0;
96 for (i = 0; i < s->nbanks; ++i)
97 has_intr |= s->bank[i].irqs & ~s->bank[i].mask &
98 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);
100 if (s->new_agr[is_fiq] & has_intr & s->mask) {
101 s->new_agr[is_fiq] = 0;
102 omap_inth_sir_update(s, is_fiq);
103 qemu_set_irq(s->parent_intr[is_fiq], 1);
107 #define INT_FALLING_EDGE 0
108 #define INT_LOW_LEVEL 1
110 static void omap_set_intr(void *opaque, int irq, int req)
112 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
115 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
119 rise = ~bank->irqs & (1 << n);
120 if (~bank->sens_edge & (1 << n))
121 rise &= ~bank->inputs;
123 bank->inputs |= (1 << n);
126 omap_inth_update(ih, 0);
127 omap_inth_update(ih, 1);
130 rise = bank->sens_edge & bank->irqs & (1 << n);
132 bank->inputs &= ~(1 << n);
136 /* Simplified version with no edge detection */
137 static void omap_set_intr_noedge(void *opaque, int irq, int req)
139 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
142 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
146 rise = ~bank->inputs & (1 << n);
148 bank->irqs |= bank->inputs |= rise;
149 omap_inth_update(ih, 0);
150 omap_inth_update(ih, 1);
153 bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
156 static uint64_t omap_inth_read(void *opaque, hwaddr addr,
159 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
160 int i, offset = addr;
161 int bank_no = offset >> 8;
163 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
173 case 0x10: /* SIR_IRQ_CODE */
174 case 0x14: /* SIR_FIQ_CODE */
177 line_no = s->sir_intr[(offset - 0x10) >> 2];
178 bank = &s->bank[line_no >> 5];
180 if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
181 bank->irqs &= ~(1 << i);
184 case 0x18: /* CONTROL_REG */
189 case 0x1c: /* ILR0 */
190 case 0x20: /* ILR1 */
191 case 0x24: /* ILR2 */
192 case 0x28: /* ILR3 */
193 case 0x2c: /* ILR4 */
194 case 0x30: /* ILR5 */
195 case 0x34: /* ILR6 */
196 case 0x38: /* ILR7 */
197 case 0x3c: /* ILR8 */
198 case 0x40: /* ILR9 */
199 case 0x44: /* ILR10 */
200 case 0x48: /* ILR11 */
201 case 0x4c: /* ILR12 */
202 case 0x50: /* ILR13 */
203 case 0x54: /* ILR14 */
204 case 0x58: /* ILR15 */
205 case 0x5c: /* ILR16 */
206 case 0x60: /* ILR17 */
207 case 0x64: /* ILR18 */
208 case 0x68: /* ILR19 */
209 case 0x6c: /* ILR20 */
210 case 0x70: /* ILR21 */
211 case 0x74: /* ILR22 */
212 case 0x78: /* ILR23 */
213 case 0x7c: /* ILR24 */
214 case 0x80: /* ILR25 */
215 case 0x84: /* ILR26 */
216 case 0x88: /* ILR27 */
217 case 0x8c: /* ILR28 */
218 case 0x90: /* ILR29 */
219 case 0x94: /* ILR30 */
220 case 0x98: /* ILR31 */
221 i = (offset - 0x1c) >> 2;
222 return (bank->priority[i] << 2) |
223 (((bank->sens_edge >> i) & 1) << 1) |
224 ((bank->fiq >> i) & 1);
234 static void omap_inth_write(void *opaque, hwaddr addr,
235 uint64_t value, unsigned size)
237 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
238 int i, offset = addr;
239 int bank_no = offset >> 8;
240 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
245 /* Important: ignore the clearing if the IRQ is level-triggered and
246 the input bit is 1 */
247 bank->irqs &= value | (bank->inputs & bank->sens_edge);
252 omap_inth_update(s, 0);
253 omap_inth_update(s, 1);
256 case 0x10: /* SIR_IRQ_CODE */
257 case 0x14: /* SIR_FIQ_CODE */
261 case 0x18: /* CONTROL_REG */
265 qemu_set_irq(s->parent_intr[1], 0);
267 omap_inth_update(s, 1);
270 qemu_set_irq(s->parent_intr[0], 0);
272 omap_inth_update(s, 0);
276 case 0x1c: /* ILR0 */
277 case 0x20: /* ILR1 */
278 case 0x24: /* ILR2 */
279 case 0x28: /* ILR3 */
280 case 0x2c: /* ILR4 */
281 case 0x30: /* ILR5 */
282 case 0x34: /* ILR6 */
283 case 0x38: /* ILR7 */
284 case 0x3c: /* ILR8 */
285 case 0x40: /* ILR9 */
286 case 0x44: /* ILR10 */
287 case 0x48: /* ILR11 */
288 case 0x4c: /* ILR12 */
289 case 0x50: /* ILR13 */
290 case 0x54: /* ILR14 */
291 case 0x58: /* ILR15 */
292 case 0x5c: /* ILR16 */
293 case 0x60: /* ILR17 */
294 case 0x64: /* ILR18 */
295 case 0x68: /* ILR19 */
296 case 0x6c: /* ILR20 */
297 case 0x70: /* ILR21 */
298 case 0x74: /* ILR22 */
299 case 0x78: /* ILR23 */
300 case 0x7c: /* ILR24 */
301 case 0x80: /* ILR25 */
302 case 0x84: /* ILR26 */
303 case 0x88: /* ILR27 */
304 case 0x8c: /* ILR28 */
305 case 0x90: /* ILR29 */
306 case 0x94: /* ILR30 */
307 case 0x98: /* ILR31 */
308 i = (offset - 0x1c) >> 2;
309 bank->priority[i] = (value >> 2) & 0x1f;
310 bank->sens_edge &= ~(1 << i);
311 bank->sens_edge |= ((value >> 1) & 1) << i;
312 bank->fiq &= ~(1 << i);
313 bank->fiq |= (value & 1) << i;
317 for (i = 0; i < 32; i ++)
318 if (value & (1 << i)) {
319 omap_set_intr(s, 32 * bank_no + i, 1);
327 static const MemoryRegionOps omap_inth_mem_ops = {
328 .read = omap_inth_read,
329 .write = omap_inth_write,
330 .endianness = DEVICE_NATIVE_ENDIAN,
332 .min_access_size = 4,
333 .max_access_size = 4,
337 static void omap_inth_reset(DeviceState *dev)
339 struct omap_intr_handler_s *s = OMAP_INTC(dev);
342 for (i = 0; i < s->nbanks; ++i){
343 s->bank[i].irqs = 0x00000000;
344 s->bank[i].mask = 0xffffffff;
345 s->bank[i].sens_edge = 0x00000000;
346 s->bank[i].fiq = 0x00000000;
347 s->bank[i].inputs = 0x00000000;
348 s->bank[i].swi = 0x00000000;
349 memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));
352 s->bank[i].sens_edge = 0xffffffff;
362 qemu_set_irq(s->parent_intr[0], 0);
363 qemu_set_irq(s->parent_intr[1], 0);
366 static int omap_intc_init(SysBusDevice *sbd)
368 DeviceState *dev = DEVICE(sbd);
369 struct omap_intr_handler_s *s = OMAP_INTC(dev);
372 error_report("omap-intc: clk not connected");
376 sysbus_init_irq(sbd, &s->parent_intr[0]);
377 sysbus_init_irq(sbd, &s->parent_intr[1]);
378 qdev_init_gpio_in(dev, omap_set_intr, s->nbanks * 32);
379 memory_region_init_io(&s->mmio, OBJECT(s), &omap_inth_mem_ops, s,
380 "omap-intc", s->size);
381 sysbus_init_mmio(sbd, &s->mmio);
385 static Property omap_intc_properties[] = {
386 DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
387 DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk),
388 DEFINE_PROP_END_OF_LIST(),
391 static void omap_intc_class_init(ObjectClass *klass, void *data)
393 DeviceClass *dc = DEVICE_CLASS(klass);
394 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
396 k->init = omap_intc_init;
397 dc->reset = omap_inth_reset;
398 dc->props = omap_intc_properties;
399 /* Reason: pointer property "clk" */
400 dc->cannot_instantiate_with_device_add_yet = true;
403 static const TypeInfo omap_intc_info = {
405 .parent = TYPE_OMAP_INTC,
406 .class_init = omap_intc_class_init,
409 static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
412 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
414 int bank_no, line_no;
415 struct omap_intr_handler_bank_s *bank = NULL;
417 if ((offset & 0xf80) == 0x80) {
418 bank_no = (offset & 0x60) >> 5;
419 if (bank_no < s->nbanks) {
421 bank = &s->bank[bank_no];
429 case 0x00: /* INTC_REVISION */
432 case 0x10: /* INTC_SYSCONFIG */
433 return (s->autoidle >> 2) & 1;
435 case 0x14: /* INTC_SYSSTATUS */
436 return 1; /* RESETDONE */
438 case 0x40: /* INTC_SIR_IRQ */
439 return s->sir_intr[0];
441 case 0x44: /* INTC_SIR_FIQ */
442 return s->sir_intr[1];
444 case 0x48: /* INTC_CONTROL */
445 return (!s->mask) << 2; /* GLOBALMASK */
447 case 0x4c: /* INTC_PROTECTION */
450 case 0x50: /* INTC_IDLE */
451 return s->autoidle & 3;
453 /* Per-bank registers */
454 case 0x80: /* INTC_ITR */
457 case 0x84: /* INTC_MIR */
460 case 0x88: /* INTC_MIR_CLEAR */
461 case 0x8c: /* INTC_MIR_SET */
464 case 0x90: /* INTC_ISR_SET */
467 case 0x94: /* INTC_ISR_CLEAR */
470 case 0x98: /* INTC_PENDING_IRQ */
471 return bank->irqs & ~bank->mask & ~bank->fiq;
473 case 0x9c: /* INTC_PENDING_FIQ */
474 return bank->irqs & ~bank->mask & bank->fiq;
476 /* Per-line registers */
477 case 0x100 ... 0x300: /* INTC_ILR */
478 bank_no = (offset - 0x100) >> 7;
479 if (bank_no > s->nbanks)
481 bank = &s->bank[bank_no];
482 line_no = (offset & 0x7f) >> 2;
483 return (bank->priority[line_no] << 2) |
484 ((bank->fiq >> line_no) & 1);
490 static void omap2_inth_write(void *opaque, hwaddr addr,
491 uint64_t value, unsigned size)
493 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
495 int bank_no, line_no;
496 struct omap_intr_handler_bank_s *bank = NULL;
498 if ((offset & 0xf80) == 0x80) {
499 bank_no = (offset & 0x60) >> 5;
500 if (bank_no < s->nbanks) {
502 bank = &s->bank[bank_no];
510 case 0x10: /* INTC_SYSCONFIG */
512 s->autoidle |= (value & 1) << 2;
513 if (value & 2) { /* SOFTRESET */
514 omap_inth_reset(DEVICE(s));
518 case 0x48: /* INTC_CONTROL */
519 s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */
520 if (value & 2) { /* NEWFIQAGR */
521 qemu_set_irq(s->parent_intr[1], 0);
523 omap_inth_update(s, 1);
525 if (value & 1) { /* NEWIRQAGR */
526 qemu_set_irq(s->parent_intr[0], 0);
528 omap_inth_update(s, 0);
532 case 0x4c: /* INTC_PROTECTION */
533 /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
534 * for every register, see Chapter 3 and 4 for privileged mode. */
536 fprintf(stderr, "%s: protection mode enable attempt\n",
540 case 0x50: /* INTC_IDLE */
542 s->autoidle |= value & 3;
545 /* Per-bank registers */
546 case 0x84: /* INTC_MIR */
548 omap_inth_update(s, 0);
549 omap_inth_update(s, 1);
552 case 0x88: /* INTC_MIR_CLEAR */
553 bank->mask &= ~value;
554 omap_inth_update(s, 0);
555 omap_inth_update(s, 1);
558 case 0x8c: /* INTC_MIR_SET */
562 case 0x90: /* INTC_ISR_SET */
563 bank->irqs |= bank->swi |= value;
564 omap_inth_update(s, 0);
565 omap_inth_update(s, 1);
568 case 0x94: /* INTC_ISR_CLEAR */
570 bank->irqs = bank->swi & bank->inputs;
573 /* Per-line registers */
574 case 0x100 ... 0x300: /* INTC_ILR */
575 bank_no = (offset - 0x100) >> 7;
576 if (bank_no > s->nbanks)
578 bank = &s->bank[bank_no];
579 line_no = (offset & 0x7f) >> 2;
580 bank->priority[line_no] = (value >> 2) & 0x3f;
581 bank->fiq &= ~(1 << line_no);
582 bank->fiq |= (value & 1) << line_no;
585 case 0x00: /* INTC_REVISION */
586 case 0x14: /* INTC_SYSSTATUS */
587 case 0x40: /* INTC_SIR_IRQ */
588 case 0x44: /* INTC_SIR_FIQ */
589 case 0x80: /* INTC_ITR */
590 case 0x98: /* INTC_PENDING_IRQ */
591 case 0x9c: /* INTC_PENDING_FIQ */
598 static const MemoryRegionOps omap2_inth_mem_ops = {
599 .read = omap2_inth_read,
600 .write = omap2_inth_write,
601 .endianness = DEVICE_NATIVE_ENDIAN,
603 .min_access_size = 4,
604 .max_access_size = 4,
608 static int omap2_intc_init(SysBusDevice *sbd)
610 DeviceState *dev = DEVICE(sbd);
611 struct omap_intr_handler_s *s = OMAP_INTC(dev);
614 error_report("omap2-intc: iclk not connected");
618 error_report("omap2-intc: fclk not connected");
623 sysbus_init_irq(sbd, &s->parent_intr[0]);
624 sysbus_init_irq(sbd, &s->parent_intr[1]);
625 qdev_init_gpio_in(dev, omap_set_intr_noedge, s->nbanks * 32);
626 memory_region_init_io(&s->mmio, OBJECT(s), &omap2_inth_mem_ops, s,
627 "omap2-intc", 0x1000);
628 sysbus_init_mmio(sbd, &s->mmio);
632 static Property omap2_intc_properties[] = {
633 DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
635 DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk),
636 DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk),
637 DEFINE_PROP_END_OF_LIST(),
640 static void omap2_intc_class_init(ObjectClass *klass, void *data)
642 DeviceClass *dc = DEVICE_CLASS(klass);
643 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
645 k->init = omap2_intc_init;
646 dc->reset = omap_inth_reset;
647 dc->props = omap2_intc_properties;
648 /* Reason: pointer property "iclk", "fclk" */
649 dc->cannot_instantiate_with_device_add_yet = true;
652 static const TypeInfo omap2_intc_info = {
653 .name = "omap2-intc",
654 .parent = TYPE_OMAP_INTC,
655 .class_init = omap2_intc_class_init,
658 static const TypeInfo omap_intc_type_info = {
659 .name = TYPE_OMAP_INTC,
660 .parent = TYPE_SYS_BUS_DEVICE,
661 .instance_size = sizeof(struct omap_intr_handler_s),
665 static void omap_intc_register_types(void)
667 type_register_static(&omap_intc_type_info);
668 type_register_static(&omap_intc_info);
669 type_register_static(&omap2_intc_info);
672 type_init(omap_intc_register_types)