2 * QEMU IDE Emulation: MacIO support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/ppc/mac.h"
28 #include "hw/ppc/mac_dbdma.h"
29 #include "sysemu/block-backend.h"
30 #include "sysemu/dma.h"
32 #include <hw/ide/internal.h>
35 // #define DEBUG_MACIO
38 static const int debug_macio = 1;
40 static const int debug_macio = 0;
43 #define MACIO_DPRINTF(fmt, ...) do { \
45 printf(fmt , ## __VA_ARGS__); \
50 /***********************************************************/
51 /* MacIO based PowerPC IDE */
53 #define MACIO_PAGE_SIZE 4096
56 * Unaligned DMA read/write access functions required for OS X/Darwin which
57 * don't perform DMA transactions on sector boundaries. These functions are
58 * modelled on bdrv_co_do_preadv()/bdrv_co_do_pwritev() and so should be
59 * easy to remove if the unaligned block APIs are ever exposed.
62 static void pmac_dma_read(BlockBackend *blk,
63 int64_t offset, unsigned int bytes,
64 void (*cb)(void *opaque, int ret), void *opaque)
66 DBDMA_io *io = opaque;
67 MACIOIDEState *m = io->opaque;
68 IDEState *s = idebus_active_if(&m->bus);
69 dma_addr_t dma_addr, dma_len;
73 uint64_t align = BDRV_SECTOR_SIZE;
74 size_t head_bytes, tail_bytes;
76 qemu_iovec_destroy(&io->iov);
77 qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
79 sector_num = (offset >> 9);
80 nsector = (io->len >> 9);
82 MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx ",0x%x): "
83 "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
88 mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
89 DMA_DIRECTION_FROM_DEVICE);
91 if (offset & (align - 1)) {
92 head_bytes = offset & (align - 1);
94 MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64 ", "
95 "discarding %zu bytes\n", sector_num, head_bytes);
97 qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
99 bytes += offset & (align - 1);
100 offset = offset & ~(align - 1);
103 qemu_iovec_add(&io->iov, mem, io->len);
105 if ((offset + bytes) & (align - 1)) {
106 tail_bytes = (offset + bytes) & (align - 1);
108 MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64 ", "
109 "discarding bytes %zu\n", sector_num, tail_bytes);
111 qemu_iovec_add(&io->iov, &io->tail_remainder, align - tail_bytes);
112 bytes = ROUND_UP(bytes, align);
115 s->io_buffer_size -= io->len;
116 s->io_buffer_index += io->len;
120 MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 " "
121 "nsector: %x\n", (offset >> 9), (bytes >> 9));
123 s->bus->dma->aiocb = blk_aio_readv(blk, (offset >> 9), &io->iov,
124 (bytes >> 9), cb, io);
127 static void pmac_dma_write(BlockBackend *blk,
128 int64_t offset, int bytes,
129 void (*cb)(void *opaque, int ret), void *opaque)
131 DBDMA_io *io = opaque;
132 MACIOIDEState *m = io->opaque;
133 IDEState *s = idebus_active_if(&m->bus);
134 dma_addr_t dma_addr, dma_len;
138 uint64_t align = BDRV_SECTOR_SIZE;
139 size_t head_bytes, tail_bytes;
140 bool unaligned_head = false, unaligned_tail = false;
142 qemu_iovec_destroy(&io->iov);
143 qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
145 sector_num = (offset >> 9);
146 nsector = (io->len >> 9);
148 MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx ",0x%x): "
149 "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
150 sector_num, nsector);
154 mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
155 DMA_DIRECTION_TO_DEVICE);
157 if (offset & (align - 1)) {
158 head_bytes = offset & (align - 1);
159 sector_num = ((offset & ~(align - 1)) >> 9);
161 MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %"
162 PRId64 "\n", sector_num);
164 blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align);
166 qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
167 qemu_iovec_add(&io->iov, mem, io->len);
169 bytes += offset & (align - 1);
170 offset = offset & ~(align - 1);
172 unaligned_head = true;
175 if ((offset + bytes) & (align - 1)) {
176 tail_bytes = (offset + bytes) & (align - 1);
177 sector_num = (((offset + bytes) & ~(align - 1)) >> 9);
179 MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %"
180 PRId64 "\n", sector_num);
182 blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align);
184 if (!unaligned_head) {
185 qemu_iovec_add(&io->iov, mem, io->len);
188 qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes,
191 bytes = ROUND_UP(bytes, align);
193 unaligned_tail = true;
196 if (!unaligned_head && !unaligned_tail) {
197 qemu_iovec_add(&io->iov, mem, io->len);
200 s->io_buffer_size -= io->len;
201 s->io_buffer_index += io->len;
205 MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 " "
206 "nsector: %x\n", (offset >> 9), (bytes >> 9));
208 s->bus->dma->aiocb = blk_aio_writev(blk, (offset >> 9), &io->iov,
209 (bytes >> 9), cb, io);
212 static void pmac_dma_trim(BlockBackend *blk,
213 int64_t offset, int bytes,
214 void (*cb)(void *opaque, int ret), void *opaque)
216 DBDMA_io *io = opaque;
217 MACIOIDEState *m = io->opaque;
218 IDEState *s = idebus_active_if(&m->bus);
219 dma_addr_t dma_addr, dma_len;
222 qemu_iovec_destroy(&io->iov);
223 qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
227 mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
228 DMA_DIRECTION_TO_DEVICE);
230 qemu_iovec_add(&io->iov, mem, io->len);
231 s->io_buffer_size -= io->len;
232 s->io_buffer_index += io->len;
235 s->bus->dma->aiocb = ide_issue_trim(blk, (offset >> 9), &io->iov,
236 (bytes >> 9), cb, io);
239 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
241 DBDMA_io *io = opaque;
242 MACIOIDEState *m = io->opaque;
243 IDEState *s = idebus_active_if(&m->bus);
246 MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
249 MACIO_DPRINTF("DMA error: %d\n", ret);
250 ide_atapi_io_error(s, ret);
254 if (!m->dma_active) {
255 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
256 s->nsector, io->len, s->status);
257 /* data not ready yet, wait for the channel to get restarted */
258 io->processing = false;
262 if (s->io_buffer_size <= 0) {
263 MACIO_DPRINTF("End of IDE transfer\n");
265 m->dma_active = false;
270 MACIO_DPRINTF("End of DMA transfer\n");
275 /* Non-block ATAPI transfer - just copy to RAM */
276 s->io_buffer_size = MIN(s->io_buffer_size, io->len);
277 cpu_physical_memory_write(io->addr, s->io_buffer, s->io_buffer_size);
279 m->dma_active = false;
283 /* Calculate current offset */
284 offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
286 pmac_dma_read(s->blk, offset, io->len, pmac_ide_atapi_transfer_cb, io);
291 block_acct_failed(blk_get_stats(s->blk), &s->acct);
293 block_acct_done(blk_get_stats(s->blk), &s->acct);
296 ide_set_inactive(s, false);
300 static void pmac_ide_transfer_cb(void *opaque, int ret)
302 DBDMA_io *io = opaque;
303 MACIOIDEState *m = io->opaque;
304 IDEState *s = idebus_active_if(&m->bus);
307 MACIO_DPRINTF("pmac_ide_transfer_cb\n");
310 MACIO_DPRINTF("DMA error: %d\n", ret);
315 if (!m->dma_active) {
316 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
317 s->nsector, io->len, s->status);
318 /* data not ready yet, wait for the channel to get restarted */
319 io->processing = false;
323 if (s->io_buffer_size <= 0) {
324 MACIO_DPRINTF("End of IDE transfer\n");
325 s->status = READY_STAT | SEEK_STAT;
327 m->dma_active = false;
332 MACIO_DPRINTF("End of DMA transfer\n");
336 /* Calculate number of sectors */
337 offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
339 switch (s->dma_cmd) {
341 pmac_dma_read(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
344 pmac_dma_write(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
347 pmac_dma_trim(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
356 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
358 block_acct_failed(blk_get_stats(s->blk), &s->acct);
360 block_acct_done(blk_get_stats(s->blk), &s->acct);
364 ide_set_inactive(s, false);
368 static void pmac_ide_transfer(DBDMA_io *io)
370 MACIOIDEState *m = io->opaque;
371 IDEState *s = idebus_active_if(&m->bus);
375 if (s->drive_kind == IDE_CD) {
376 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
379 pmac_ide_atapi_transfer_cb(io, 0);
383 switch (s->dma_cmd) {
385 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
389 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
396 pmac_ide_transfer_cb(io, 0);
399 static void pmac_ide_flush(DBDMA_io *io)
401 MACIOIDEState *m = io->opaque;
402 IDEState *s = idebus_active_if(&m->bus);
404 if (s->bus->dma->aiocb) {
409 /* PowerMac IDE memory IO */
410 static void pmac_ide_writeb (void *opaque,
411 hwaddr addr, uint32_t val)
413 MACIOIDEState *d = opaque;
415 addr = (addr & 0xFFF) >> 4;
418 ide_ioport_write(&d->bus, addr, val);
422 ide_cmd_write(&d->bus, 0, val);
429 static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
432 MACIOIDEState *d = opaque;
434 addr = (addr & 0xFFF) >> 4;
437 retval = ide_ioport_read(&d->bus, addr);
441 retval = ide_status_read(&d->bus, 0);
450 static void pmac_ide_writew (void *opaque,
451 hwaddr addr, uint32_t val)
453 MACIOIDEState *d = opaque;
455 addr = (addr & 0xFFF) >> 4;
458 ide_data_writew(&d->bus, 0, val);
462 static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
465 MACIOIDEState *d = opaque;
467 addr = (addr & 0xFFF) >> 4;
469 retval = ide_data_readw(&d->bus, 0);
473 retval = bswap16(retval);
477 static void pmac_ide_writel (void *opaque,
478 hwaddr addr, uint32_t val)
480 MACIOIDEState *d = opaque;
482 addr = (addr & 0xFFF) >> 4;
485 ide_data_writel(&d->bus, 0, val);
489 static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
492 MACIOIDEState *d = opaque;
494 addr = (addr & 0xFFF) >> 4;
496 retval = ide_data_readl(&d->bus, 0);
500 retval = bswap32(retval);
504 static const MemoryRegionOps pmac_ide_ops = {
517 .endianness = DEVICE_NATIVE_ENDIAN,
520 static const VMStateDescription vmstate_pmac = {
523 .minimum_version_id = 0,
524 .fields = (VMStateField[]) {
525 VMSTATE_IDE_BUS(bus, MACIOIDEState),
526 VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
527 VMSTATE_BOOL(dma_active, MACIOIDEState),
528 VMSTATE_END_OF_LIST()
532 static void macio_ide_reset(DeviceState *dev)
534 MACIOIDEState *d = MACIO_IDE(dev);
536 ide_bus_reset(&d->bus);
539 static int ide_nop_int(IDEDMA *dma, int x)
544 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
549 static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
550 BlockCompletionFunc *cb)
552 MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
554 s->io_buffer_index = 0;
555 if (s->drive_kind == IDE_CD) {
556 s->io_buffer_size = s->packet_transfer_size;
558 s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
561 MACIO_DPRINTF("\n\n------------ IDE transfer\n");
562 MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
563 s->io_buffer_size, s->io_buffer_index);
564 MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size);
565 MACIO_DPRINTF("-------------------------\n");
567 m->dma_active = true;
568 DBDMA_kick(m->dbdma);
571 static const IDEDMAOps dbdma_ops = {
572 .start_dma = ide_dbdma_start,
573 .prepare_buf = ide_nop_int32,
574 .rw_buf = ide_nop_int,
577 static void macio_ide_realizefn(DeviceState *dev, Error **errp)
579 MACIOIDEState *s = MACIO_IDE(dev);
581 ide_init2(&s->bus, s->irq);
583 /* Register DMA callbacks */
584 s->dma.ops = &dbdma_ops;
585 s->bus.dma = &s->dma;
588 static void macio_ide_initfn(Object *obj)
590 SysBusDevice *d = SYS_BUS_DEVICE(obj);
591 MACIOIDEState *s = MACIO_IDE(obj);
593 ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
594 memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
595 sysbus_init_mmio(d, &s->mem);
596 sysbus_init_irq(d, &s->irq);
597 sysbus_init_irq(d, &s->dma_irq);
600 static void macio_ide_class_init(ObjectClass *oc, void *data)
602 DeviceClass *dc = DEVICE_CLASS(oc);
604 dc->realize = macio_ide_realizefn;
605 dc->reset = macio_ide_reset;
606 dc->vmsd = &vmstate_pmac;
607 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
610 static const TypeInfo macio_ide_type_info = {
611 .name = TYPE_MACIO_IDE,
612 .parent = TYPE_SYS_BUS_DEVICE,
613 .instance_size = sizeof(MACIOIDEState),
614 .instance_init = macio_ide_initfn,
615 .class_init = macio_ide_class_init,
618 static void macio_ide_register_types(void)
620 type_register_static(&macio_ide_type_info);
623 /* hd_table must contain 2 block drivers */
624 void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
628 for (i = 0; i < 2; i++) {
630 ide_create_drive(&s->bus, i, hd_table[i]);
635 void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
638 DBDMA_register_channel(dbdma, channel, s->dma_irq,
639 pmac_ide_transfer, pmac_ide_flush, s);
642 type_init(macio_ide_register_types)