2 * i.MX processors GPIO emulation.
4 * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "hw/gpio/imx_gpio.h"
23 #ifndef DEBUG_IMX_GPIO
24 #define DEBUG_IMX_GPIO 0
27 typedef enum IMXGPIOLevel {
28 IMX_GPIO_LEVEL_LOW = 0,
29 IMX_GPIO_LEVEL_HIGH = 1,
32 #define DPRINTF(fmt, args...) \
34 if (DEBUG_IMX_GPIO) { \
35 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPIO, \
40 static const char *imx_gpio_reg_name(uint32_t reg)
64 static void imx_gpio_update_int(IMXGPIOState *s)
66 if (s->has_upper_pin_irq) {
67 qemu_set_irq(s->irq[0], (s->isr & s->imr & 0x0000FFFF) ? 1 : 0);
68 qemu_set_irq(s->irq[1], (s->isr & s->imr & 0xFFFF0000) ? 1 : 0);
70 qemu_set_irq(s->irq[0], (s->isr & s->imr) ? 1 : 0);
74 static void imx_gpio_set_int_line(IMXGPIOState *s, int line, IMXGPIOLevel level)
76 /* if this signal isn't configured as an input signal, nothing to do */
77 if (!extract32(s->gdir, line, 1)) {
81 /* When set, EDGE_SEL overrides the ICR config */
82 if (extract32(s->edge_sel, line, 1)) {
83 /* we detect interrupt on rising and falling edge */
84 if (extract32(s->psr, line, 1) != level) {
86 s->isr = deposit32(s->isr, line, 1, 1);
88 } else if (extract64(s->icr, 2*line + 1, 1)) {
89 /* interrupt is edge sensitive */
90 if (extract32(s->psr, line, 1) != level) {
92 if (extract64(s->icr, 2*line, 1) != level) {
93 s->isr = deposit32(s->isr, line, 1, 1);
97 /* interrupt is level sensitive */
98 if (extract64(s->icr, 2*line, 1) == level) {
99 s->isr = deposit32(s->isr, line, 1, 1);
104 static void imx_gpio_set(void *opaque, int line, int level)
106 IMXGPIOState *s = IMX_GPIO(opaque);
107 IMXGPIOLevel imx_level = level ? IMX_GPIO_LEVEL_HIGH : IMX_GPIO_LEVEL_LOW;
109 imx_gpio_set_int_line(s, line, imx_level);
111 /* this is an input signal, so set PSR */
112 s->psr = deposit32(s->psr, line, 1, imx_level);
114 imx_gpio_update_int(s);
117 static void imx_gpio_set_all_int_lines(IMXGPIOState *s)
121 for (i = 0; i < IMX_GPIO_PIN_COUNT; i++) {
122 IMXGPIOLevel imx_level = extract32(s->psr, i, 1);
123 imx_gpio_set_int_line(s, i, imx_level);
126 imx_gpio_update_int(s);
129 static inline void imx_gpio_set_all_output_lines(IMXGPIOState *s)
133 for (i = 0; i < IMX_GPIO_PIN_COUNT; i++) {
135 * if the line is set as output, then forward the line
138 if (extract32(s->gdir, i, 1) && s->output[i]) {
139 qemu_set_irq(s->output[i], extract32(s->dr, i, 1));
144 static uint64_t imx_gpio_read(void *opaque, hwaddr offset, unsigned size)
146 IMXGPIOState *s = IMX_GPIO(opaque);
147 uint32_t reg_value = 0;
152 * depending on the "line" configuration, the bit values
153 * are coming either from DR or PSR
155 reg_value = (s->dr & s->gdir) | (s->psr & ~s->gdir);
163 reg_value = s->psr & ~s->gdir;
167 reg_value = extract64(s->icr, 0, 32);
171 reg_value = extract64(s->icr, 32, 32);
183 if (s->has_edge_sel) {
184 reg_value = s->edge_sel;
186 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
187 "present on this version of GPIO device\n",
188 TYPE_IMX_GPIO, __func__);
193 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
194 HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
198 DPRINTF("(%s) = 0x%" PRIx32 "\n", imx_gpio_reg_name(offset), reg_value);
203 static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
206 IMXGPIOState *s = IMX_GPIO(opaque);
208 DPRINTF("(%s, value = 0x%" PRIx32 ")\n", imx_gpio_reg_name(offset),
214 imx_gpio_set_all_output_lines(s);
219 imx_gpio_set_all_output_lines(s);
220 imx_gpio_set_all_int_lines(s);
224 s->icr = deposit64(s->icr, 0, 32, value);
225 imx_gpio_set_all_int_lines(s);
229 s->icr = deposit64(s->icr, 32, 32, value);
230 imx_gpio_set_all_int_lines(s);
235 imx_gpio_update_int(s);
240 imx_gpio_set_all_int_lines(s);
244 if (s->has_edge_sel) {
246 imx_gpio_set_all_int_lines(s);
248 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
249 "present on this version of GPIO device\n",
250 TYPE_IMX_GPIO, __func__);
255 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
256 HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
263 static const MemoryRegionOps imx_gpio_ops = {
264 .read = imx_gpio_read,
265 .write = imx_gpio_write,
266 .valid.min_access_size = 4,
267 .valid.max_access_size = 4,
268 .endianness = DEVICE_NATIVE_ENDIAN,
271 static const VMStateDescription vmstate_imx_gpio = {
272 .name = TYPE_IMX_GPIO,
274 .minimum_version_id = 1,
275 .minimum_version_id_old = 1,
276 .fields = (VMStateField[]) {
277 VMSTATE_UINT32(dr, IMXGPIOState),
278 VMSTATE_UINT32(gdir, IMXGPIOState),
279 VMSTATE_UINT32(psr, IMXGPIOState),
280 VMSTATE_UINT64(icr, IMXGPIOState),
281 VMSTATE_UINT32(imr, IMXGPIOState),
282 VMSTATE_UINT32(isr, IMXGPIOState),
283 VMSTATE_BOOL(has_edge_sel, IMXGPIOState),
284 VMSTATE_UINT32(edge_sel, IMXGPIOState),
285 VMSTATE_END_OF_LIST()
289 static Property imx_gpio_properties[] = {
290 DEFINE_PROP_BOOL("has-edge-sel", IMXGPIOState, has_edge_sel, true),
291 DEFINE_PROP_BOOL("has-upper-pin-irq", IMXGPIOState, has_upper_pin_irq,
293 DEFINE_PROP_END_OF_LIST(),
296 static void imx_gpio_reset(DeviceState *dev)
298 IMXGPIOState *s = IMX_GPIO(dev);
308 imx_gpio_set_all_output_lines(s);
309 imx_gpio_update_int(s);
312 static void imx_gpio_realize(DeviceState *dev, Error **errp)
314 IMXGPIOState *s = IMX_GPIO(dev);
316 memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpio_ops, s,
317 TYPE_IMX_GPIO, IMX_GPIO_MEM_SIZE);
319 qdev_init_gpio_in(DEVICE(s), imx_gpio_set, IMX_GPIO_PIN_COUNT);
320 qdev_init_gpio_out(DEVICE(s), s->output, IMX_GPIO_PIN_COUNT);
322 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[0]);
323 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[1]);
324 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
327 static void imx_gpio_class_init(ObjectClass *klass, void *data)
329 DeviceClass *dc = DEVICE_CLASS(klass);
331 dc->realize = imx_gpio_realize;
332 dc->reset = imx_gpio_reset;
333 dc->props = imx_gpio_properties;
334 dc->vmsd = &vmstate_imx_gpio;
335 dc->desc = "i.MX GPIO controller";
338 static const TypeInfo imx_gpio_info = {
339 .name = TYPE_IMX_GPIO,
340 .parent = TYPE_SYS_BUS_DEVICE,
341 .instance_size = sizeof(IMXGPIOState),
342 .class_init = imx_gpio_class_init,
345 static void imx_gpio_register_types(void)
347 type_register_static(&imx_gpio_info);
350 type_init(imx_gpio_register_types)