2 * Arm PrimeCell PL110 Color LCD Controller
4 * Copyright (c) 2005-2009 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GNU LGPL
10 #include "hw/sysbus.h"
11 #include "ui/console.h"
12 #include "framebuffer.h"
13 #include "ui/pixel_ops.h"
15 #define PL110_CR_EN 0x001
16 #define PL110_CR_BGR 0x100
17 #define PL110_CR_BEBO 0x200
18 #define PL110_CR_BEPO 0x400
19 #define PL110_CR_PWR 0x800
29 BPP_16_565, /* PL111 only */
30 BPP_12 /* PL111 only */
34 /* The Versatile/PB uses a slightly modified PL110 controller. */
42 #define TYPE_PL110 "pl110"
43 #define PL110(obj) OBJECT_CHECK(PL110State, (obj), TYPE_PL110)
45 typedef struct PL110State {
46 SysBusDevice parent_obj;
49 MemoryRegionSection fbsection;
61 enum pl110_bppmode bpp;
64 uint32_t palette[256];
65 uint32_t raw_palette[128];
69 static int vmstate_pl110_post_load(void *opaque, int version_id);
71 static const VMStateDescription vmstate_pl110 = {
74 .minimum_version_id = 1,
75 .post_load = vmstate_pl110_post_load,
76 .fields = (VMStateField[]) {
77 VMSTATE_INT32(version, PL110State),
78 VMSTATE_UINT32_ARRAY(timing, PL110State, 4),
79 VMSTATE_UINT32(cr, PL110State),
80 VMSTATE_UINT32(upbase, PL110State),
81 VMSTATE_UINT32(lpbase, PL110State),
82 VMSTATE_UINT32(int_status, PL110State),
83 VMSTATE_UINT32(int_mask, PL110State),
84 VMSTATE_INT32(cols, PL110State),
85 VMSTATE_INT32(rows, PL110State),
86 VMSTATE_UINT32(bpp, PL110State),
87 VMSTATE_INT32(invalidate, PL110State),
88 VMSTATE_UINT32_ARRAY(palette, PL110State, 256),
89 VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128),
90 VMSTATE_UINT32_V(mux_ctrl, PL110State, 2),
95 static const unsigned char pl110_id[] =
96 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
98 static const unsigned char pl111_id[] = {
99 0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
103 /* Indexed by pl110_version */
104 static const unsigned char *idregs[] = {
106 /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board
107 * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware
108 * itself has the same ID values as a stock PL110, and guests (in
109 * particular Linux) rely on this. We emulate what the hardware does,
110 * rather than what the docs claim it ought to do.
117 #include "pl110_template.h"
119 #include "pl110_template.h"
121 #include "pl110_template.h"
123 #include "pl110_template.h"
125 #include "pl110_template.h"
127 static int pl110_enabled(PL110State *s)
129 return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
132 static void pl110_update_display(void *opaque)
134 PL110State *s = (PL110State *)opaque;
136 DisplaySurface *surface = qemu_console_surface(s->con);
145 if (!pl110_enabled(s)) {
149 sbd = SYS_BUS_DEVICE(s);
151 switch (surface_bits_per_pixel(surface)) {
155 fntable = pl110_draw_fn_8;
159 fntable = pl110_draw_fn_15;
163 fntable = pl110_draw_fn_16;
167 fntable = pl110_draw_fn_24;
171 fntable = pl110_draw_fn_32;
175 fprintf(stderr, "pl110: Bad color depth\n");
178 if (s->cr & PL110_CR_BGR)
183 if ((s->version != PL111) && (s->bpp == BPP_16)) {
184 /* The PL110's native 16 bit mode is 5551; however
185 * most boards with a PL110 implement an external
186 * mux which allows bits to be reshuffled to give
187 * 565 format. The mux is typically controlled by
188 * an external system register.
189 * This is controlled by a GPIO input pin
190 * so boards can wire it up to their register.
192 * The PL111 straightforwardly implements both
193 * 5551 and 565 under control of the bpp field
194 * in the LCDControl register.
196 switch (s->mux_ctrl) {
197 case 3: /* 565 BGR */
198 bpp_offset = (BPP_16_565 - BPP_16);
202 case 0: /* 888; also if we have loaded vmstate from an old version */
203 case 2: /* 565 RGB */
205 /* treat as 565 but honour BGR bit */
206 bpp_offset += (BPP_16_565 - BPP_16);
211 if (s->cr & PL110_CR_BEBO)
212 fn = fntable[s->bpp + 8 + bpp_offset];
213 else if (s->cr & PL110_CR_BEPO)
214 fn = fntable[s->bpp + 16 + bpp_offset];
216 fn = fntable[s->bpp + bpp_offset];
240 dest_width *= s->cols;
243 framebuffer_update_memory_section(&s->fbsection,
244 sysbus_address_space(sbd),
249 framebuffer_update_display(surface, &s->fbsection,
251 src_width, dest_width, 0,
257 dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1);
262 static void pl110_invalidate_display(void * opaque)
264 PL110State *s = (PL110State *)opaque;
266 if (pl110_enabled(s)) {
267 qemu_console_resize(s->con, s->cols, s->rows);
271 static void pl110_update_palette(PL110State *s, int n)
273 DisplaySurface *surface = qemu_console_surface(s->con);
276 unsigned int r, g, b;
278 raw = s->raw_palette[n];
280 for (i = 0; i < 2; i++) {
281 r = (raw & 0x1f) << 3;
283 g = (raw & 0x1f) << 3;
285 b = (raw & 0x1f) << 3;
286 /* The I bit is ignored. */
288 switch (surface_bits_per_pixel(surface)) {
290 s->palette[n] = rgb_to_pixel8(r, g, b);
293 s->palette[n] = rgb_to_pixel15(r, g, b);
296 s->palette[n] = rgb_to_pixel16(r, g, b);
300 s->palette[n] = rgb_to_pixel32(r, g, b);
307 static void pl110_resize(PL110State *s, int width, int height)
309 if (width != s->cols || height != s->rows) {
310 if (pl110_enabled(s)) {
311 qemu_console_resize(s->con, width, height);
318 /* Update interrupts. */
319 static void pl110_update(PL110State *s)
321 /* TODO: Implement interrupts. */
324 static uint64_t pl110_read(void *opaque, hwaddr offset,
327 PL110State *s = (PL110State *)opaque;
329 if (offset >= 0xfe0 && offset < 0x1000) {
330 return idregs[s->version][(offset - 0xfe0) >> 2];
332 if (offset >= 0x200 && offset < 0x400) {
333 return s->raw_palette[(offset - 0x200) >> 2];
335 switch (offset >> 2) {
336 case 0: /* LCDTiming0 */
338 case 1: /* LCDTiming1 */
340 case 2: /* LCDTiming2 */
342 case 3: /* LCDTiming3 */
344 case 4: /* LCDUPBASE */
346 case 5: /* LCDLPBASE */
348 case 6: /* LCDIMSC */
349 if (s->version != PL110) {
353 case 7: /* LCDControl */
354 if (s->version != PL110) {
359 return s->int_status;
361 return s->int_status & s->int_mask;
362 case 11: /* LCDUPCURR */
363 /* TODO: Implement vertical refresh. */
365 case 12: /* LCDLPCURR */
368 qemu_log_mask(LOG_GUEST_ERROR,
369 "pl110_read: Bad offset %x\n", (int)offset);
374 static void pl110_write(void *opaque, hwaddr offset,
375 uint64_t val, unsigned size)
377 PL110State *s = (PL110State *)opaque;
380 /* For simplicity invalidate the display whenever a control register
383 if (offset >= 0x200 && offset < 0x400) {
385 n = (offset - 0x200) >> 2;
386 s->raw_palette[(offset - 0x200) >> 2] = val;
387 pl110_update_palette(s, n);
390 switch (offset >> 2) {
391 case 0: /* LCDTiming0 */
393 n = ((val & 0xfc) + 4) * 4;
394 pl110_resize(s, n, s->rows);
396 case 1: /* LCDTiming1 */
398 n = (val & 0x3ff) + 1;
399 pl110_resize(s, s->cols, n);
401 case 2: /* LCDTiming2 */
404 case 3: /* LCDTiming3 */
407 case 4: /* LCDUPBASE */
410 case 5: /* LCDLPBASE */
413 case 6: /* LCDIMSC */
414 if (s->version != PL110) {
421 case 7: /* LCDControl */
422 if (s->version != PL110) {
427 s->bpp = (val >> 1) & 7;
428 if (pl110_enabled(s)) {
429 qemu_console_resize(s->con, s->cols, s->rows);
432 case 10: /* LCDICR */
433 s->int_status &= ~val;
437 qemu_log_mask(LOG_GUEST_ERROR,
438 "pl110_write: Bad offset %x\n", (int)offset);
442 static const MemoryRegionOps pl110_ops = {
444 .write = pl110_write,
445 .endianness = DEVICE_NATIVE_ENDIAN,
448 static void pl110_mux_ctrl_set(void *opaque, int line, int level)
450 PL110State *s = (PL110State *)opaque;
454 static int vmstate_pl110_post_load(void *opaque, int version_id)
456 PL110State *s = opaque;
457 /* Make sure we redraw, and at the right size */
458 pl110_invalidate_display(s);
462 static const GraphicHwOps pl110_gfx_ops = {
463 .invalidate = pl110_invalidate_display,
464 .gfx_update = pl110_update_display,
467 static int pl110_initfn(SysBusDevice *sbd)
469 DeviceState *dev = DEVICE(sbd);
470 PL110State *s = PL110(dev);
472 memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);
473 sysbus_init_mmio(sbd, &s->iomem);
474 sysbus_init_irq(sbd, &s->irq);
475 qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1);
476 s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s);
480 static void pl110_init(Object *obj)
482 PL110State *s = PL110(obj);
487 static void pl110_versatile_init(Object *obj)
489 PL110State *s = PL110(obj);
491 s->version = PL110_VERSATILE;
494 static void pl111_init(Object *obj)
496 PL110State *s = PL110(obj);
501 static void pl110_class_init(ObjectClass *klass, void *data)
503 DeviceClass *dc = DEVICE_CLASS(klass);
504 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
506 k->init = pl110_initfn;
507 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
508 dc->vmsd = &vmstate_pl110;
511 static const TypeInfo pl110_info = {
513 .parent = TYPE_SYS_BUS_DEVICE,
514 .instance_size = sizeof(PL110State),
515 .instance_init = pl110_init,
516 .class_init = pl110_class_init,
519 static const TypeInfo pl110_versatile_info = {
520 .name = "pl110_versatile",
521 .parent = TYPE_PL110,
522 .instance_init = pl110_versatile_init,
525 static const TypeInfo pl111_info = {
527 .parent = TYPE_PL110,
528 .instance_init = pl111_init,
531 static void pl110_register_types(void)
533 type_register_static(&pl110_info);
534 type_register_static(&pl110_versatile_info);
535 type_register_static(&pl111_info);
538 type_init(pl110_register_types)