4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "hw/char/stm32f2xx_usart.h"
28 #ifndef STM_USART_ERR_DEBUG
29 #define STM_USART_ERR_DEBUG 0
32 #define DB_PRINT_L(lvl, fmt, args...) do { \
33 if (STM_USART_ERR_DEBUG >= lvl) { \
34 qemu_log("%s: " fmt, __func__, ## args); \
38 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
40 static int stm32f2xx_usart_can_receive(void *opaque)
42 STM32F2XXUsartState *s = opaque;
44 if (!(s->usart_sr & USART_SR_RXNE)) {
51 static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
53 STM32F2XXUsartState *s = opaque;
57 if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
58 /* USART not enabled - drop the chars */
59 DB_PRINT("Dropping the chars\n");
63 s->usart_sr |= USART_SR_RXNE;
65 if (s->usart_cr1 & USART_CR1_RXNEIE) {
66 qemu_set_irq(s->irq, 1);
69 DB_PRINT("Receiving: %c\n", s->usart_dr);
72 static void stm32f2xx_usart_reset(DeviceState *dev)
74 STM32F2XXUsartState *s = STM32F2XX_USART(dev);
76 s->usart_sr = USART_SR_RESET;
77 s->usart_dr = 0x00000000;
78 s->usart_brr = 0x00000000;
79 s->usart_cr1 = 0x00000000;
80 s->usart_cr2 = 0x00000000;
81 s->usart_cr3 = 0x00000000;
82 s->usart_gtpr = 0x00000000;
84 qemu_set_irq(s->irq, 0);
87 static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
90 STM32F2XXUsartState *s = opaque;
93 DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
97 retvalue = s->usart_sr;
98 s->usart_sr &= ~USART_SR_TC;
100 qemu_chr_accept_input(s->chr);
104 DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
105 s->usart_sr |= USART_SR_TXE;
106 s->usart_sr &= ~USART_SR_RXNE;
108 qemu_chr_accept_input(s->chr);
110 qemu_set_irq(s->irq, 0);
111 return s->usart_dr & 0x3FF;
121 return s->usart_gtpr;
123 qemu_log_mask(LOG_GUEST_ERROR,
124 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
131 static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
132 uint64_t val64, unsigned int size)
134 STM32F2XXUsartState *s = opaque;
135 uint32_t value = val64;
138 DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);
142 if (value <= 0x3FF) {
145 s->usart_sr &= value;
147 if (!(s->usart_sr & USART_SR_RXNE)) {
148 qemu_set_irq(s->irq, 0);
152 if (value < 0xF000) {
155 qemu_chr_fe_write_all(s->chr, &ch, 1);
157 s->usart_sr |= USART_SR_TC;
158 s->usart_sr &= ~USART_SR_TXE;
162 s->usart_brr = value;
165 s->usart_cr1 = value;
166 if (s->usart_cr1 & USART_CR1_RXNEIE &&
167 s->usart_sr & USART_SR_RXNE) {
168 qemu_set_irq(s->irq, 1);
172 s->usart_cr2 = value;
175 s->usart_cr3 = value;
178 s->usart_gtpr = value;
181 qemu_log_mask(LOG_GUEST_ERROR,
182 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
186 static const MemoryRegionOps stm32f2xx_usart_ops = {
187 .read = stm32f2xx_usart_read,
188 .write = stm32f2xx_usart_write,
189 .endianness = DEVICE_NATIVE_ENDIAN,
192 static void stm32f2xx_usart_init(Object *obj)
194 STM32F2XXUsartState *s = STM32F2XX_USART(obj);
196 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
198 memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
199 TYPE_STM32F2XX_USART, 0x2000);
200 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
202 /* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
203 s->chr = qemu_char_get_next_serial();
206 qemu_chr_add_handlers(s->chr, stm32f2xx_usart_can_receive,
207 stm32f2xx_usart_receive, NULL, s);
211 static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
213 DeviceClass *dc = DEVICE_CLASS(klass);
215 dc->reset = stm32f2xx_usart_reset;
216 /* Reason: instance_init() method uses qemu_char_get_next_serial() */
217 dc->cannot_instantiate_with_device_add_yet = true;
220 static const TypeInfo stm32f2xx_usart_info = {
221 .name = TYPE_STM32F2XX_USART,
222 .parent = TYPE_SYS_BUS_DEVICE,
223 .instance_size = sizeof(STM32F2XXUsartState),
224 .instance_init = stm32f2xx_usart_init,
225 .class_init = stm32f2xx_usart_class_init,
228 static void stm32f2xx_usart_register_types(void)
230 type_register_static(&stm32f2xx_usart_info);
233 type_init(stm32f2xx_usart_register_types)