2 * QEMU GRLIB APB UART Emulator
4 * Copyright (c) 2010-2011 AdaCore
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "sysemu/char.h"
31 #define UART_REG_SIZE 20 /* Size of memory mapped registers */
33 /* UART status register fields */
34 #define UART_DATA_READY (1 << 0)
35 #define UART_TRANSMIT_SHIFT_EMPTY (1 << 1)
36 #define UART_TRANSMIT_FIFO_EMPTY (1 << 2)
37 #define UART_BREAK_RECEIVED (1 << 3)
38 #define UART_OVERRUN (1 << 4)
39 #define UART_PARITY_ERROR (1 << 5)
40 #define UART_FRAMING_ERROR (1 << 6)
41 #define UART_TRANSMIT_FIFO_HALF (1 << 7)
42 #define UART_RECEIVE_FIFO_HALF (1 << 8)
43 #define UART_TRANSMIT_FIFO_FULL (1 << 9)
44 #define UART_RECEIVE_FIFO_FULL (1 << 10)
46 /* UART control register fields */
47 #define UART_RECEIVE_ENABLE (1 << 0)
48 #define UART_TRANSMIT_ENABLE (1 << 1)
49 #define UART_RECEIVE_INTERRUPT (1 << 2)
50 #define UART_TRANSMIT_INTERRUPT (1 << 3)
51 #define UART_PARITY_SELECT (1 << 4)
52 #define UART_PARITY_ENABLE (1 << 5)
53 #define UART_FLOW_CONTROL (1 << 6)
54 #define UART_LOOPBACK (1 << 7)
55 #define UART_EXTERNAL_CLOCK (1 << 8)
56 #define UART_RECEIVE_FIFO_INTERRUPT (1 << 9)
57 #define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10)
58 #define UART_FIFO_DEBUG_MODE (1 << 11)
59 #define UART_OUTPUT_ENABLE (1 << 12)
60 #define UART_FIFO_AVAILABLE (1 << 31)
62 /* Memory mapped register offsets */
63 #define DATA_OFFSET 0x00
64 #define STATUS_OFFSET 0x04
65 #define CONTROL_OFFSET 0x08
66 #define SCALER_OFFSET 0x0C /* not supported */
67 #define FIFO_DEBUG_OFFSET 0x10 /* not supported */
69 #define FIFO_LENGTH 1024
71 #define TYPE_GRLIB_APB_UART "grlib,apbuart"
72 #define GRLIB_APB_UART(obj) \
73 OBJECT_CHECK(UART, (obj), TYPE_GRLIB_APB_UART)
76 SysBusDevice parent_obj;
88 char buffer[FIFO_LENGTH];
93 static int uart_data_to_read(UART *uart)
95 return uart->current < uart->len;
98 static char uart_pop(UART *uart)
102 if (uart->len == 0) {
103 uart->status &= ~UART_DATA_READY;
107 ret = uart->buffer[uart->current++];
109 if (uart->current >= uart->len) {
115 if (!uart_data_to_read(uart)) {
116 uart->status &= ~UART_DATA_READY;
122 static void uart_add_to_fifo(UART *uart,
123 const uint8_t *buffer,
126 if (uart->len + length > FIFO_LENGTH) {
129 memcpy(uart->buffer + uart->len, buffer, length);
133 static int grlib_apbuart_can_receive(void *opaque)
137 return FIFO_LENGTH - uart->len;
140 static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size)
144 if (uart->control & UART_RECEIVE_ENABLE) {
145 uart_add_to_fifo(uart, buf, size);
147 uart->status |= UART_DATA_READY;
149 if (uart->control & UART_RECEIVE_INTERRUPT) {
150 qemu_irq_pulse(uart->irq);
155 static void grlib_apbuart_event(void *opaque, int event)
157 trace_grlib_apbuart_event(event);
161 static uint64_t grlib_apbuart_read(void *opaque, hwaddr addr,
171 case DATA_OFFSET + 3: /* when only one byte read */
172 return uart_pop(uart);
179 return uart->control;
186 trace_grlib_apbuart_readl_unknown(addr);
191 static void grlib_apbuart_write(void *opaque, hwaddr addr,
192 uint64_t value, unsigned size)
202 case DATA_OFFSET + 3: /* When only one byte write */
203 /* Transmit when character device available and transmitter enabled */
204 if ((uart->chr) && (uart->control & UART_TRANSMIT_ENABLE)) {
206 qemu_chr_fe_write(uart->chr, &c, 1);
207 /* Generate interrupt */
208 if (uart->control & UART_TRANSMIT_INTERRUPT) {
209 qemu_irq_pulse(uart->irq);
219 uart->control = value;
230 trace_grlib_apbuart_writel_unknown(addr, value);
233 static const MemoryRegionOps grlib_apbuart_ops = {
234 .write = grlib_apbuart_write,
235 .read = grlib_apbuart_read,
236 .endianness = DEVICE_NATIVE_ENDIAN,
239 static int grlib_apbuart_init(SysBusDevice *dev)
241 UART *uart = GRLIB_APB_UART(dev);
243 qemu_chr_add_handlers(uart->chr,
244 grlib_apbuart_can_receive,
245 grlib_apbuart_receive,
249 sysbus_init_irq(dev, &uart->irq);
251 memory_region_init_io(&uart->iomem, OBJECT(uart), &grlib_apbuart_ops, uart,
252 "uart", UART_REG_SIZE);
254 sysbus_init_mmio(dev, &uart->iomem);
259 static void grlib_apbuart_reset(DeviceState *d)
261 UART *uart = GRLIB_APB_UART(d);
263 /* Transmitter FIFO and shift registers are always empty in QEMU */
264 uart->status = UART_TRANSMIT_FIFO_EMPTY | UART_TRANSMIT_SHIFT_EMPTY;
265 /* Everything is off */
267 /* Flush receive FIFO */
272 static Property grlib_apbuart_properties[] = {
273 DEFINE_PROP_CHR("chrdev", UART, chr),
274 DEFINE_PROP_END_OF_LIST(),
277 static void grlib_apbuart_class_init(ObjectClass *klass, void *data)
279 DeviceClass *dc = DEVICE_CLASS(klass);
280 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
282 k->init = grlib_apbuart_init;
283 dc->reset = grlib_apbuart_reset;
284 dc->props = grlib_apbuart_properties;
287 static const TypeInfo grlib_apbuart_info = {
288 .name = TYPE_GRLIB_APB_UART,
289 .parent = TYPE_SYS_BUS_DEVICE,
290 .instance_size = sizeof(UART),
291 .class_init = grlib_apbuart_class_init,
294 static void grlib_apbuart_register_types(void)
296 type_register_static(&grlib_apbuart_info);
299 type_init(grlib_apbuart_register_types)